radeon_screen.c revision d07d1379314c9222ccb955244fa7e56bd4d03d6d
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include "main/glheader.h" 39#include "main/imports.h" 40#include "main/mtypes.h" 41#include "main/framebuffer.h" 42#include "main/renderbuffer.h" 43 44#define STANDALONE_MMIO 45#include "radeon_chipset.h" 46#include "radeon_macros.h" 47#include "radeon_screen.h" 48#include "radeon_buffer.h" 49#if !RADEON_COMMON 50#include "radeon_context.h" 51#include "radeon_span.h" 52#include "radeon_tex.h" 53#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 54#include "r200_context.h" 55#include "r200_ioctl.h" 56#include "r200_span.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_fragprog.h" 61#include "r300_tex.h" 62#include "radeon_span.h" 63#endif 64 65#include "utils.h" 66#include "vblank.h" 67#include "drirenderbuffer.h" 68 69#include "GL/internal/dri_interface.h" 70 71/* Radeon configuration 72 */ 73#include "xmlpool.h" 74#include "radeon_bo_legacy.h" 75#include "radeon_bo_gem.h" 76 77#if !RADEON_COMMON /* R100 */ 78PUBLIC const char __driConfigOptions[] = 79DRI_CONF_BEGIN 80 DRI_CONF_SECTION_PERFORMANCE 81 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 82 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 83 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 84 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 85 DRI_CONF_HYPERZ(false) 86 DRI_CONF_SECTION_END 87 DRI_CONF_SECTION_QUALITY 88 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 89 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 90 DRI_CONF_NO_NEG_LOD_BIAS(false) 91 DRI_CONF_FORCE_S3TC_ENABLE(false) 92 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 93 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 94 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 95 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 96 DRI_CONF_SECTION_END 97 DRI_CONF_SECTION_DEBUG 98 DRI_CONF_NO_RAST(false) 99 DRI_CONF_SECTION_END 100DRI_CONF_END; 101static const GLuint __driNConfigOptions = 14; 102 103#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 104 105PUBLIC const char __driConfigOptions[] = 106DRI_CONF_BEGIN 107 DRI_CONF_SECTION_PERFORMANCE 108 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 109 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 110 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 111 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 112 DRI_CONF_HYPERZ(false) 113 DRI_CONF_SECTION_END 114 DRI_CONF_SECTION_QUALITY 115 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 116 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 117 DRI_CONF_NO_NEG_LOD_BIAS(false) 118 DRI_CONF_FORCE_S3TC_ENABLE(false) 119 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 120 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 121 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 122 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 123 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 124 DRI_CONF_SECTION_END 125 DRI_CONF_SECTION_DEBUG 126 DRI_CONF_NO_RAST(false) 127 DRI_CONF_SECTION_END 128 DRI_CONF_SECTION_SOFTWARE 129 DRI_CONF_NV_VERTEX_PROGRAM(false) 130 DRI_CONF_SECTION_END 131DRI_CONF_END; 132static const GLuint __driNConfigOptions = 16; 133 134extern const struct dri_extension blend_extensions[]; 135extern const struct dri_extension ARB_vp_extension[]; 136extern const struct dri_extension NV_vp_extension[]; 137extern const struct dri_extension ATI_fs_extension[]; 138extern const struct dri_extension point_extensions[]; 139 140#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 141 142/* TODO: integrate these into xmlpool.h! */ 143#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 144DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 145 DRI_CONF_DESC(en,"Number of texture image units") \ 146 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 147DRI_CONF_OPT_END 148 149#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 150DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 151 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 152 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 153DRI_CONF_OPT_END 154 155#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 156DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 157 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 158 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 159DRI_CONF_OPT_END 160 161#define DRI_CONF_DISABLE_S3TC(def) \ 162DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 163 DRI_CONF_DESC(en,"Disable S3TC compression") \ 164DRI_CONF_OPT_END 165 166#define DRI_CONF_DISABLE_FALLBACK(def) \ 167DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 169DRI_CONF_OPT_END 170 171#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 172DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 174DRI_CONF_OPT_END 175 176#define DRI_CONF_FP_OPTIMIZATION(def) \ 177DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 179 DRI_CONF_ENUM(0,"Optimize for Speed") \ 180 DRI_CONF_ENUM(1,"Optimize for Quality") \ 181 DRI_CONF_DESC_END \ 182DRI_CONF_OPT_END 183 184PUBLIC const char __driConfigOptions[] = 185DRI_CONF_BEGIN 186 DRI_CONF_SECTION_PERFORMANCE 187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 193 DRI_CONF_DISABLE_FALLBACK(true) 194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 195 DRI_CONF_SECTION_END 196 DRI_CONF_SECTION_QUALITY 197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 199 DRI_CONF_FORCE_S3TC_ENABLE(false) 200 DRI_CONF_DISABLE_S3TC(false) 201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 205 DRI_CONF_SECTION_END 206 DRI_CONF_SECTION_DEBUG 207 DRI_CONF_NO_RAST(false) 208 DRI_CONF_SECTION_END 209DRI_CONF_END; 210static const GLuint __driNConfigOptions = 17; 211 212#ifndef RADEON_DEBUG 213int RADEON_DEBUG = 0; 214 215static const struct dri_debug_control debug_control[] = { 216 {"fall", DEBUG_FALLBACKS}, 217 {"tex", DEBUG_TEXTURE}, 218 {"ioctl", DEBUG_IOCTL}, 219 {"prim", DEBUG_PRIMS}, 220 {"vert", DEBUG_VERTS}, 221 {"state", DEBUG_STATE}, 222 {"code", DEBUG_CODEGEN}, 223 {"vfmt", DEBUG_VFMT}, 224 {"vtxf", DEBUG_VFMT}, 225 {"verb", DEBUG_VERBOSE}, 226 {"dri", DEBUG_DRI}, 227 {"dma", DEBUG_DMA}, 228 {"san", DEBUG_SANITY}, 229 {"sync", DEBUG_SYNC}, 230 {"pix", DEBUG_PIXEL}, 231 {"mem", DEBUG_MEMORY}, 232 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 233 {NULL, 0} 234}; 235#endif /* RADEON_DEBUG */ 236 237#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 238 239extern const struct dri_extension card_extensions[]; 240 241static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 242 243static int 244radeonGetParam(int fd, int param, void *value) 245{ 246 int ret; 247 drm_radeon_getparam_t gp; 248 249 gp.param = param; 250 gp.value = value; 251 252 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 253 return ret; 254} 255 256static const __DRIconfig ** 257radeonFillInModes( __DRIscreenPrivate *psp, 258 unsigned pixel_bits, unsigned depth_bits, 259 unsigned stencil_bits, GLboolean have_back_buffer ) 260{ 261 __DRIconfig **configs; 262 __GLcontextModes *m; 263 unsigned depth_buffer_factor; 264 unsigned back_buffer_factor; 265 GLenum fb_format; 266 GLenum fb_type; 267 int i; 268 269 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 270 * enough to add support. Basically, if a context is created with an 271 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 272 * will never be used. 273 */ 274 static const GLenum back_buffer_modes[] = { 275 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 276 }; 277 278 uint8_t depth_bits_array[2]; 279 uint8_t stencil_bits_array[2]; 280 281 282 depth_bits_array[0] = depth_bits; 283 depth_bits_array[1] = depth_bits; 284 285 /* Just like with the accumulation buffer, always provide some modes 286 * with a stencil buffer. It will be a sw fallback, but some apps won't 287 * care about that. 288 */ 289 stencil_bits_array[0] = 0; 290 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 291 292 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 293 back_buffer_factor = (have_back_buffer) ? 2 : 1; 294 295 if ( pixel_bits == 16 ) { 296 fb_format = GL_RGB; 297 fb_type = GL_UNSIGNED_SHORT_5_6_5; 298 } 299 else { 300 fb_format = GL_BGRA; 301 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 302 } 303 304 configs = driCreateConfigs(fb_format, fb_type, 305 depth_bits_array, stencil_bits_array, 306 depth_buffer_factor, 307 back_buffer_modes, back_buffer_factor); 308 if (configs == NULL) { 309 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 310 __func__, __LINE__ ); 311 return NULL; 312 } 313 314 /* Mark the visual as slow if there are "fake" stencil bits. 315 */ 316 for (i = 0; configs[i]; i++) { 317 m = &configs[i]->modes; 318 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 319 m->visualRating = GLX_SLOW_CONFIG; 320 } 321 } 322 323 return (const __DRIconfig **) configs; 324} 325 326#if !RADEON_COMMON 327static const __DRItexOffsetExtension radeonTexOffsetExtension = { 328 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 329 radeonSetTexOffset, 330}; 331#endif 332 333#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 334static const __DRIallocateExtension r200AllocateExtension = { 335 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 336 r200AllocateMemoryMESA, 337 r200FreeMemoryMESA, 338 r200GetMemoryOffsetMESA 339}; 340 341static const __DRItexOffsetExtension r200texOffsetExtension = { 342 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 343 r200SetTexOffset, 344}; 345#endif 346 347#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 348static const __DRItexOffsetExtension r300texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r300SetTexOffset, 351}; 352 353void r300SetTexBuffer(__DRIcontext *pDRICtx, 354 GLint target, 355 __DRIdrawable *dPriv); 356static const __DRItexBufferExtension r300TexBufferExtension = { 357 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 358 r300SetTexBuffer, 359}; 360#endif 361 362/* Create the device specific screen private data struct. 363 */ 364static radeonScreenPtr 365radeonCreateScreen( __DRIscreenPrivate *sPriv ) 366{ 367 radeonScreenPtr screen; 368 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 369 unsigned char *RADEONMMIO; 370 int i; 371 int ret; 372 uint32_t temp; 373 374 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 375 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 376 return GL_FALSE; 377 } 378 379 /* Allocate the private area */ 380 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 381 if ( !screen ) { 382 __driUtilMessage("%s: Could not allocate memory for screen structure", 383 __FUNCTION__); 384 return NULL; 385 } 386 387#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 388 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 389#endif 390 391 /* parse information in __driConfigOptions */ 392 driParseOptionInfo (&screen->optionCache, 393 __driConfigOptions, __driNConfigOptions); 394 395 /* This is first since which regions we map depends on whether or 396 * not we are using a PCI card. 397 */ 398 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 399 { 400 int ret; 401 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 402 &screen->gart_buffer_offset); 403 404 if (ret) { 405 FREE( screen ); 406 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 407 return NULL; 408 } 409 410 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 411 &screen->gart_base); 412 if (ret) { 413 FREE( screen ); 414 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 415 return NULL; 416 } 417 418 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 419 &screen->irq); 420 if (ret) { 421 FREE( screen ); 422 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 423 return NULL; 424 } 425 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 426 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 427 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 428 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 429 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 430 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 431 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 432 } 433 434 screen->mmio.handle = dri_priv->registerHandle; 435 screen->mmio.size = dri_priv->registerSize; 436 if ( drmMap( sPriv->fd, 437 screen->mmio.handle, 438 screen->mmio.size, 439 &screen->mmio.map ) ) { 440 FREE( screen ); 441 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 442 return NULL; 443 } 444 445 RADEONMMIO = screen->mmio.map; 446 447 screen->status.handle = dri_priv->statusHandle; 448 screen->status.size = dri_priv->statusSize; 449 if ( drmMap( sPriv->fd, 450 screen->status.handle, 451 screen->status.size, 452 &screen->status.map ) ) { 453 drmUnmap( screen->mmio.map, screen->mmio.size ); 454 FREE( screen ); 455 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 456 return NULL; 457 } 458 screen->scratch = (__volatile__ uint32_t *) 459 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 460 461 screen->buffers = drmMapBufs( sPriv->fd ); 462 if ( !screen->buffers ) { 463 drmUnmap( screen->status.map, screen->status.size ); 464 drmUnmap( screen->mmio.map, screen->mmio.size ); 465 FREE( screen ); 466 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 467 return NULL; 468 } 469 470 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 471 screen->gartTextures.handle = dri_priv->gartTexHandle; 472 screen->gartTextures.size = dri_priv->gartTexMapSize; 473 if ( drmMap( sPriv->fd, 474 screen->gartTextures.handle, 475 screen->gartTextures.size, 476 (drmAddressPtr)&screen->gartTextures.map ) ) { 477 drmUnmapBufs( screen->buffers ); 478 drmUnmap( screen->status.map, screen->status.size ); 479 drmUnmap( screen->mmio.map, screen->mmio.size ); 480 FREE( screen ); 481 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 482 return NULL; 483 } 484 485 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 486 } 487 488 screen->chip_flags = 0; 489 /* XXX: add more chipsets */ 490 switch ( dri_priv->deviceID ) { 491 case PCI_CHIP_RADEON_LY: 492 case PCI_CHIP_RADEON_LZ: 493 case PCI_CHIP_RADEON_QY: 494 case PCI_CHIP_RADEON_QZ: 495 case PCI_CHIP_RN50_515E: 496 case PCI_CHIP_RN50_5969: 497 screen->chip_family = CHIP_FAMILY_RV100; 498 break; 499 500 case PCI_CHIP_RS100_4136: 501 case PCI_CHIP_RS100_4336: 502 screen->chip_family = CHIP_FAMILY_RS100; 503 break; 504 505 case PCI_CHIP_RS200_4137: 506 case PCI_CHIP_RS200_4337: 507 case PCI_CHIP_RS250_4237: 508 case PCI_CHIP_RS250_4437: 509 screen->chip_family = CHIP_FAMILY_RS200; 510 break; 511 512 case PCI_CHIP_RADEON_QD: 513 case PCI_CHIP_RADEON_QE: 514 case PCI_CHIP_RADEON_QF: 515 case PCI_CHIP_RADEON_QG: 516 /* all original radeons (7200) presumably have a stencil op bug */ 517 screen->chip_family = CHIP_FAMILY_R100; 518 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 519 break; 520 521 case PCI_CHIP_RV200_QW: 522 case PCI_CHIP_RV200_QX: 523 case PCI_CHIP_RADEON_LW: 524 case PCI_CHIP_RADEON_LX: 525 screen->chip_family = CHIP_FAMILY_RV200; 526 screen->chip_flags = RADEON_CHIPSET_TCL; 527 break; 528 529 case PCI_CHIP_R200_BB: 530 case PCI_CHIP_R200_BC: 531 case PCI_CHIP_R200_QH: 532 case PCI_CHIP_R200_QL: 533 case PCI_CHIP_R200_QM: 534 screen->chip_family = CHIP_FAMILY_R200; 535 screen->chip_flags = RADEON_CHIPSET_TCL; 536 break; 537 538 case PCI_CHIP_RV250_If: 539 case PCI_CHIP_RV250_Ig: 540 case PCI_CHIP_RV250_Ld: 541 case PCI_CHIP_RV250_Lf: 542 case PCI_CHIP_RV250_Lg: 543 screen->chip_family = CHIP_FAMILY_RV250; 544 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 545 break; 546 547 case PCI_CHIP_RV280_5960: 548 case PCI_CHIP_RV280_5961: 549 case PCI_CHIP_RV280_5962: 550 case PCI_CHIP_RV280_5964: 551 case PCI_CHIP_RV280_5965: 552 case PCI_CHIP_RV280_5C61: 553 case PCI_CHIP_RV280_5C63: 554 screen->chip_family = CHIP_FAMILY_RV280; 555 screen->chip_flags = RADEON_CHIPSET_TCL; 556 break; 557 558 case PCI_CHIP_RS300_5834: 559 case PCI_CHIP_RS300_5835: 560 case PCI_CHIP_RS350_7834: 561 case PCI_CHIP_RS350_7835: 562 screen->chip_family = CHIP_FAMILY_RS300; 563 break; 564 565 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 566 case PCI_CHIP_R300_AD: 567 screen->chip_family = CHIP_FAMILY_RV350; 568 screen->chip_flags = RADEON_CHIPSET_TCL; 569 break; 570 case PCI_CHIP_R300_AE: 571 case PCI_CHIP_R300_AF: 572 case PCI_CHIP_R300_AG: 573 case PCI_CHIP_R300_ND: 574 case PCI_CHIP_R300_NE: 575 case PCI_CHIP_R300_NF: 576 case PCI_CHIP_R300_NG: 577 screen->chip_family = CHIP_FAMILY_R300; 578 screen->chip_flags = RADEON_CHIPSET_TCL; 579 break; 580 581 case PCI_CHIP_RV350_AP: 582 case PCI_CHIP_RV350_AQ: 583 case PCI_CHIP_RV350_AR: 584 case PCI_CHIP_RV350_AS: 585 case PCI_CHIP_RV350_AT: 586 case PCI_CHIP_RV350_AV: 587 case PCI_CHIP_RV350_AU: 588 case PCI_CHIP_RV350_NP: 589 case PCI_CHIP_RV350_NQ: 590 case PCI_CHIP_RV350_NR: 591 case PCI_CHIP_RV350_NS: 592 case PCI_CHIP_RV350_NT: 593 case PCI_CHIP_RV350_NV: 594 screen->chip_family = CHIP_FAMILY_RV350; 595 screen->chip_flags = RADEON_CHIPSET_TCL; 596 break; 597 598 case PCI_CHIP_R350_AH: 599 case PCI_CHIP_R350_AI: 600 case PCI_CHIP_R350_AJ: 601 case PCI_CHIP_R350_AK: 602 case PCI_CHIP_R350_NH: 603 case PCI_CHIP_R350_NI: 604 case PCI_CHIP_R360_NJ: 605 case PCI_CHIP_R350_NK: 606 screen->chip_family = CHIP_FAMILY_R350; 607 screen->chip_flags = RADEON_CHIPSET_TCL; 608 break; 609 610 case PCI_CHIP_RV370_5460: 611 case PCI_CHIP_RV370_5462: 612 case PCI_CHIP_RV370_5464: 613 case PCI_CHIP_RV370_5B60: 614 case PCI_CHIP_RV370_5B62: 615 case PCI_CHIP_RV370_5B63: 616 case PCI_CHIP_RV370_5B64: 617 case PCI_CHIP_RV370_5B65: 618 case PCI_CHIP_RV380_3150: 619 case PCI_CHIP_RV380_3152: 620 case PCI_CHIP_RV380_3154: 621 case PCI_CHIP_RV380_3E50: 622 case PCI_CHIP_RV380_3E54: 623 screen->chip_family = CHIP_FAMILY_RV380; 624 screen->chip_flags = RADEON_CHIPSET_TCL; 625 break; 626 627 case PCI_CHIP_R420_JN: 628 case PCI_CHIP_R420_JH: 629 case PCI_CHIP_R420_JI: 630 case PCI_CHIP_R420_JJ: 631 case PCI_CHIP_R420_JK: 632 case PCI_CHIP_R420_JL: 633 case PCI_CHIP_R420_JM: 634 case PCI_CHIP_R420_JO: 635 case PCI_CHIP_R420_JP: 636 case PCI_CHIP_R420_JT: 637 case PCI_CHIP_R481_4B49: 638 case PCI_CHIP_R481_4B4A: 639 case PCI_CHIP_R481_4B4B: 640 case PCI_CHIP_R481_4B4C: 641 case PCI_CHIP_R423_UH: 642 case PCI_CHIP_R423_UI: 643 case PCI_CHIP_R423_UJ: 644 case PCI_CHIP_R423_UK: 645 case PCI_CHIP_R430_554C: 646 case PCI_CHIP_R430_554D: 647 case PCI_CHIP_R430_554E: 648 case PCI_CHIP_R430_554F: 649 case PCI_CHIP_R423_5550: 650 case PCI_CHIP_R423_UQ: 651 case PCI_CHIP_R423_UR: 652 case PCI_CHIP_R423_UT: 653 case PCI_CHIP_R430_5D48: 654 case PCI_CHIP_R430_5D49: 655 case PCI_CHIP_R430_5D4A: 656 case PCI_CHIP_R480_5D4C: 657 case PCI_CHIP_R480_5D4D: 658 case PCI_CHIP_R480_5D4E: 659 case PCI_CHIP_R480_5D4F: 660 case PCI_CHIP_R480_5D50: 661 case PCI_CHIP_R480_5D52: 662 case PCI_CHIP_R423_5D57: 663 screen->chip_family = CHIP_FAMILY_R420; 664 screen->chip_flags = RADEON_CHIPSET_TCL; 665 break; 666 667 case PCI_CHIP_RV410_5E4C: 668 case PCI_CHIP_RV410_5E4F: 669 case PCI_CHIP_RV410_564A: 670 case PCI_CHIP_RV410_564B: 671 case PCI_CHIP_RV410_564F: 672 case PCI_CHIP_RV410_5652: 673 case PCI_CHIP_RV410_5653: 674 case PCI_CHIP_RV410_5657: 675 case PCI_CHIP_RV410_5E48: 676 case PCI_CHIP_RV410_5E4A: 677 case PCI_CHIP_RV410_5E4B: 678 case PCI_CHIP_RV410_5E4D: 679 screen->chip_family = CHIP_FAMILY_RV410; 680 screen->chip_flags = RADEON_CHIPSET_TCL; 681 break; 682 683 case PCI_CHIP_RS480_5954: 684 case PCI_CHIP_RS480_5955: 685 case PCI_CHIP_RS482_5974: 686 case PCI_CHIP_RS482_5975: 687 case PCI_CHIP_RS400_5A41: 688 case PCI_CHIP_RS400_5A42: 689 case PCI_CHIP_RC410_5A61: 690 case PCI_CHIP_RC410_5A62: 691 screen->chip_family = CHIP_FAMILY_RS400; 692 break; 693 694 case PCI_CHIP_RS690_791E: 695 case PCI_CHIP_RS690_791F: 696 screen->chip_family = CHIP_FAMILY_RS690; 697 break; 698 case PCI_CHIP_RS740_796C: 699 case PCI_CHIP_RS740_796D: 700 case PCI_CHIP_RS740_796E: 701 case PCI_CHIP_RS740_796F: 702 screen->chip_family = CHIP_FAMILY_RS740; 703 break; 704 705 case PCI_CHIP_R520_7100: 706 case PCI_CHIP_R520_7101: 707 case PCI_CHIP_R520_7102: 708 case PCI_CHIP_R520_7103: 709 case PCI_CHIP_R520_7104: 710 case PCI_CHIP_R520_7105: 711 case PCI_CHIP_R520_7106: 712 case PCI_CHIP_R520_7108: 713 case PCI_CHIP_R520_7109: 714 case PCI_CHIP_R520_710A: 715 case PCI_CHIP_R520_710B: 716 case PCI_CHIP_R520_710C: 717 case PCI_CHIP_R520_710E: 718 case PCI_CHIP_R520_710F: 719 screen->chip_family = CHIP_FAMILY_R520; 720 screen->chip_flags = RADEON_CHIPSET_TCL; 721 break; 722 723 case PCI_CHIP_RV515_7140: 724 case PCI_CHIP_RV515_7141: 725 case PCI_CHIP_RV515_7142: 726 case PCI_CHIP_RV515_7143: 727 case PCI_CHIP_RV515_7144: 728 case PCI_CHIP_RV515_7145: 729 case PCI_CHIP_RV515_7146: 730 case PCI_CHIP_RV515_7147: 731 case PCI_CHIP_RV515_7149: 732 case PCI_CHIP_RV515_714A: 733 case PCI_CHIP_RV515_714B: 734 case PCI_CHIP_RV515_714C: 735 case PCI_CHIP_RV515_714D: 736 case PCI_CHIP_RV515_714E: 737 case PCI_CHIP_RV515_714F: 738 case PCI_CHIP_RV515_7151: 739 case PCI_CHIP_RV515_7152: 740 case PCI_CHIP_RV515_7153: 741 case PCI_CHIP_RV515_715E: 742 case PCI_CHIP_RV515_715F: 743 case PCI_CHIP_RV515_7180: 744 case PCI_CHIP_RV515_7181: 745 case PCI_CHIP_RV515_7183: 746 case PCI_CHIP_RV515_7186: 747 case PCI_CHIP_RV515_7187: 748 case PCI_CHIP_RV515_7188: 749 case PCI_CHIP_RV515_718A: 750 case PCI_CHIP_RV515_718B: 751 case PCI_CHIP_RV515_718C: 752 case PCI_CHIP_RV515_718D: 753 case PCI_CHIP_RV515_718F: 754 case PCI_CHIP_RV515_7193: 755 case PCI_CHIP_RV515_7196: 756 case PCI_CHIP_RV515_719B: 757 case PCI_CHIP_RV515_719F: 758 case PCI_CHIP_RV515_7200: 759 case PCI_CHIP_RV515_7210: 760 case PCI_CHIP_RV515_7211: 761 screen->chip_family = CHIP_FAMILY_RV515; 762 screen->chip_flags = RADEON_CHIPSET_TCL; 763 break; 764 765 case PCI_CHIP_RV530_71C0: 766 case PCI_CHIP_RV530_71C1: 767 case PCI_CHIP_RV530_71C2: 768 case PCI_CHIP_RV530_71C3: 769 case PCI_CHIP_RV530_71C4: 770 case PCI_CHIP_RV530_71C5: 771 case PCI_CHIP_RV530_71C6: 772 case PCI_CHIP_RV530_71C7: 773 case PCI_CHIP_RV530_71CD: 774 case PCI_CHIP_RV530_71CE: 775 case PCI_CHIP_RV530_71D2: 776 case PCI_CHIP_RV530_71D4: 777 case PCI_CHIP_RV530_71D5: 778 case PCI_CHIP_RV530_71D6: 779 case PCI_CHIP_RV530_71DA: 780 case PCI_CHIP_RV530_71DE: 781 screen->chip_family = CHIP_FAMILY_RV530; 782 screen->chip_flags = RADEON_CHIPSET_TCL; 783 break; 784 785 case PCI_CHIP_R580_7240: 786 case PCI_CHIP_R580_7243: 787 case PCI_CHIP_R580_7244: 788 case PCI_CHIP_R580_7245: 789 case PCI_CHIP_R580_7246: 790 case PCI_CHIP_R580_7247: 791 case PCI_CHIP_R580_7248: 792 case PCI_CHIP_R580_7249: 793 case PCI_CHIP_R580_724A: 794 case PCI_CHIP_R580_724B: 795 case PCI_CHIP_R580_724C: 796 case PCI_CHIP_R580_724D: 797 case PCI_CHIP_R580_724E: 798 case PCI_CHIP_R580_724F: 799 case PCI_CHIP_R580_7284: 800 screen->chip_family = CHIP_FAMILY_R580; 801 screen->chip_flags = RADEON_CHIPSET_TCL; 802 break; 803 804 case PCI_CHIP_RV570_7280: 805 case PCI_CHIP_RV560_7281: 806 case PCI_CHIP_RV560_7283: 807 case PCI_CHIP_RV560_7287: 808 case PCI_CHIP_RV570_7288: 809 case PCI_CHIP_RV570_7289: 810 case PCI_CHIP_RV570_728B: 811 case PCI_CHIP_RV570_728C: 812 case PCI_CHIP_RV560_7290: 813 case PCI_CHIP_RV560_7291: 814 case PCI_CHIP_RV560_7293: 815 case PCI_CHIP_RV560_7297: 816 screen->chip_family = CHIP_FAMILY_RV560; 817 screen->chip_flags = RADEON_CHIPSET_TCL; 818 break; 819 820 default: 821 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 822 dri_priv->deviceID); 823 return NULL; 824 } 825 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 826 sPriv->ddx_version.minor < 2) { 827 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 828 return NULL; 829 } 830 831 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 832 fprintf(stderr, "R500 support requires a newer drm.\n"); 833 return NULL; 834 } 835 836 if (getenv("R300_NO_TCL")) 837 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 838 839 if (screen->chip_family <= CHIP_FAMILY_RS200) 840 screen->chip_flags |= RADEON_CLASS_R100; 841 else if (screen->chip_family <= CHIP_FAMILY_RV280) 842 screen->chip_flags |= RADEON_CLASS_R200; 843 else 844 screen->chip_flags |= RADEON_CLASS_R300; 845 846 screen->cpp = dri_priv->bpp / 8; 847 screen->AGPMode = dri_priv->AGPMode; 848 849 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 850 &temp); 851 if (ret) { 852 if (screen->chip_family < CHIP_FAMILY_RS690) 853 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 854 else { 855 FREE( screen ); 856 fprintf(stderr, "Unable to get fb location need newer drm\n"); 857 return NULL; 858 } 859 } else { 860 screen->fbLocation = (temp & 0xffff) << 16; 861 } 862 863 if (screen->chip_family >= CHIP_FAMILY_RV515) { 864 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 865 &temp); 866 if (ret) { 867 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 868 switch (screen->chip_family) { 869 case CHIP_FAMILY_R300: 870 case CHIP_FAMILY_R350: 871 screen->num_gb_pipes = 2; 872 break; 873 case CHIP_FAMILY_R420: 874 case CHIP_FAMILY_R520: 875 case CHIP_FAMILY_R580: 876 case CHIP_FAMILY_RV560: 877 case CHIP_FAMILY_RV570: 878 screen->num_gb_pipes = 4; 879 break; 880 case CHIP_FAMILY_RV350: 881 case CHIP_FAMILY_RV515: 882 case CHIP_FAMILY_RV530: 883 case CHIP_FAMILY_RV410: 884 default: 885 screen->num_gb_pipes = 1; 886 break; 887 } 888 } else { 889 screen->num_gb_pipes = temp; 890 } 891 } 892 893 if ( sPriv->drm_version.minor >= 10 ) { 894 drm_radeon_setparam_t sp; 895 896 sp.param = RADEON_SETPARAM_FB_LOCATION; 897 sp.value = screen->fbLocation; 898 899 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 900 &sp, sizeof( sp ) ); 901 } 902 903 screen->frontOffset = dri_priv->frontOffset; 904 screen->frontPitch = dri_priv->frontPitch; 905 screen->backOffset = dri_priv->backOffset; 906 screen->backPitch = dri_priv->backPitch; 907 screen->depthOffset = dri_priv->depthOffset; 908 screen->depthPitch = dri_priv->depthPitch; 909 910 /* Check if ddx has set up a surface reg to cover depth buffer */ 911 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 912 /* these chips don't use tiled z without hyperz. So always pretend 913 we have set up a surface which will cause linear reads/writes */ 914 (IS_R100_CLASS(screen) && 915 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 916 917 if ( dri_priv->textureSize == 0 ) { 918 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 919 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 920 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 921 dri_priv->log2GARTTexGran; 922 } else { 923 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 924 + screen->fbLocation; 925 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 926 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 927 dri_priv->log2TexGran; 928 } 929 930 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 931 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 932 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 933 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 934 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 935 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 936 } else { 937 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 938 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 939 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 940 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 941 dri_priv->log2GARTTexGran; 942 } 943 944 i = 0; 945 screen->extensions[i++] = &driCopySubBufferExtension.base; 946 screen->extensions[i++] = &driFrameTrackingExtension.base; 947 screen->extensions[i++] = &driReadDrawableExtension; 948 949 if ( screen->irq != 0 ) { 950 screen->extensions[i++] = &driSwapControlExtension.base; 951 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 952 } 953 954#if !RADEON_COMMON 955 screen->extensions[i++] = &radeonTexOffsetExtension.base; 956#endif 957 958#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 959 if (IS_R200_CLASS(screen)) 960 screen->extensions[i++] = &r200AllocateExtension.base; 961 962 screen->extensions[i++] = &r200texOffsetExtension.base; 963#endif 964 965#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 966 screen->extensions[i++] = &r300texOffsetExtension.base; 967#endif 968 969 screen->extensions[i++] = NULL; 970 sPriv->extensions = screen->extensions; 971 972 screen->driScreen = sPriv; 973 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 974 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 975 screen->sarea_priv_offset); 976 screen->bom = radeon_bo_manager_legacy(screen); 977 if (screen->bom == NULL) { 978 free(screen); 979 return NULL; 980 } 981 return screen; 982} 983 984static radeonScreenPtr 985radeonCreateScreen2(__DRIscreenPrivate *sPriv) 986{ 987 radeonScreenPtr screen; 988 int i; 989 990 /* Allocate the private area */ 991 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 992 if ( !screen ) { 993 __driUtilMessage("%s: Could not allocate memory for screen structure", 994 __FUNCTION__); 995 fprintf(stderr, "leaving here\n"); 996 return NULL; 997 } 998 999#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1000 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1001#endif 1002 1003 /* parse information in __driConfigOptions */ 1004 driParseOptionInfo (&screen->optionCache, 1005 __driConfigOptions, __driNConfigOptions); 1006 1007 screen->chip_flags = 0; 1008 /* FIXME: do either an ioctl (bad) or a sysfs file for driver to 1009 * information about which chipset is their */ 1010 screen->chip_family = CHIP_FAMILY_RV350; 1011 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300; 1012 1013 i = 0; 1014 screen->extensions[i++] = &driCopySubBufferExtension.base; 1015 screen->extensions[i++] = &driFrameTrackingExtension.base; 1016 screen->extensions[i++] = &driReadDrawableExtension; 1017 1018 if ( screen->irq != 0 ) { 1019 screen->extensions[i++] = &driSwapControlExtension.base; 1020 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1021 } 1022 1023#if !RADEON_COMMON 1024 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1025#endif 1026 1027#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1028 if (IS_R200_CLASS(screen)) 1029 screen->extensions[i++] = &r200AllocateExtension.base; 1030 1031 screen->extensions[i++] = &r200texOffsetExtension.base; 1032#endif 1033 1034#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1035 screen->extensions[i++] = &r300texOffsetExtension.base; 1036 screen->extensions[i++] = &r300TexBufferExtension.base; 1037#endif 1038 1039 screen->extensions[i++] = NULL; 1040 sPriv->extensions = screen->extensions; 1041 1042 screen->driScreen = sPriv; 1043 screen->bom = radeon_bo_manager_gem(sPriv->fd); 1044 if (screen->bom == NULL) { 1045 free(screen); 1046 return NULL; 1047 } 1048 return screen; 1049} 1050 1051/* Destroy the device specific screen private data struct. 1052 */ 1053static void 1054radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1055{ 1056 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1057 1058 if (!screen) 1059 return; 1060 1061 if (sPriv->dri2.enabled) { 1062 radeon_bo_manager_gem_shutdown(screen->bom); 1063 } else { 1064 radeon_bo_manager_legacy_shutdown(screen->bom); 1065 1066 if ( screen->gartTextures.map ) { 1067 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1068 } 1069 drmUnmapBufs( screen->buffers ); 1070 drmUnmap( screen->status.map, screen->status.size ); 1071 drmUnmap( screen->mmio.map, screen->mmio.size ); 1072 } 1073 1074 /* free all option information */ 1075 driDestroyOptionInfo (&screen->optionCache); 1076 1077 FREE( screen ); 1078 sPriv->private = NULL; 1079} 1080 1081 1082/* Initialize the driver specific screen private data. 1083 */ 1084static GLboolean 1085radeonInitDriver( __DRIscreenPrivate *sPriv ) 1086{ 1087 if (sPriv->dri2.enabled) { 1088 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1089 } else { 1090 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1091 } 1092 if ( !sPriv->private ) { 1093 radeonDestroyScreen( sPriv ); 1094 return GL_FALSE; 1095 } 1096 1097 return GL_TRUE; 1098} 1099 1100#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1101static GLboolean 1102radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1103 GLenum intFormat, GLuint w, GLuint h) 1104{ 1105 rb->Width = w; 1106 rb->Height = h; 1107 rb->_ActualFormat = intFormat; 1108 1109 return GL_TRUE; 1110} 1111 1112 1113static struct radeon_renderbuffer * 1114radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1115{ 1116 struct radeon_renderbuffer *ret; 1117 1118 ret = CALLOC_STRUCT(radeon_renderbuffer); 1119 if (!ret) 1120 return NULL; 1121 1122 _mesa_init_renderbuffer(&ret->base, 0); 1123 1124 /* XXX format junk */ 1125 switch (format) { 1126 case GL_RGB5: 1127 ret->base._ActualFormat = GL_RGB5; 1128 ret->base._BaseFormat = GL_RGBA; 1129 ret->base.RedBits = 5; 1130 ret->base.GreenBits = 6; 1131 ret->base.BlueBits = 5; 1132 ret->base.DataType = GL_UNSIGNED_BYTE; 1133 break; 1134 case GL_RGBA8: 1135 ret->base._ActualFormat = GL_RGBA8; 1136 ret->base._BaseFormat = GL_RGBA; 1137 ret->base.RedBits = 8; 1138 ret->base.GreenBits = 8; 1139 ret->base.BlueBits = 8; 1140 ret->base.AlphaBits = 8; 1141 ret->base.DataType = GL_UNSIGNED_BYTE; 1142 break; 1143 case GL_STENCIL_INDEX8_EXT: 1144 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1145 ret->base._BaseFormat = GL_STENCIL_INDEX; 1146 ret->base.StencilBits = 8; 1147 ret->base.DataType = GL_UNSIGNED_BYTE; 1148 break; 1149 case GL_DEPTH_COMPONENT16: 1150 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1151 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1152 ret->base.DepthBits = 16; 1153 ret->base.DataType = GL_UNSIGNED_SHORT; 1154 break; 1155 case GL_DEPTH_COMPONENT24: 1156 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1157 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1158 ret->base.DepthBits = 24; 1159 ret->base.DataType = GL_UNSIGNED_INT; 1160 break; 1161 case GL_DEPTH24_STENCIL8_EXT: 1162 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1163 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1164 ret->base.DepthBits = 24; 1165 ret->base.StencilBits = 8; 1166 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1167 break; 1168 default: 1169 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1170 _mesa_delete_renderbuffer(&ret->base); 1171 return NULL; 1172 } 1173 1174 ret->dPriv = driDrawPriv; 1175 ret->base.InternalFormat = format; 1176 1177 ret->base.AllocStorage = radeon_alloc_window_storage; 1178 1179 radeonSetSpanFunctions(ret); 1180 1181 return ret; 1182} 1183 1184/** 1185 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1186 * 1187 * \todo This function (and its interface) will need to be updated to support 1188 * pbuffers. 1189 */ 1190static GLboolean 1191radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1192 __DRIdrawablePrivate *driDrawPriv, 1193 const __GLcontextModes *mesaVis, 1194 GLboolean isPixmap ) 1195{ 1196 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1197 1198 const GLboolean swDepth = GL_FALSE; 1199 const GLboolean swAlpha = GL_FALSE; 1200 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1201 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1202 mesaVis->depthBits != 24; 1203 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1204 GLenum depthFormat = GL_NONE; 1205 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1206 1207 if (mesaVis->depthBits == 16) 1208 depthFormat = GL_DEPTH_COMPONENT16; 1209 else if (mesaVis->depthBits == 24) 1210 depthFormat = GL_DEPTH_COMPONENT24; 1211 1212 /* front color renderbuffer */ 1213 { 1214 struct radeon_renderbuffer *front = 1215 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1216 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1217 front->has_surface = 1; 1218 } 1219 1220 /* back color renderbuffer */ 1221 if (mesaVis->doubleBufferMode) { 1222 struct radeon_renderbuffer *back = 1223 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1224 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1225 back->has_surface = 1; 1226 } 1227 1228 /* depth renderbuffer */ 1229 if (depthFormat != GL_NONE) { 1230 struct radeon_renderbuffer *depth = 1231 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1232 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1233 depth->has_surface = screen->depthHasSurface; 1234 } 1235 1236 /* stencil renderbuffer */ 1237 if (mesaVis->stencilBits > 0 && !swStencil) { 1238 struct radeon_renderbuffer *stencil = 1239 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1240 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1241 stencil->has_surface = screen->depthHasSurface; 1242 } 1243 1244 _mesa_add_soft_renderbuffers(fb, 1245 GL_FALSE, /* color */ 1246 swDepth, 1247 swStencil, 1248 swAccum, 1249 swAlpha, 1250 GL_FALSE /* aux */); 1251 driDrawPriv->driverPrivate = (void *) fb; 1252 1253 return (driDrawPriv->driverPrivate != NULL); 1254} 1255#else 1256 1257/** 1258 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1259 * 1260 * \todo This function (and its interface) will need to be updated to support 1261 * pbuffers. 1262 */ 1263static GLboolean 1264radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1265 __DRIdrawablePrivate *driDrawPriv, 1266 const __GLcontextModes *mesaVis, 1267 GLboolean isPixmap ) 1268{ 1269 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1270 1271 if (isPixmap) { 1272 return GL_FALSE; /* not implemented */ 1273 } 1274 else { 1275 const GLboolean swDepth = GL_FALSE; 1276 const GLboolean swAlpha = GL_FALSE; 1277 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1278 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1279 mesaVis->depthBits != 24; 1280 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1281 1282 /* front color renderbuffer */ 1283 { 1284 driRenderbuffer *frontRb 1285 = driNewRenderbuffer(GL_RGBA, 1286 driScrnPriv->pFB + screen->frontOffset, 1287 screen->cpp, 1288 screen->frontOffset, screen->frontPitch, 1289 driDrawPriv); 1290 radeonSetSpanFunctions(frontRb, mesaVis); 1291 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); 1292 } 1293 1294 /* back color renderbuffer */ 1295 if (mesaVis->doubleBufferMode) { 1296 driRenderbuffer *backRb 1297 = driNewRenderbuffer(GL_RGBA, 1298 driScrnPriv->pFB + screen->backOffset, 1299 screen->cpp, 1300 screen->backOffset, screen->backPitch, 1301 driDrawPriv); 1302 radeonSetSpanFunctions(backRb, mesaVis); 1303 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); 1304 } 1305 1306 /* depth renderbuffer */ 1307 if (mesaVis->depthBits == 16) { 1308 driRenderbuffer *depthRb 1309 = driNewRenderbuffer(GL_DEPTH_COMPONENT16, 1310 driScrnPriv->pFB + screen->depthOffset, 1311 screen->cpp, 1312 screen->depthOffset, screen->depthPitch, 1313 driDrawPriv); 1314 radeonSetSpanFunctions(depthRb, mesaVis); 1315 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1316 depthRb->has_surface = screen->depthHasSurface; 1317 } 1318 else if (mesaVis->depthBits == 24) { 1319 driRenderbuffer *depthRb 1320 = driNewRenderbuffer(GL_DEPTH_COMPONENT24, 1321 driScrnPriv->pFB + screen->depthOffset, 1322 screen->cpp, 1323 screen->depthOffset, screen->depthPitch, 1324 driDrawPriv); 1325 radeonSetSpanFunctions(depthRb, mesaVis); 1326 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1327 depthRb->has_surface = screen->depthHasSurface; 1328 } 1329 1330 /* stencil renderbuffer */ 1331 if (mesaVis->stencilBits > 0 && !swStencil) { 1332 driRenderbuffer *stencilRb 1333 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, 1334 driScrnPriv->pFB + screen->depthOffset, 1335 screen->cpp, 1336 screen->depthOffset, screen->depthPitch, 1337 driDrawPriv); 1338 radeonSetSpanFunctions(stencilRb, mesaVis); 1339 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); 1340 stencilRb->has_surface = screen->depthHasSurface; 1341 } 1342 1343 _mesa_add_soft_renderbuffers(fb, 1344 GL_FALSE, /* color */ 1345 swDepth, 1346 swStencil, 1347 swAccum, 1348 swAlpha, 1349 GL_FALSE /* aux */); 1350 driDrawPriv->driverPrivate = (void *) fb; 1351 1352 return (driDrawPriv->driverPrivate != NULL); 1353 } 1354} 1355#endif 1356 1357static void 1358radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1359{ 1360 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1361} 1362 1363#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1364/** 1365 * Choose the appropriate CreateContext function based on the chipset. 1366 * Eventually, all drivers will go through this process. 1367 */ 1368static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1369 __DRIcontextPrivate * driContextPriv, 1370 void *sharedContextPriv) 1371{ 1372 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1373 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1374 1375 if (IS_R300_CLASS(screen)) 1376 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1377 return GL_FALSE; 1378} 1379 1380/** 1381 * Choose the appropriate DestroyContext function based on the chipset. 1382 */ 1383static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1384{ 1385 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1386 1387 if (IS_R300_CLASS(radeon->radeonScreen)) 1388 return r300DestroyContext(driContextPriv); 1389} 1390 1391 1392#endif 1393 1394/** 1395 * This is the driver specific part of the createNewScreen entry point. 1396 * 1397 * \todo maybe fold this into intelInitDriver 1398 * 1399 * \return the __GLcontextModes supported by this driver 1400 */ 1401static const __DRIconfig ** 1402radeonInitScreen(__DRIscreenPrivate *psp) 1403{ 1404#if !RADEON_COMMON 1405 static const char *driver_name = "Radeon"; 1406 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1407 static const __DRIversion dri_expected = { 4, 0, 0 }; 1408 static const __DRIversion drm_expected = { 1, 6, 0 }; 1409#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1410 static const char *driver_name = "R200"; 1411 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1412 static const __DRIversion dri_expected = { 4, 0, 0 }; 1413 static const __DRIversion drm_expected = { 1, 6, 0 }; 1414#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1415 static const char *driver_name = "R300"; 1416 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1417 static const __DRIversion dri_expected = { 4, 0, 0 }; 1418 static const __DRIversion drm_expected = { 1, 24, 0 }; 1419#endif 1420 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1421 1422 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1423 &psp->dri_version, & dri_expected, 1424 &psp->ddx_version, & ddx_expected, 1425 &psp->drm_version, & drm_expected ) ) { 1426 return NULL; 1427 } 1428 1429 /* Calling driInitExtensions here, with a NULL context pointer, 1430 * does not actually enable the extensions. It just makes sure 1431 * that all the dispatch offsets for all the extensions that 1432 * *might* be enables are known. This is needed because the 1433 * dispatch offsets need to be known when _mesa_context_create 1434 * is called, but we can't enable the extensions until we have a 1435 * context pointer. 1436 * 1437 * Hello chicken. Hello egg. How are you two today? 1438 */ 1439 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1440#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1441 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1442 driInitSingleExtension( NULL, ARB_vp_extension ); 1443 driInitSingleExtension( NULL, NV_vp_extension ); 1444 driInitSingleExtension( NULL, ATI_fs_extension ); 1445 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1446#endif 1447 1448 if (!radeonInitDriver(psp)) 1449 return NULL; 1450 1451 /* for now fill in all modes */ 1452 return radeonFillInModes( psp, 1453 dri_priv->bpp, 1454 (dri_priv->bpp == 16) ? 16 : 24, 1455 (dri_priv->bpp == 16) ? 0 : 8, 1); 1456} 1457 1458/** 1459 * This is the driver specific part of the createNewScreen entry point. 1460 * Called when using DRI2. 1461 * 1462 * \return the __GLcontextModes supported by this driver 1463 */ 1464static const 1465__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1466{ 1467 /* Calling driInitExtensions here, with a NULL context pointer, 1468 * does not actually enable the extensions. It just makes sure 1469 * that all the dispatch offsets for all the extensions that 1470 * *might* be enables are known. This is needed because the 1471 * dispatch offsets need to be known when _mesa_context_create 1472 * is called, but we can't enable the extensions until we have a 1473 * context pointer. 1474 * 1475 * Hello chicken. Hello egg. How are you two today? 1476 */ 1477 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1478#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1479 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1480 driInitSingleExtension( NULL, ARB_vp_extension ); 1481 driInitSingleExtension( NULL, NV_vp_extension ); 1482 driInitSingleExtension( NULL, ATI_fs_extension ); 1483 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1484#endif 1485 1486 if (!radeonInitDriver(psp)) { 1487 return NULL; 1488 } 1489 1490 /* for now fill in all modes */ 1491 return radeonFillInModes( psp, 24, 24, 8, 1); 1492} 1493 1494/** 1495 * Get information about previous buffer swaps. 1496 */ 1497static int 1498getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1499{ 1500#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1501 radeonContextPtr rmesa; 1502#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1503 r200ContextPtr rmesa; 1504#endif 1505 1506 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1507 || (dPriv->driContextPriv->driverPrivate == NULL) 1508 || (sInfo == NULL) ) { 1509 return -1; 1510 } 1511 1512 rmesa = dPriv->driContextPriv->driverPrivate; 1513 sInfo->swap_count = rmesa->swap_count; 1514 sInfo->swap_ust = rmesa->swap_ust; 1515 sInfo->swap_missed_count = rmesa->swap_missed_count; 1516 1517 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1518 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1519 : 0.0; 1520 1521 return 0; 1522} 1523 1524#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1525const struct __DriverAPIRec driDriverAPI = { 1526 .InitScreen = radeonInitScreen, 1527 .DestroyScreen = radeonDestroyScreen, 1528 .CreateContext = radeonCreateContext, 1529 .DestroyContext = radeonDestroyContext, 1530 .CreateBuffer = radeonCreateBuffer, 1531 .DestroyBuffer = radeonDestroyBuffer, 1532 .SwapBuffers = radeonSwapBuffers, 1533 .MakeCurrent = radeonMakeCurrent, 1534 .UnbindContext = radeonUnbindContext, 1535 .GetSwapInfo = getSwapInfo, 1536 .GetDrawableMSC = driDrawableGetMSC32, 1537 .WaitForMSC = driWaitForMSC32, 1538 .WaitForSBC = NULL, 1539 .SwapBuffersMSC = NULL, 1540 .CopySubBuffer = radeonCopySubBuffer, 1541 /* DRI2 */ 1542 .InitScreen2 = radeonInitScreen2, 1543}; 1544#else 1545const struct __DriverAPIRec driDriverAPI = { 1546 .InitScreen = radeonInitScreen, 1547 .DestroyScreen = radeonDestroyScreen, 1548 .CreateContext = r200CreateContext, 1549 .DestroyContext = r200DestroyContext, 1550 .CreateBuffer = radeonCreateBuffer, 1551 .DestroyBuffer = radeonDestroyBuffer, 1552 .SwapBuffers = r200SwapBuffers, 1553 .MakeCurrent = r200MakeCurrent, 1554 .UnbindContext = r200UnbindContext, 1555 .GetSwapInfo = getSwapInfo, 1556 .GetDrawableMSC = driDrawableGetMSC32, 1557 .WaitForMSC = driWaitForMSC32, 1558 .WaitForSBC = NULL, 1559 .SwapBuffersMSC = NULL, 1560 .CopySubBuffer = r200CopySubBuffer, 1561}; 1562#endif 1563 1564