radeon_screen.c revision e015a4c29bf61077a50780cc99381510671b20ec
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if defined(RADEON_R100) 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif defined(RADEON_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif defined(RADEON_R300) 59#include "r300_context.h" 60#include "r300_tex.h" 61#elif defined(RADEON_R600) 62#include "r600_context.h" 63#include "r700_driconf.h" /* +r6/r7 */ 64#include "r600_tex.h" /* +r6/r7 */ 65#endif 66 67#include "utils.h" 68#include "vblank.h" 69#include "drirenderbuffer.h" 70 71#include "radeon_bocs_wrapper.h" 72 73#include "GL/internal/dri_interface.h" 74 75/* Radeon configuration 76 */ 77#include "xmlpool.h" 78 79#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 80DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 81 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 82 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 83DRI_CONF_OPT_END 84 85#if defined(RADEON_R100) /* R100 */ 86PUBLIC const char __driConfigOptions[] = 87DRI_CONF_BEGIN 88 DRI_CONF_SECTION_PERFORMANCE 89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 91 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 92 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 93 DRI_CONF_HYPERZ(false) 94 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 95 DRI_CONF_SECTION_END 96 DRI_CONF_SECTION_QUALITY 97 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 98 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 99 DRI_CONF_NO_NEG_LOD_BIAS(false) 100 DRI_CONF_FORCE_S3TC_ENABLE(false) 101 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 102 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 103 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 104 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 105 DRI_CONF_SECTION_END 106 DRI_CONF_SECTION_DEBUG 107 DRI_CONF_NO_RAST(false) 108 DRI_CONF_SECTION_END 109DRI_CONF_END; 110static const GLuint __driNConfigOptions = 15; 111 112#elif defined(RADEON_R200) 113 114PUBLIC const char __driConfigOptions[] = 115DRI_CONF_BEGIN 116 DRI_CONF_SECTION_PERFORMANCE 117 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 118 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 119 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 121 DRI_CONF_HYPERZ(false) 122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 123 DRI_CONF_SECTION_END 124 DRI_CONF_SECTION_QUALITY 125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 127 DRI_CONF_NO_NEG_LOD_BIAS(false) 128 DRI_CONF_FORCE_S3TC_ENABLE(false) 129 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 130 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 131 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 132 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 133 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_DEBUG 136 DRI_CONF_NO_RAST(false) 137 DRI_CONF_SECTION_END 138 DRI_CONF_SECTION_SOFTWARE 139 DRI_CONF_NV_VERTEX_PROGRAM(false) 140 DRI_CONF_SECTION_END 141DRI_CONF_END; 142static const GLuint __driNConfigOptions = 17; 143 144#elif defined(RADEON_R300) || defined(RADEON_R600) 145 146#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 147#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 148 149/* TODO: integrate these into xmlpool.h! */ 150#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 151DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 152 DRI_CONF_DESC(en,"Number of texture image units") \ 153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 154DRI_CONF_OPT_END 155 156#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 157DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 158 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 160DRI_CONF_OPT_END 161 162 163 164#define DRI_CONF_DISABLE_S3TC(def) \ 165DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 166 DRI_CONF_DESC(en,"Disable S3TC compression") \ 167DRI_CONF_OPT_END 168 169#define DRI_CONF_DISABLE_FALLBACK(def) \ 170DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 172DRI_CONF_OPT_END 173 174#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 175DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 177DRI_CONF_OPT_END 178 179#define DRI_CONF_FP_OPTIMIZATION(def) \ 180DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 182 DRI_CONF_ENUM(0,"Optimize for Speed") \ 183 DRI_CONF_ENUM(1,"Optimize for Quality") \ 184 DRI_CONF_DESC_END \ 185DRI_CONF_OPT_END 186 187PUBLIC const char __driConfigOptions[] = 188DRI_CONF_BEGIN 189 DRI_CONF_SECTION_PERFORMANCE 190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 196 DRI_CONF_DISABLE_FALLBACK(true) 197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 198 DRI_CONF_SECTION_END 199 DRI_CONF_SECTION_QUALITY 200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 202 DRI_CONF_FORCE_S3TC_ENABLE(false) 203 DRI_CONF_DISABLE_S3TC(false) 204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 208 DRI_CONF_SECTION_END 209 DRI_CONF_SECTION_DEBUG 210 DRI_CONF_NO_RAST(false) 211 DRI_CONF_SECTION_END 212DRI_CONF_END; 213static const GLuint __driNConfigOptions = 17; 214 215#endif 216 217static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 218 219static int 220radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) 221{ 222 int ret; 223 drm_radeon_getparam_t gp = { 0 }; 224 struct drm_radeon_info info = { 0 }; 225 226 if (sPriv->drm_version.major >= 2) { 227 info.value = (uint64_t)(uintptr_t)value; 228 switch (param) { 229 case RADEON_PARAM_DEVICE_ID: 230 info.request = RADEON_INFO_DEVICE_ID; 231 break; 232 case RADEON_PARAM_NUM_GB_PIPES: 233 info.request = RADEON_INFO_NUM_GB_PIPES; 234 break; 235 case RADEON_PARAM_NUM_Z_PIPES: 236 info.request = RADEON_INFO_NUM_Z_PIPES; 237 break; 238 default: 239 return -EINVAL; 240 } 241 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 242 } else { 243 gp.param = param; 244 gp.value = value; 245 246 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 247 } 248 return ret; 249} 250 251static const __DRIconfig ** 252radeonFillInModes( __DRIscreenPrivate *psp, 253 unsigned pixel_bits, unsigned depth_bits, 254 unsigned stencil_bits, GLboolean have_back_buffer ) 255{ 256 __DRIconfig **configs; 257 __GLcontextModes *m; 258 unsigned depth_buffer_factor; 259 unsigned back_buffer_factor; 260 int i; 261 262 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 263 * enough to add support. Basically, if a context is created with an 264 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 265 * will never be used. 266 */ 267 static const GLenum back_buffer_modes[] = { 268 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 269 }; 270 271 uint8_t depth_bits_array[2]; 272 uint8_t stencil_bits_array[2]; 273 uint8_t msaa_samples_array[1]; 274 275 depth_bits_array[0] = depth_bits; 276 depth_bits_array[1] = depth_bits; 277 278 /* Just like with the accumulation buffer, always provide some modes 279 * with a stencil buffer. It will be a sw fallback, but some apps won't 280 * care about that. 281 */ 282 stencil_bits_array[0] = stencil_bits; 283 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 284 285 msaa_samples_array[0] = 0; 286 287 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1; 288 back_buffer_factor = (have_back_buffer) ? 2 : 1; 289 290 if (pixel_bits == 16) { 291 __DRIconfig **configs_a8r8g8b8; 292 __DRIconfig **configs_r5g6b5; 293 294 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 295 depth_bits_array, stencil_bits_array, 296 depth_buffer_factor, back_buffer_modes, 297 back_buffer_factor, msaa_samples_array, 298 1); 299 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 300 depth_bits_array, stencil_bits_array, 301 1, back_buffer_modes, 1, 302 msaa_samples_array, 1); 303 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 304 } else 305 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 306 depth_bits_array, stencil_bits_array, 307 depth_buffer_factor, 308 back_buffer_modes, back_buffer_factor, 309 msaa_samples_array, 1); 310 311 if (configs == NULL) { 312 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 313 __func__, __LINE__ ); 314 return NULL; 315 } 316 317 /* Mark the visual as slow if there are "fake" stencil bits. 318 */ 319 for (i = 0; configs[i]; i++) { 320 m = &configs[i]->modes; 321 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 322 m->visualRating = GLX_SLOW_CONFIG; 323 } 324 } 325 326 return (const __DRIconfig **) configs; 327} 328 329#if defined(RADEON_R100) 330static const __DRItexOffsetExtension radeonTexOffsetExtension = { 331 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 332 radeonSetTexOffset, 333}; 334 335static const __DRItexBufferExtension radeonTexBufferExtension = { 336 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 337 radeonSetTexBuffer, 338 radeonSetTexBuffer2, 339}; 340#endif 341 342#if defined(RADEON_R200) 343static const __DRIallocateExtension r200AllocateExtension = { 344 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 345 r200AllocateMemoryMESA, 346 r200FreeMemoryMESA, 347 r200GetMemoryOffsetMESA 348}; 349 350static const __DRItexOffsetExtension r200texOffsetExtension = { 351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 352 r200SetTexOffset, 353}; 354 355static const __DRItexBufferExtension r200TexBufferExtension = { 356 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 357 r200SetTexBuffer, 358 r200SetTexBuffer2, 359}; 360#endif 361 362#if defined(RADEON_R300) 363static const __DRItexOffsetExtension r300texOffsetExtension = { 364 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 365 r300SetTexOffset, 366}; 367 368static const __DRItexBufferExtension r300TexBufferExtension = { 369 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 370 r300SetTexBuffer, 371 r300SetTexBuffer2, 372}; 373#endif 374 375#if defined(RADEON_R600) 376static const __DRItexOffsetExtension r600texOffsetExtension = { 377 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 378 r600SetTexOffset, /* +r6/r7 */ 379}; 380 381static const __DRItexBufferExtension r600TexBufferExtension = { 382 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 383 r600SetTexBuffer, /* +r6/r7 */ 384 r600SetTexBuffer2, /* +r6/r7 */ 385}; 386#endif 387 388static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 389{ 390 screen->device_id = device_id; 391 screen->chip_flags = 0; 392 switch ( device_id ) { 393 case PCI_CHIP_RN50_515E: 394 case PCI_CHIP_RN50_5969: 395 return -1; 396 397 case PCI_CHIP_RADEON_LY: 398 case PCI_CHIP_RADEON_LZ: 399 case PCI_CHIP_RADEON_QY: 400 case PCI_CHIP_RADEON_QZ: 401 screen->chip_family = CHIP_FAMILY_RV100; 402 break; 403 404 case PCI_CHIP_RS100_4136: 405 case PCI_CHIP_RS100_4336: 406 screen->chip_family = CHIP_FAMILY_RS100; 407 break; 408 409 case PCI_CHIP_RS200_4137: 410 case PCI_CHIP_RS200_4337: 411 case PCI_CHIP_RS250_4237: 412 case PCI_CHIP_RS250_4437: 413 screen->chip_family = CHIP_FAMILY_RS200; 414 break; 415 416 case PCI_CHIP_RADEON_QD: 417 case PCI_CHIP_RADEON_QE: 418 case PCI_CHIP_RADEON_QF: 419 case PCI_CHIP_RADEON_QG: 420 /* all original radeons (7200) presumably have a stencil op bug */ 421 screen->chip_family = CHIP_FAMILY_R100; 422 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 423 break; 424 425 case PCI_CHIP_RV200_QW: 426 case PCI_CHIP_RV200_QX: 427 case PCI_CHIP_RADEON_LW: 428 case PCI_CHIP_RADEON_LX: 429 screen->chip_family = CHIP_FAMILY_RV200; 430 screen->chip_flags = RADEON_CHIPSET_TCL; 431 break; 432 433 case PCI_CHIP_R200_BB: 434 case PCI_CHIP_R200_BC: 435 case PCI_CHIP_R200_QH: 436 case PCI_CHIP_R200_QL: 437 case PCI_CHIP_R200_QM: 438 screen->chip_family = CHIP_FAMILY_R200; 439 screen->chip_flags = RADEON_CHIPSET_TCL; 440 break; 441 442 case PCI_CHIP_RV250_If: 443 case PCI_CHIP_RV250_Ig: 444 case PCI_CHIP_RV250_Ld: 445 case PCI_CHIP_RV250_Lf: 446 case PCI_CHIP_RV250_Lg: 447 screen->chip_family = CHIP_FAMILY_RV250; 448 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 449 break; 450 451 case PCI_CHIP_RV280_5960: 452 case PCI_CHIP_RV280_5961: 453 case PCI_CHIP_RV280_5962: 454 case PCI_CHIP_RV280_5964: 455 case PCI_CHIP_RV280_5965: 456 case PCI_CHIP_RV280_5C61: 457 case PCI_CHIP_RV280_5C63: 458 screen->chip_family = CHIP_FAMILY_RV280; 459 screen->chip_flags = RADEON_CHIPSET_TCL; 460 break; 461 462 case PCI_CHIP_RS300_5834: 463 case PCI_CHIP_RS300_5835: 464 case PCI_CHIP_RS350_7834: 465 case PCI_CHIP_RS350_7835: 466 screen->chip_family = CHIP_FAMILY_RS300; 467 break; 468 469 case PCI_CHIP_R300_AD: 470 case PCI_CHIP_R300_AE: 471 case PCI_CHIP_R300_AF: 472 case PCI_CHIP_R300_AG: 473 case PCI_CHIP_R300_ND: 474 case PCI_CHIP_R300_NE: 475 case PCI_CHIP_R300_NF: 476 case PCI_CHIP_R300_NG: 477 screen->chip_family = CHIP_FAMILY_R300; 478 screen->chip_flags = RADEON_CHIPSET_TCL; 479 break; 480 481 case PCI_CHIP_RV350_AP: 482 case PCI_CHIP_RV350_AQ: 483 case PCI_CHIP_RV350_AR: 484 case PCI_CHIP_RV350_AS: 485 case PCI_CHIP_RV350_AT: 486 case PCI_CHIP_RV350_AV: 487 case PCI_CHIP_RV350_AU: 488 case PCI_CHIP_RV350_NP: 489 case PCI_CHIP_RV350_NQ: 490 case PCI_CHIP_RV350_NR: 491 case PCI_CHIP_RV350_NS: 492 case PCI_CHIP_RV350_NT: 493 case PCI_CHIP_RV350_NV: 494 screen->chip_family = CHIP_FAMILY_RV350; 495 screen->chip_flags = RADEON_CHIPSET_TCL; 496 break; 497 498 case PCI_CHIP_R350_AH: 499 case PCI_CHIP_R350_AI: 500 case PCI_CHIP_R350_AJ: 501 case PCI_CHIP_R350_AK: 502 case PCI_CHIP_R350_NH: 503 case PCI_CHIP_R350_NI: 504 case PCI_CHIP_R360_NJ: 505 case PCI_CHIP_R350_NK: 506 screen->chip_family = CHIP_FAMILY_R350; 507 screen->chip_flags = RADEON_CHIPSET_TCL; 508 break; 509 510 case PCI_CHIP_RV370_5460: 511 case PCI_CHIP_RV370_5462: 512 case PCI_CHIP_RV370_5464: 513 case PCI_CHIP_RV370_5B60: 514 case PCI_CHIP_RV370_5B62: 515 case PCI_CHIP_RV370_5B63: 516 case PCI_CHIP_RV370_5B64: 517 case PCI_CHIP_RV370_5B65: 518 case PCI_CHIP_RV380_3150: 519 case PCI_CHIP_RV380_3152: 520 case PCI_CHIP_RV380_3154: 521 case PCI_CHIP_RV380_3E50: 522 case PCI_CHIP_RV380_3E54: 523 screen->chip_family = CHIP_FAMILY_RV380; 524 screen->chip_flags = RADEON_CHIPSET_TCL; 525 break; 526 527 case PCI_CHIP_R420_JN: 528 case PCI_CHIP_R420_JH: 529 case PCI_CHIP_R420_JI: 530 case PCI_CHIP_R420_JJ: 531 case PCI_CHIP_R420_JK: 532 case PCI_CHIP_R420_JL: 533 case PCI_CHIP_R420_JM: 534 case PCI_CHIP_R420_JO: 535 case PCI_CHIP_R420_JP: 536 case PCI_CHIP_R420_JT: 537 case PCI_CHIP_R481_4B49: 538 case PCI_CHIP_R481_4B4A: 539 case PCI_CHIP_R481_4B4B: 540 case PCI_CHIP_R481_4B4C: 541 case PCI_CHIP_R423_UH: 542 case PCI_CHIP_R423_UI: 543 case PCI_CHIP_R423_UJ: 544 case PCI_CHIP_R423_UK: 545 case PCI_CHIP_R430_554C: 546 case PCI_CHIP_R430_554D: 547 case PCI_CHIP_R430_554E: 548 case PCI_CHIP_R430_554F: 549 case PCI_CHIP_R423_5550: 550 case PCI_CHIP_R423_UQ: 551 case PCI_CHIP_R423_UR: 552 case PCI_CHIP_R423_UT: 553 case PCI_CHIP_R430_5D48: 554 case PCI_CHIP_R430_5D49: 555 case PCI_CHIP_R430_5D4A: 556 case PCI_CHIP_R480_5D4C: 557 case PCI_CHIP_R480_5D4D: 558 case PCI_CHIP_R480_5D4E: 559 case PCI_CHIP_R480_5D4F: 560 case PCI_CHIP_R480_5D50: 561 case PCI_CHIP_R480_5D52: 562 case PCI_CHIP_R423_5D57: 563 screen->chip_family = CHIP_FAMILY_R420; 564 screen->chip_flags = RADEON_CHIPSET_TCL; 565 break; 566 567 case PCI_CHIP_RV410_5E4C: 568 case PCI_CHIP_RV410_5E4F: 569 case PCI_CHIP_RV410_564A: 570 case PCI_CHIP_RV410_564B: 571 case PCI_CHIP_RV410_564F: 572 case PCI_CHIP_RV410_5652: 573 case PCI_CHIP_RV410_5653: 574 case PCI_CHIP_RV410_5657: 575 case PCI_CHIP_RV410_5E48: 576 case PCI_CHIP_RV410_5E4A: 577 case PCI_CHIP_RV410_5E4B: 578 case PCI_CHIP_RV410_5E4D: 579 screen->chip_family = CHIP_FAMILY_RV410; 580 screen->chip_flags = RADEON_CHIPSET_TCL; 581 break; 582 583 case PCI_CHIP_RS480_5954: 584 case PCI_CHIP_RS480_5955: 585 case PCI_CHIP_RS482_5974: 586 case PCI_CHIP_RS482_5975: 587 case PCI_CHIP_RS400_5A41: 588 case PCI_CHIP_RS400_5A42: 589 case PCI_CHIP_RC410_5A61: 590 case PCI_CHIP_RC410_5A62: 591 screen->chip_family = CHIP_FAMILY_RS400; 592 break; 593 594 case PCI_CHIP_RS600_793F: 595 case PCI_CHIP_RS600_7941: 596 case PCI_CHIP_RS600_7942: 597 screen->chip_family = CHIP_FAMILY_RS600; 598 break; 599 600 case PCI_CHIP_RS690_791E: 601 case PCI_CHIP_RS690_791F: 602 screen->chip_family = CHIP_FAMILY_RS690; 603 break; 604 case PCI_CHIP_RS740_796C: 605 case PCI_CHIP_RS740_796D: 606 case PCI_CHIP_RS740_796E: 607 case PCI_CHIP_RS740_796F: 608 screen->chip_family = CHIP_FAMILY_RS740; 609 break; 610 611 case PCI_CHIP_R520_7100: 612 case PCI_CHIP_R520_7101: 613 case PCI_CHIP_R520_7102: 614 case PCI_CHIP_R520_7103: 615 case PCI_CHIP_R520_7104: 616 case PCI_CHIP_R520_7105: 617 case PCI_CHIP_R520_7106: 618 case PCI_CHIP_R520_7108: 619 case PCI_CHIP_R520_7109: 620 case PCI_CHIP_R520_710A: 621 case PCI_CHIP_R520_710B: 622 case PCI_CHIP_R520_710C: 623 case PCI_CHIP_R520_710E: 624 case PCI_CHIP_R520_710F: 625 screen->chip_family = CHIP_FAMILY_R520; 626 screen->chip_flags = RADEON_CHIPSET_TCL; 627 break; 628 629 case PCI_CHIP_RV515_7140: 630 case PCI_CHIP_RV515_7141: 631 case PCI_CHIP_RV515_7142: 632 case PCI_CHIP_RV515_7143: 633 case PCI_CHIP_RV515_7144: 634 case PCI_CHIP_RV515_7145: 635 case PCI_CHIP_RV515_7146: 636 case PCI_CHIP_RV515_7147: 637 case PCI_CHIP_RV515_7149: 638 case PCI_CHIP_RV515_714A: 639 case PCI_CHIP_RV515_714B: 640 case PCI_CHIP_RV515_714C: 641 case PCI_CHIP_RV515_714D: 642 case PCI_CHIP_RV515_714E: 643 case PCI_CHIP_RV515_714F: 644 case PCI_CHIP_RV515_7151: 645 case PCI_CHIP_RV515_7152: 646 case PCI_CHIP_RV515_7153: 647 case PCI_CHIP_RV515_715E: 648 case PCI_CHIP_RV515_715F: 649 case PCI_CHIP_RV515_7180: 650 case PCI_CHIP_RV515_7181: 651 case PCI_CHIP_RV515_7183: 652 case PCI_CHIP_RV515_7186: 653 case PCI_CHIP_RV515_7187: 654 case PCI_CHIP_RV515_7188: 655 case PCI_CHIP_RV515_718A: 656 case PCI_CHIP_RV515_718B: 657 case PCI_CHIP_RV515_718C: 658 case PCI_CHIP_RV515_718D: 659 case PCI_CHIP_RV515_718F: 660 case PCI_CHIP_RV515_7193: 661 case PCI_CHIP_RV515_7196: 662 case PCI_CHIP_RV515_719B: 663 case PCI_CHIP_RV515_719F: 664 case PCI_CHIP_RV515_7200: 665 case PCI_CHIP_RV515_7210: 666 case PCI_CHIP_RV515_7211: 667 screen->chip_family = CHIP_FAMILY_RV515; 668 screen->chip_flags = RADEON_CHIPSET_TCL; 669 break; 670 671 case PCI_CHIP_RV530_71C0: 672 case PCI_CHIP_RV530_71C1: 673 case PCI_CHIP_RV530_71C2: 674 case PCI_CHIP_RV530_71C3: 675 case PCI_CHIP_RV530_71C4: 676 case PCI_CHIP_RV530_71C5: 677 case PCI_CHIP_RV530_71C6: 678 case PCI_CHIP_RV530_71C7: 679 case PCI_CHIP_RV530_71CD: 680 case PCI_CHIP_RV530_71CE: 681 case PCI_CHIP_RV530_71D2: 682 case PCI_CHIP_RV530_71D4: 683 case PCI_CHIP_RV530_71D5: 684 case PCI_CHIP_RV530_71D6: 685 case PCI_CHIP_RV530_71DA: 686 case PCI_CHIP_RV530_71DE: 687 screen->chip_family = CHIP_FAMILY_RV530; 688 screen->chip_flags = RADEON_CHIPSET_TCL; 689 break; 690 691 case PCI_CHIP_R580_7240: 692 case PCI_CHIP_R580_7243: 693 case PCI_CHIP_R580_7244: 694 case PCI_CHIP_R580_7245: 695 case PCI_CHIP_R580_7246: 696 case PCI_CHIP_R580_7247: 697 case PCI_CHIP_R580_7248: 698 case PCI_CHIP_R580_7249: 699 case PCI_CHIP_R580_724A: 700 case PCI_CHIP_R580_724B: 701 case PCI_CHIP_R580_724C: 702 case PCI_CHIP_R580_724D: 703 case PCI_CHIP_R580_724E: 704 case PCI_CHIP_R580_724F: 705 case PCI_CHIP_R580_7284: 706 screen->chip_family = CHIP_FAMILY_R580; 707 screen->chip_flags = RADEON_CHIPSET_TCL; 708 break; 709 710 case PCI_CHIP_RV570_7280: 711 case PCI_CHIP_RV560_7281: 712 case PCI_CHIP_RV560_7283: 713 case PCI_CHIP_RV560_7287: 714 case PCI_CHIP_RV570_7288: 715 case PCI_CHIP_RV570_7289: 716 case PCI_CHIP_RV570_728B: 717 case PCI_CHIP_RV570_728C: 718 case PCI_CHIP_RV560_7290: 719 case PCI_CHIP_RV560_7291: 720 case PCI_CHIP_RV560_7293: 721 case PCI_CHIP_RV560_7297: 722 screen->chip_family = CHIP_FAMILY_RV560; 723 screen->chip_flags = RADEON_CHIPSET_TCL; 724 break; 725 726 case PCI_CHIP_R600_9400: 727 case PCI_CHIP_R600_9401: 728 case PCI_CHIP_R600_9402: 729 case PCI_CHIP_R600_9403: 730 case PCI_CHIP_R600_9405: 731 case PCI_CHIP_R600_940A: 732 case PCI_CHIP_R600_940B: 733 case PCI_CHIP_R600_940F: 734 screen->chip_family = CHIP_FAMILY_R600; 735 screen->chip_flags = RADEON_CHIPSET_TCL; 736 break; 737 738 case PCI_CHIP_RV610_94C0: 739 case PCI_CHIP_RV610_94C1: 740 case PCI_CHIP_RV610_94C3: 741 case PCI_CHIP_RV610_94C4: 742 case PCI_CHIP_RV610_94C5: 743 case PCI_CHIP_RV610_94C6: 744 case PCI_CHIP_RV610_94C7: 745 case PCI_CHIP_RV610_94C8: 746 case PCI_CHIP_RV610_94C9: 747 case PCI_CHIP_RV610_94CB: 748 case PCI_CHIP_RV610_94CC: 749 case PCI_CHIP_RV610_94CD: 750 screen->chip_family = CHIP_FAMILY_RV610; 751 screen->chip_flags = RADEON_CHIPSET_TCL; 752 break; 753 754 case PCI_CHIP_RV630_9580: 755 case PCI_CHIP_RV630_9581: 756 case PCI_CHIP_RV630_9583: 757 case PCI_CHIP_RV630_9586: 758 case PCI_CHIP_RV630_9587: 759 case PCI_CHIP_RV630_9588: 760 case PCI_CHIP_RV630_9589: 761 case PCI_CHIP_RV630_958A: 762 case PCI_CHIP_RV630_958B: 763 case PCI_CHIP_RV630_958C: 764 case PCI_CHIP_RV630_958D: 765 case PCI_CHIP_RV630_958E: 766 case PCI_CHIP_RV630_958F: 767 screen->chip_family = CHIP_FAMILY_RV630; 768 screen->chip_flags = RADEON_CHIPSET_TCL; 769 break; 770 771 case PCI_CHIP_RV670_9500: 772 case PCI_CHIP_RV670_9501: 773 case PCI_CHIP_RV670_9504: 774 case PCI_CHIP_RV670_9505: 775 case PCI_CHIP_RV670_9506: 776 case PCI_CHIP_RV670_9507: 777 case PCI_CHIP_RV670_9508: 778 case PCI_CHIP_RV670_9509: 779 case PCI_CHIP_RV670_950F: 780 case PCI_CHIP_RV670_9511: 781 case PCI_CHIP_RV670_9515: 782 case PCI_CHIP_RV670_9517: 783 case PCI_CHIP_RV670_9519: 784 screen->chip_family = CHIP_FAMILY_RV670; 785 screen->chip_flags = RADEON_CHIPSET_TCL; 786 break; 787 788 case PCI_CHIP_RV620_95C0: 789 case PCI_CHIP_RV620_95C2: 790 case PCI_CHIP_RV620_95C4: 791 case PCI_CHIP_RV620_95C5: 792 case PCI_CHIP_RV620_95C6: 793 case PCI_CHIP_RV620_95C7: 794 case PCI_CHIP_RV620_95C9: 795 case PCI_CHIP_RV620_95CC: 796 case PCI_CHIP_RV620_95CD: 797 case PCI_CHIP_RV620_95CE: 798 case PCI_CHIP_RV620_95CF: 799 screen->chip_family = CHIP_FAMILY_RV620; 800 screen->chip_flags = RADEON_CHIPSET_TCL; 801 break; 802 803 case PCI_CHIP_RV635_9590: 804 case PCI_CHIP_RV635_9591: 805 case PCI_CHIP_RV635_9593: 806 case PCI_CHIP_RV635_9595: 807 case PCI_CHIP_RV635_9596: 808 case PCI_CHIP_RV635_9597: 809 case PCI_CHIP_RV635_9598: 810 case PCI_CHIP_RV635_9599: 811 case PCI_CHIP_RV635_959B: 812 screen->chip_family = CHIP_FAMILY_RV635; 813 screen->chip_flags = RADEON_CHIPSET_TCL; 814 break; 815 816 case PCI_CHIP_RS780_9610: 817 case PCI_CHIP_RS780_9611: 818 case PCI_CHIP_RS780_9612: 819 case PCI_CHIP_RS780_9613: 820 case PCI_CHIP_RS780_9614: 821 case PCI_CHIP_RS780_9615: 822 case PCI_CHIP_RS780_9616: 823 screen->chip_family = CHIP_FAMILY_RS780; 824 screen->chip_flags = RADEON_CHIPSET_TCL; 825 break; 826 case PCI_CHIP_RS880_9710: 827 case PCI_CHIP_RS880_9711: 828 case PCI_CHIP_RS880_9712: 829 case PCI_CHIP_RS880_9713: 830 case PCI_CHIP_RS880_9714: 831 screen->chip_family = CHIP_FAMILY_RS880; 832 screen->chip_flags = RADEON_CHIPSET_TCL; 833 break; 834 835 case PCI_CHIP_RV770_9440: 836 case PCI_CHIP_RV770_9441: 837 case PCI_CHIP_RV770_9442: 838 case PCI_CHIP_RV770_9443: 839 case PCI_CHIP_RV770_9444: 840 case PCI_CHIP_RV770_9446: 841 case PCI_CHIP_RV770_944A: 842 case PCI_CHIP_RV770_944B: 843 case PCI_CHIP_RV770_944C: 844 case PCI_CHIP_RV770_944E: 845 case PCI_CHIP_RV770_9450: 846 case PCI_CHIP_RV770_9452: 847 case PCI_CHIP_RV770_9456: 848 case PCI_CHIP_RV770_945A: 849 case PCI_CHIP_RV770_945B: 850 case PCI_CHIP_RV790_9460: 851 case PCI_CHIP_RV790_9462: 852 case PCI_CHIP_RV770_946A: 853 case PCI_CHIP_RV770_946B: 854 case PCI_CHIP_RV770_947A: 855 case PCI_CHIP_RV770_947B: 856 screen->chip_family = CHIP_FAMILY_RV770; 857 screen->chip_flags = RADEON_CHIPSET_TCL; 858 break; 859 860 case PCI_CHIP_RV730_9480: 861 case PCI_CHIP_RV730_9487: 862 case PCI_CHIP_RV730_9488: 863 case PCI_CHIP_RV730_9489: 864 case PCI_CHIP_RV730_948F: 865 case PCI_CHIP_RV730_9490: 866 case PCI_CHIP_RV730_9491: 867 case PCI_CHIP_RV730_9495: 868 case PCI_CHIP_RV730_9498: 869 case PCI_CHIP_RV730_949C: 870 case PCI_CHIP_RV730_949E: 871 case PCI_CHIP_RV730_949F: 872 screen->chip_family = CHIP_FAMILY_RV730; 873 screen->chip_flags = RADEON_CHIPSET_TCL; 874 break; 875 876 case PCI_CHIP_RV710_9540: 877 case PCI_CHIP_RV710_9541: 878 case PCI_CHIP_RV710_9542: 879 case PCI_CHIP_RV710_954E: 880 case PCI_CHIP_RV710_954F: 881 case PCI_CHIP_RV710_9552: 882 case PCI_CHIP_RV710_9553: 883 case PCI_CHIP_RV710_9555: 884 case PCI_CHIP_RV710_9557: 885 screen->chip_family = CHIP_FAMILY_RV710; 886 screen->chip_flags = RADEON_CHIPSET_TCL; 887 break; 888 889 case PCI_CHIP_RV740_94A0: 890 case PCI_CHIP_RV740_94A1: 891 case PCI_CHIP_RV740_94A3: 892 case PCI_CHIP_RV740_94B1: 893 case PCI_CHIP_RV740_94B3: 894 case PCI_CHIP_RV740_94B4: 895 case PCI_CHIP_RV740_94B5: 896 case PCI_CHIP_RV740_94B9: 897 screen->chip_family = CHIP_FAMILY_RV740; 898 screen->chip_flags = RADEON_CHIPSET_TCL; 899 break; 900 901 default: 902 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 903 device_id); 904 return -1; 905 } 906 907 return 0; 908} 909 910 911/* Create the device specific screen private data struct. 912 */ 913static radeonScreenPtr 914radeonCreateScreen( __DRIscreenPrivate *sPriv ) 915{ 916 radeonScreenPtr screen; 917 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 918 unsigned char *RADEONMMIO = NULL; 919 int i; 920 int ret; 921 uint32_t temp = 0; 922 923 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 924 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 925 return GL_FALSE; 926 } 927 928 /* Allocate the private area */ 929 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 930 if ( !screen ) { 931 __driUtilMessage("%s: Could not allocate memory for screen structure", 932 __FUNCTION__); 933 return NULL; 934 } 935 936 radeon_init_debug(); 937 938 /* parse information in __driConfigOptions */ 939 driParseOptionInfo (&screen->optionCache, 940 __driConfigOptions, __driNConfigOptions); 941 942 /* This is first since which regions we map depends on whether or 943 * not we are using a PCI card. 944 */ 945 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 946 { 947 int ret; 948 949 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 950 &screen->gart_buffer_offset); 951 952 if (ret) { 953 FREE( screen ); 954 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 955 return NULL; 956 } 957 958 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 959 &screen->gart_base); 960 if (ret) { 961 FREE( screen ); 962 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 963 return NULL; 964 } 965 966 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 967 &screen->irq); 968 if (ret) { 969 FREE( screen ); 970 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 971 return NULL; 972 } 973 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 974 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 975 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 976 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 977 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 978 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 979 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 980 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30); 981 } 982 983 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 984 if (ret == -1) 985 return NULL; 986 987 screen->mmio.handle = dri_priv->registerHandle; 988 screen->mmio.size = dri_priv->registerSize; 989 if ( drmMap( sPriv->fd, 990 screen->mmio.handle, 991 screen->mmio.size, 992 &screen->mmio.map ) ) { 993 FREE( screen ); 994 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 995 return NULL; 996 } 997 998 RADEONMMIO = screen->mmio.map; 999 1000 screen->status.handle = dri_priv->statusHandle; 1001 screen->status.size = dri_priv->statusSize; 1002 if ( drmMap( sPriv->fd, 1003 screen->status.handle, 1004 screen->status.size, 1005 &screen->status.map ) ) { 1006 drmUnmap( screen->mmio.map, screen->mmio.size ); 1007 FREE( screen ); 1008 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1009 return NULL; 1010 } 1011 if (screen->chip_family < CHIP_FAMILY_R600) 1012 screen->scratch = (__volatile__ uint32_t *) 1013 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1014 else 1015 screen->scratch = (__volatile__ uint32_t *) 1016 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1017 1018 screen->buffers = drmMapBufs( sPriv->fd ); 1019 if ( !screen->buffers ) { 1020 drmUnmap( screen->status.map, screen->status.size ); 1021 drmUnmap( screen->mmio.map, screen->mmio.size ); 1022 FREE( screen ); 1023 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1024 return NULL; 1025 } 1026 1027 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1028 screen->gartTextures.handle = dri_priv->gartTexHandle; 1029 screen->gartTextures.size = dri_priv->gartTexMapSize; 1030 if ( drmMap( sPriv->fd, 1031 screen->gartTextures.handle, 1032 screen->gartTextures.size, 1033 (drmAddressPtr)&screen->gartTextures.map ) ) { 1034 drmUnmapBufs( screen->buffers ); 1035 drmUnmap( screen->status.map, screen->status.size ); 1036 drmUnmap( screen->mmio.map, screen->mmio.size ); 1037 FREE( screen ); 1038 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1039 return NULL; 1040 } 1041 1042 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1043 } 1044 1045 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1046 sPriv->ddx_version.minor < 2) { 1047 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1048 return NULL; 1049 } 1050 1051 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1052 fprintf(stderr, "R500 support requires a newer drm.\n"); 1053 return NULL; 1054 } 1055 1056 if (getenv("R300_NO_TCL")) 1057 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1058 1059 if (screen->chip_family <= CHIP_FAMILY_RS200) 1060 screen->chip_flags |= RADEON_CLASS_R100; 1061 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1062 screen->chip_flags |= RADEON_CLASS_R200; 1063 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1064 screen->chip_flags |= RADEON_CLASS_R300; 1065 else 1066 screen->chip_flags |= RADEON_CLASS_R600; 1067 1068 screen->cpp = dri_priv->bpp / 8; 1069 screen->AGPMode = dri_priv->AGPMode; 1070 1071 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1072 1073 /* +r6/r7 */ 1074 if(screen->chip_family >= CHIP_FAMILY_R600) 1075 { 1076 if (ret) 1077 { 1078 FREE( screen ); 1079 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1080 return NULL; 1081 } 1082 else 1083 { 1084 screen->fbLocation = (temp & 0xffff) << 24; 1085 } 1086 } 1087 else 1088 { 1089 if (ret) 1090 { 1091 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1092 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1093 else 1094 { 1095 FREE( screen ); 1096 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1097 return NULL; 1098 } 1099 } 1100 else 1101 { 1102 screen->fbLocation = (temp & 0xffff) << 16; 1103 } 1104 } 1105 1106 if (IS_R300_CLASS(screen)) { 1107 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1108 if (ret) { 1109 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1110 switch (screen->chip_family) { 1111 case CHIP_FAMILY_R300: 1112 case CHIP_FAMILY_R350: 1113 screen->num_gb_pipes = 2; 1114 break; 1115 case CHIP_FAMILY_R420: 1116 case CHIP_FAMILY_R520: 1117 case CHIP_FAMILY_R580: 1118 case CHIP_FAMILY_RV560: 1119 case CHIP_FAMILY_RV570: 1120 screen->num_gb_pipes = 4; 1121 break; 1122 case CHIP_FAMILY_RV350: 1123 case CHIP_FAMILY_RV515: 1124 case CHIP_FAMILY_RV530: 1125 case CHIP_FAMILY_RV410: 1126 default: 1127 screen->num_gb_pipes = 1; 1128 break; 1129 } 1130 } else { 1131 screen->num_gb_pipes = temp; 1132 } 1133 1134 /* pipe overrides */ 1135 switch (dri_priv->deviceID) { 1136 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1137 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1138 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1139 screen->num_gb_pipes = 1; 1140 break; 1141 default: 1142 break; 1143 } 1144 1145 if ( sPriv->drm_version.minor >= 31 ) { 1146 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1147 if (ret) 1148 screen->num_z_pipes = 2; 1149 else 1150 screen->num_z_pipes = temp; 1151 } else 1152 screen->num_z_pipes = 2; 1153 } 1154 1155 if ( sPriv->drm_version.minor >= 10 ) { 1156 drm_radeon_setparam_t sp; 1157 1158 sp.param = RADEON_SETPARAM_FB_LOCATION; 1159 sp.value = screen->fbLocation; 1160 1161 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1162 &sp, sizeof( sp ) ); 1163 } 1164 1165 screen->frontOffset = dri_priv->frontOffset; 1166 screen->frontPitch = dri_priv->frontPitch; 1167 screen->backOffset = dri_priv->backOffset; 1168 screen->backPitch = dri_priv->backPitch; 1169 screen->depthOffset = dri_priv->depthOffset; 1170 screen->depthPitch = dri_priv->depthPitch; 1171 1172 /* Check if ddx has set up a surface reg to cover depth buffer */ 1173 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1174 /* these chips don't use tiled z without hyperz. So always pretend 1175 we have set up a surface which will cause linear reads/writes */ 1176 (IS_R100_CLASS(screen) && 1177 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1178 1179 if ( dri_priv->textureSize == 0 ) { 1180 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1181 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1182 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1183 dri_priv->log2GARTTexGran; 1184 } else { 1185 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1186 + screen->fbLocation; 1187 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1188 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1189 dri_priv->log2TexGran; 1190 } 1191 1192 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1193 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1194 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1195 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1196 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1197 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1198 } else { 1199 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1200 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1201 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1202 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1203 dri_priv->log2GARTTexGran; 1204 } 1205 1206 i = 0; 1207 screen->extensions[i++] = &driCopySubBufferExtension.base; 1208 screen->extensions[i++] = &driFrameTrackingExtension.base; 1209 screen->extensions[i++] = &driReadDrawableExtension; 1210 1211 if ( screen->irq != 0 ) { 1212 screen->extensions[i++] = &driSwapControlExtension.base; 1213 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1214 } 1215 1216#if defined(RADEON_R100) 1217 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1218#endif 1219 1220#if defined(RADEON_R200) 1221 if (IS_R200_CLASS(screen)) 1222 screen->extensions[i++] = &r200AllocateExtension.base; 1223 1224 screen->extensions[i++] = &r200texOffsetExtension.base; 1225#endif 1226 1227#if defined(RADEON_R300) 1228 screen->extensions[i++] = &r300texOffsetExtension.base; 1229#endif 1230 1231#if defined(RADEON_R600) 1232 screen->extensions[i++] = &r600texOffsetExtension.base; 1233#endif 1234 1235 screen->extensions[i++] = NULL; 1236 sPriv->extensions = screen->extensions; 1237 1238 screen->driScreen = sPriv; 1239 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1240 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1241 screen->sarea_priv_offset); 1242 1243 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1244 if (screen->bom == NULL) { 1245 free(screen); 1246 return NULL; 1247 } 1248 1249 return screen; 1250} 1251 1252static radeonScreenPtr 1253radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1254{ 1255 radeonScreenPtr screen; 1256 int i; 1257 int ret; 1258 uint32_t device_id = 0; 1259 uint32_t temp = 0; 1260 1261 /* Allocate the private area */ 1262 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1263 if ( !screen ) { 1264 __driUtilMessage("%s: Could not allocate memory for screen structure", 1265 __FUNCTION__); 1266 fprintf(stderr, "leaving here\n"); 1267 return NULL; 1268 } 1269 1270 radeon_init_debug(); 1271 1272 /* parse information in __driConfigOptions */ 1273 driParseOptionInfo (&screen->optionCache, 1274 __driConfigOptions, __driNConfigOptions); 1275 1276 screen->kernel_mm = 1; 1277 screen->chip_flags = 0; 1278 1279 /* if we have kms we can support all of these */ 1280 screen->drmSupportsCubeMapsR200 = 1; 1281 screen->drmSupportsBlendColor = 1; 1282 screen->drmSupportsTriPerf = 1; 1283 screen->drmSupportsFragShader = 1; 1284 screen->drmSupportsPointSprites = 1; 1285 screen->drmSupportsCubeMapsR100 = 1; 1286 screen->drmSupportsVertexProgram = 1; 1287 screen->drmSupportsOcclusionQueries = 1; 1288 screen->irq = 1; 1289 1290 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1291 if (ret) { 1292 FREE( screen ); 1293 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1294 return NULL; 1295 } 1296 1297 ret = radeon_set_screen_flags(screen, device_id); 1298 if (ret == -1) 1299 return NULL; 1300 1301 if (getenv("R300_NO_TCL")) 1302 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1303 1304 if (screen->chip_family <= CHIP_FAMILY_RS200) 1305 screen->chip_flags |= RADEON_CLASS_R100; 1306 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1307 screen->chip_flags |= RADEON_CLASS_R200; 1308 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1309 screen->chip_flags |= RADEON_CLASS_R300; 1310 else 1311 screen->chip_flags |= RADEON_CLASS_R600; 1312 1313 if (IS_R300_CLASS(screen)) { 1314 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1315 if (ret) { 1316 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1317 switch (screen->chip_family) { 1318 case CHIP_FAMILY_R300: 1319 case CHIP_FAMILY_R350: 1320 screen->num_gb_pipes = 2; 1321 break; 1322 case CHIP_FAMILY_R420: 1323 case CHIP_FAMILY_R520: 1324 case CHIP_FAMILY_R580: 1325 case CHIP_FAMILY_RV560: 1326 case CHIP_FAMILY_RV570: 1327 screen->num_gb_pipes = 4; 1328 break; 1329 case CHIP_FAMILY_RV350: 1330 case CHIP_FAMILY_RV515: 1331 case CHIP_FAMILY_RV530: 1332 case CHIP_FAMILY_RV410: 1333 default: 1334 screen->num_gb_pipes = 1; 1335 break; 1336 } 1337 } else { 1338 screen->num_gb_pipes = temp; 1339 } 1340 1341 /* pipe overrides */ 1342 switch (device_id) { 1343 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1344 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1345 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1346 screen->num_gb_pipes = 1; 1347 break; 1348 default: 1349 break; 1350 } 1351 1352 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1353 if (ret) 1354 screen->num_z_pipes = 2; 1355 else 1356 screen->num_z_pipes = temp; 1357 1358 } 1359 1360 i = 0; 1361 screen->extensions[i++] = &driCopySubBufferExtension.base; 1362 screen->extensions[i++] = &driFrameTrackingExtension.base; 1363 screen->extensions[i++] = &driReadDrawableExtension; 1364 1365 if ( screen->irq != 0 ) { 1366 screen->extensions[i++] = &driSwapControlExtension.base; 1367 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1368 } 1369 1370#if defined(RADEON_R100) 1371 screen->extensions[i++] = &radeonTexBufferExtension.base; 1372#endif 1373 1374#if defined(RADEON_R200) 1375 if (IS_R200_CLASS(screen)) 1376 screen->extensions[i++] = &r200AllocateExtension.base; 1377 1378 screen->extensions[i++] = &r200TexBufferExtension.base; 1379#endif 1380 1381#if defined(RADEON_R300) 1382 screen->extensions[i++] = &r300TexBufferExtension.base; 1383#endif 1384 1385#if defined(RADEON_R600) 1386 screen->extensions[i++] = &r600TexBufferExtension.base; 1387#endif 1388 1389 screen->extensions[i++] = NULL; 1390 sPriv->extensions = screen->extensions; 1391 1392 screen->driScreen = sPriv; 1393 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1394 if (screen->bom == NULL) { 1395 free(screen); 1396 return NULL; 1397 } 1398 return screen; 1399} 1400 1401/* Destroy the device specific screen private data struct. 1402 */ 1403static void 1404radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1405{ 1406 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1407 1408 if (!screen) 1409 return; 1410 1411 if (screen->kernel_mm) { 1412#ifdef RADEON_BO_TRACK 1413 radeon_tracker_print(&screen->bom->tracker, stderr); 1414#endif 1415 radeon_bo_manager_gem_dtor(screen->bom); 1416 } else { 1417 radeon_bo_manager_legacy_dtor(screen->bom); 1418 1419 if ( screen->gartTextures.map ) { 1420 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1421 } 1422 drmUnmapBufs( screen->buffers ); 1423 drmUnmap( screen->status.map, screen->status.size ); 1424 drmUnmap( screen->mmio.map, screen->mmio.size ); 1425 } 1426 1427 /* free all option information */ 1428 driDestroyOptionInfo (&screen->optionCache); 1429 1430 FREE( screen ); 1431 sPriv->private = NULL; 1432} 1433 1434 1435/* Initialize the driver specific screen private data. 1436 */ 1437static GLboolean 1438radeonInitDriver( __DRIscreenPrivate *sPriv ) 1439{ 1440 if (sPriv->dri2.enabled) { 1441 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1442 } else { 1443 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1444 } 1445 if ( !sPriv->private ) { 1446 radeonDestroyScreen( sPriv ); 1447 return GL_FALSE; 1448 } 1449 1450 return GL_TRUE; 1451} 1452 1453 1454 1455/** 1456 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1457 * 1458 * \todo This function (and its interface) will need to be updated to support 1459 * pbuffers. 1460 */ 1461static GLboolean 1462radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1463 __DRIdrawablePrivate *driDrawPriv, 1464 const __GLcontextModes *mesaVis, 1465 GLboolean isPixmap ) 1466{ 1467 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1468 1469 const GLboolean swDepth = GL_FALSE; 1470 const GLboolean swAlpha = GL_FALSE; 1471 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1472 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1473 mesaVis->depthBits != 24; 1474 gl_format rgbFormat; 1475 struct radeon_framebuffer *rfb; 1476 1477 if (isPixmap) 1478 return GL_FALSE; /* not implemented */ 1479 1480 rfb = CALLOC_STRUCT(radeon_framebuffer); 1481 if (!rfb) 1482 return GL_FALSE; 1483 1484 _mesa_initialize_framebuffer(&rfb->base, mesaVis); 1485 1486 if (mesaVis->redBits == 5) 1487 rgbFormat = MESA_FORMAT_RGB565; 1488 else if (mesaVis->alphaBits == 0) 1489 rgbFormat = MESA_FORMAT_XRGB8888; 1490 else 1491 rgbFormat = MESA_FORMAT_ARGB8888; 1492 1493 /* front color renderbuffer */ 1494 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1495 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1496 rfb->color_rb[0]->has_surface = 1; 1497 1498 /* back color renderbuffer */ 1499 if (mesaVis->doubleBufferMode) { 1500 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1501 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1502 rfb->color_rb[1]->has_surface = 1; 1503 } 1504 1505 if (mesaVis->depthBits == 24) { 1506 if (mesaVis->stencilBits == 8) { 1507 struct radeon_renderbuffer *depthStencilRb = 1508 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1509 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1510 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1511 depthStencilRb->has_surface = screen->depthHasSurface; 1512 } else { 1513 /* depth renderbuffer */ 1514 struct radeon_renderbuffer *depth = 1515 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1516 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1517 depth->has_surface = screen->depthHasSurface; 1518 } 1519 } else if (mesaVis->depthBits == 16) { 1520 /* just 16-bit depth buffer, no hw stencil */ 1521 struct radeon_renderbuffer *depth = 1522 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1523 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1524 depth->has_surface = screen->depthHasSurface; 1525 } 1526 1527 _mesa_add_soft_renderbuffers(&rfb->base, 1528 GL_FALSE, /* color */ 1529 swDepth, 1530 swStencil, 1531 swAccum, 1532 swAlpha, 1533 GL_FALSE /* aux */); 1534 driDrawPriv->driverPrivate = (void *) rfb; 1535 1536 return (driDrawPriv->driverPrivate != NULL); 1537} 1538 1539 1540static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1541{ 1542 struct radeon_renderbuffer *rb; 1543 1544 rb = rfb->color_rb[0]; 1545 if (rb && rb->bo) { 1546 radeon_bo_unref(rb->bo); 1547 rb->bo = NULL; 1548 } 1549 rb = rfb->color_rb[1]; 1550 if (rb && rb->bo) { 1551 radeon_bo_unref(rb->bo); 1552 rb->bo = NULL; 1553 } 1554 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1555 if (rb && rb->bo) { 1556 radeon_bo_unref(rb->bo); 1557 rb->bo = NULL; 1558 } 1559} 1560 1561void 1562radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1563{ 1564 struct radeon_framebuffer *rfb; 1565 if (!driDrawPriv) 1566 return; 1567 1568 rfb = (void*)driDrawPriv->driverPrivate; 1569 if (!rfb) 1570 return; 1571 radeon_cleanup_renderbuffers(rfb); 1572 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1573} 1574 1575 1576/** 1577 * This is the driver specific part of the createNewScreen entry point. 1578 * 1579 * \todo maybe fold this into intelInitDriver 1580 * 1581 * \return the __GLcontextModes supported by this driver 1582 */ 1583static const __DRIconfig ** 1584radeonInitScreen(__DRIscreenPrivate *psp) 1585{ 1586#if defined(RADEON_R100) 1587 static const char *driver_name = "Radeon"; 1588 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1589 static const __DRIversion dri_expected = { 4, 0, 0 }; 1590 static const __DRIversion drm_expected = { 1, 6, 0 }; 1591#elif defined(RADEON_R200) 1592 static const char *driver_name = "R200"; 1593 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1594 static const __DRIversion dri_expected = { 4, 0, 0 }; 1595 static const __DRIversion drm_expected = { 1, 6, 0 }; 1596#elif defined(RADEON_R300) 1597 static const char *driver_name = "R300"; 1598 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1599 static const __DRIversion dri_expected = { 4, 0, 0 }; 1600 static const __DRIversion drm_expected = { 1, 24, 0 }; 1601#elif defined(RADEON_R600) 1602 static const char *driver_name = "R600"; 1603 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1604 static const __DRIversion dri_expected = { 4, 0, 0 }; 1605 static const __DRIversion drm_expected = { 1, 24, 0 }; 1606#endif 1607 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1608 1609 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1610 &psp->dri_version, & dri_expected, 1611 &psp->ddx_version, & ddx_expected, 1612 &psp->drm_version, & drm_expected ) ) { 1613 return NULL; 1614 } 1615 1616 if (!radeonInitDriver(psp)) 1617 return NULL; 1618 1619 /* for now fill in all modes */ 1620 return radeonFillInModes( psp, 1621 dri_priv->bpp, 1622 (dri_priv->bpp == 16) ? 16 : 24, 1623 (dri_priv->bpp == 16) ? 0 : 8, 1); 1624} 1625#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1626 1627/** 1628 * This is the driver specific part of the createNewScreen entry point. 1629 * Called when using DRI2. 1630 * 1631 * \return the __GLcontextModes supported by this driver 1632 */ 1633static const 1634__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1635{ 1636 GLenum fb_format[3]; 1637 GLenum fb_type[3]; 1638 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1639 * support pageflipping at all. 1640 */ 1641 static const GLenum back_buffer_modes[] = { 1642 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1643 }; 1644 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1645 int color; 1646 __DRIconfig **configs = NULL; 1647 1648 if (!radeonInitDriver(psp)) { 1649 return NULL; 1650 } 1651 depth_bits[0] = 0; 1652 stencil_bits[0] = 0; 1653 depth_bits[1] = 16; 1654 stencil_bits[1] = 0; 1655 depth_bits[2] = 24; 1656 stencil_bits[2] = 0; 1657 depth_bits[3] = 24; 1658 stencil_bits[3] = 8; 1659 1660 msaa_samples_array[0] = 0; 1661 1662 fb_format[0] = GL_RGB; 1663 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1664 1665 fb_format[1] = GL_BGR; 1666 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1667 1668 fb_format[2] = GL_BGRA; 1669 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1670 1671 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1672 __DRIconfig **new_configs; 1673 1674 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1675 depth_bits, 1676 stencil_bits, 1677 ARRAY_SIZE(depth_bits), 1678 back_buffer_modes, 1679 ARRAY_SIZE(back_buffer_modes), 1680 msaa_samples_array, 1681 ARRAY_SIZE(msaa_samples_array)); 1682 if (configs == NULL) 1683 configs = new_configs; 1684 else 1685 configs = driConcatConfigs(configs, new_configs); 1686 } 1687 1688 if (configs == NULL) { 1689 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1690 __LINE__); 1691 return NULL; 1692 } 1693 1694 return (const __DRIconfig **)configs; 1695} 1696 1697/** 1698 * Get information about previous buffer swaps. 1699 */ 1700static int 1701getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1702{ 1703 struct radeon_framebuffer *rfb; 1704 1705 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1706 || (dPriv->driContextPriv->driverPrivate == NULL) 1707 || (sInfo == NULL) ) { 1708 return -1; 1709 } 1710 1711 rfb = dPriv->driverPrivate; 1712 sInfo->swap_count = rfb->swap_count; 1713 sInfo->swap_ust = rfb->swap_ust; 1714 sInfo->swap_missed_count = rfb->swap_missed_count; 1715 1716 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1717 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1718 : 0.0; 1719 1720 return 0; 1721} 1722 1723const struct __DriverAPIRec driDriverAPI = { 1724 .InitScreen = radeonInitScreen, 1725 .DestroyScreen = radeonDestroyScreen, 1726#if defined(RADEON_R200) 1727 .CreateContext = r200CreateContext, 1728 .DestroyContext = r200DestroyContext, 1729#elif defined(RADEON_R600) 1730 .CreateContext = r600CreateContext, 1731 .DestroyContext = radeonDestroyContext, 1732#elif defined(RADEON_R300) 1733 .CreateContext = r300CreateContext, 1734 .DestroyContext = radeonDestroyContext, 1735#else 1736 .CreateContext = r100CreateContext, 1737 .DestroyContext = radeonDestroyContext, 1738#endif 1739 .CreateBuffer = radeonCreateBuffer, 1740 .DestroyBuffer = radeonDestroyBuffer, 1741 .SwapBuffers = radeonSwapBuffers, 1742 .MakeCurrent = radeonMakeCurrent, 1743 .UnbindContext = radeonUnbindContext, 1744 .GetSwapInfo = getSwapInfo, 1745 .GetDrawableMSC = driDrawableGetMSC32, 1746 .WaitForMSC = driWaitForMSC32, 1747 .WaitForSBC = NULL, 1748 .SwapBuffersMSC = NULL, 1749 .CopySubBuffer = radeonCopySubBuffer, 1750 /* DRI2 */ 1751 .InitScreen2 = radeonInitScreen2, 1752}; 1753 1754