radeon_screen.c revision e24e4ae2e8f69447c0917655d25fa96b62b94298
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_fragprog.h" 61#include "r300_tex.h" 62#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 63#include "r600_context.h" 64#include "r600_fragprog.h" 65#include "r600_tex.h" 66#endif 67 68#include "utils.h" 69#include "vblank.h" 70#include "drirenderbuffer.h" 71 72#include "radeon_bocs_wrapper.h" 73 74#include "GL/internal/dri_interface.h" 75 76/* Radeon configuration 77 */ 78#include "xmlpool.h" 79 80#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 81DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 82 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 83 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 84DRI_CONF_OPT_END 85 86#if !RADEON_COMMON /* R100 */ 87PUBLIC const char __driConfigOptions[] = 88DRI_CONF_BEGIN 89 DRI_CONF_SECTION_PERFORMANCE 90 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 91 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 92 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 93 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 94 DRI_CONF_HYPERZ(false) 95 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 96 DRI_CONF_SECTION_END 97 DRI_CONF_SECTION_QUALITY 98 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 99 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 100 DRI_CONF_NO_NEG_LOD_BIAS(false) 101 DRI_CONF_FORCE_S3TC_ENABLE(false) 102 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 103 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 104 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 105 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 106 DRI_CONF_SECTION_END 107 DRI_CONF_SECTION_DEBUG 108 DRI_CONF_NO_RAST(false) 109 DRI_CONF_SECTION_END 110DRI_CONF_END; 111static const GLuint __driNConfigOptions = 15; 112 113#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 114 115PUBLIC const char __driConfigOptions[] = 116DRI_CONF_BEGIN 117 DRI_CONF_SECTION_PERFORMANCE 118 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 119 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 120 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 121 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 122 DRI_CONF_HYPERZ(false) 123 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 124 DRI_CONF_SECTION_END 125 DRI_CONF_SECTION_QUALITY 126 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 127 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 128 DRI_CONF_NO_NEG_LOD_BIAS(false) 129 DRI_CONF_FORCE_S3TC_ENABLE(false) 130 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 131 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 132 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 133 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 134 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 135 DRI_CONF_SECTION_END 136 DRI_CONF_SECTION_DEBUG 137 DRI_CONF_NO_RAST(false) 138 DRI_CONF_SECTION_END 139 DRI_CONF_SECTION_SOFTWARE 140 DRI_CONF_NV_VERTEX_PROGRAM(false) 141 DRI_CONF_SECTION_END 142DRI_CONF_END; 143static const GLuint __driNConfigOptions = 17; 144 145extern const struct dri_extension blend_extensions[]; 146extern const struct dri_extension ARB_vp_extension[]; 147extern const struct dri_extension NV_vp_extension[]; 148extern const struct dri_extension ATI_fs_extension[]; 149extern const struct dri_extension point_extensions[]; 150 151#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 152 153/* TODO: integrate these into xmlpool.h! */ 154#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 155DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 156 DRI_CONF_DESC(en,"Number of texture image units") \ 157 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 158DRI_CONF_OPT_END 159 160#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 161DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 162 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 163 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 164DRI_CONF_OPT_END 165 166 167 168#define DRI_CONF_DISABLE_S3TC(def) \ 169DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 170 DRI_CONF_DESC(en,"Disable S3TC compression") \ 171DRI_CONF_OPT_END 172 173#define DRI_CONF_DISABLE_FALLBACK(def) \ 174DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 175 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 176DRI_CONF_OPT_END 177 178#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 179DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 180 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 181DRI_CONF_OPT_END 182 183#define DRI_CONF_FP_OPTIMIZATION(def) \ 184DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 185 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 186 DRI_CONF_ENUM(0,"Optimize for Speed") \ 187 DRI_CONF_ENUM(1,"Optimize for Quality") \ 188 DRI_CONF_DESC_END \ 189DRI_CONF_OPT_END 190 191PUBLIC const char __driConfigOptions[] = 192DRI_CONF_BEGIN 193 DRI_CONF_SECTION_PERFORMANCE 194 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 195 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 196 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 197 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 198 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 199 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 200 DRI_CONF_DISABLE_FALLBACK(true) 201 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 202 DRI_CONF_SECTION_END 203 DRI_CONF_SECTION_QUALITY 204 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 205 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 206 DRI_CONF_FORCE_S3TC_ENABLE(false) 207 DRI_CONF_DISABLE_S3TC(false) 208 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 209 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 210 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 211 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 212 DRI_CONF_SECTION_END 213 DRI_CONF_SECTION_DEBUG 214 DRI_CONF_NO_RAST(false) 215 DRI_CONF_SECTION_END 216DRI_CONF_END; 217static const GLuint __driNConfigOptions = 17; 218 219extern const struct dri_extension gl_20_extension[]; 220 221#ifndef RADEON_DEBUG 222 223static const struct dri_debug_control debug_control[] = { 224 {"fall", DEBUG_FALLBACKS}, 225 {"tex", DEBUG_TEXTURE}, 226 {"ioctl", DEBUG_IOCTL}, 227 {"prim", DEBUG_PRIMS}, 228 {"vert", DEBUG_VERTS}, 229 {"state", DEBUG_STATE}, 230 {"code", DEBUG_CODEGEN}, 231 {"vfmt", DEBUG_VFMT}, 232 {"vtxf", DEBUG_VFMT}, 233 {"verb", DEBUG_VERBOSE}, 234 {"dri", DEBUG_DRI}, 235 {"dma", DEBUG_DMA}, 236 {"san", DEBUG_SANITY}, 237 {"sync", DEBUG_SYNC}, 238 {"pix", DEBUG_PIXEL}, 239 {"mem", DEBUG_MEMORY}, 240 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 241 {NULL, 0} 242}; 243#endif /* RADEON_DEBUG */ 244 245#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 246 247extern const struct dri_extension card_extensions[]; 248extern const struct dri_extension mm_extensions[]; 249 250static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 251 252static int 253radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) 254{ 255 int ret; 256 drm_radeon_getparam_t gp; 257 struct drm_radeon_info info; 258 259 if (sPriv->drm_version.major >= 2) { 260 info.value = (uint64_t)value; 261 switch (param) { 262 case RADEON_PARAM_DEVICE_ID: 263 info.request = RADEON_INFO_DEVICE_ID; 264 break; 265 case RADEON_PARAM_NUM_GB_PIPES: 266 info.request = RADEON_INFO_NUM_GB_PIPES; 267 break; 268 default: 269 return -EINVAL; 270 } 271 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 272 } else { 273 gp.param = param; 274 gp.value = value; 275 276 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 277 } 278 return ret; 279} 280 281static const __DRIconfig ** 282radeonFillInModes( __DRIscreenPrivate *psp, 283 unsigned pixel_bits, unsigned depth_bits, 284 unsigned stencil_bits, GLboolean have_back_buffer ) 285{ 286 __DRIconfig **configs; 287 __GLcontextModes *m; 288 unsigned depth_buffer_factor; 289 unsigned back_buffer_factor; 290 GLenum fb_format; 291 GLenum fb_type; 292 int i; 293 294 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 295 * enough to add support. Basically, if a context is created with an 296 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 297 * will never be used. 298 */ 299 static const GLenum back_buffer_modes[] = { 300 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 301 }; 302 303 uint8_t depth_bits_array[2]; 304 uint8_t stencil_bits_array[2]; 305 uint8_t msaa_samples_array[1]; 306 307 depth_bits_array[0] = depth_bits; 308 depth_bits_array[1] = depth_bits; 309 310 /* Just like with the accumulation buffer, always provide some modes 311 * with a stencil buffer. It will be a sw fallback, but some apps won't 312 * care about that. 313 */ 314 stencil_bits_array[0] = 0; 315 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 316 317 msaa_samples_array[0] = 0; 318 319 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 320 back_buffer_factor = (have_back_buffer) ? 2 : 1; 321 322 if ( pixel_bits == 16 ) { 323 fb_format = GL_RGB; 324 fb_type = GL_UNSIGNED_SHORT_5_6_5; 325 } 326 else { 327 fb_format = GL_BGRA; 328 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 329 } 330 331 configs = driCreateConfigs(fb_format, fb_type, 332 depth_bits_array, stencil_bits_array, 333 depth_buffer_factor, 334 back_buffer_modes, back_buffer_factor, 335 msaa_samples_array, 1); 336 if (configs == NULL) { 337 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 338 __func__, __LINE__ ); 339 return NULL; 340 } 341 342 /* Mark the visual as slow if there are "fake" stencil bits. 343 */ 344 for (i = 0; configs[i]; i++) { 345 m = &configs[i]->modes; 346 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 347 m->visualRating = GLX_SLOW_CONFIG; 348 } 349 } 350 351 return (const __DRIconfig **) configs; 352} 353 354#if !RADEON_COMMON 355static const __DRItexOffsetExtension radeonTexOffsetExtension = { 356 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 357 radeonSetTexOffset, 358}; 359 360static const __DRItexBufferExtension radeonTexBufferExtension = { 361 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 362 radeonSetTexBuffer, 363 radeonSetTexBuffer2, 364}; 365#endif 366 367#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 368static const __DRIallocateExtension r200AllocateExtension = { 369 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 370 r200AllocateMemoryMESA, 371 r200FreeMemoryMESA, 372 r200GetMemoryOffsetMESA 373}; 374 375static const __DRItexOffsetExtension r200texOffsetExtension = { 376 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 377 r200SetTexOffset, 378}; 379 380static const __DRItexBufferExtension r200TexBufferExtension = { 381 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 382 r200SetTexBuffer, 383 r200SetTexBuffer2, 384}; 385#endif 386 387#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 388static const __DRItexOffsetExtension r300texOffsetExtension = { 389 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 390 r300SetTexOffset, 391}; 392 393static const __DRItexBufferExtension r300TexBufferExtension = { 394 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 395 r300SetTexBuffer, 396 r300SetTexBuffer2, 397}; 398#endif 399 400#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 401static const __DRItexOffsetExtension r600texOffsetExtension = { 402 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 403 r600SetTexOffset, 404}; 405 406static const __DRItexBufferExtension r600TexBufferExtension = { 407 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 408 r600SetTexBuffer, 409 r600SetTexBuffer2, 410}; 411#endif 412 413static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 414{ 415 screen->chip_flags = 0; 416 switch ( device_id ) { 417 case PCI_CHIP_RADEON_LY: 418 case PCI_CHIP_RADEON_LZ: 419 case PCI_CHIP_RADEON_QY: 420 case PCI_CHIP_RADEON_QZ: 421 case PCI_CHIP_RN50_515E: 422 case PCI_CHIP_RN50_5969: 423 screen->chip_family = CHIP_FAMILY_RV100; 424 break; 425 426 case PCI_CHIP_RS100_4136: 427 case PCI_CHIP_RS100_4336: 428 screen->chip_family = CHIP_FAMILY_RS100; 429 break; 430 431 case PCI_CHIP_RS200_4137: 432 case PCI_CHIP_RS200_4337: 433 case PCI_CHIP_RS250_4237: 434 case PCI_CHIP_RS250_4437: 435 screen->chip_family = CHIP_FAMILY_RS200; 436 break; 437 438 case PCI_CHIP_RADEON_QD: 439 case PCI_CHIP_RADEON_QE: 440 case PCI_CHIP_RADEON_QF: 441 case PCI_CHIP_RADEON_QG: 442 /* all original radeons (7200) presumably have a stencil op bug */ 443 screen->chip_family = CHIP_FAMILY_R100; 444 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 445 break; 446 447 case PCI_CHIP_RV200_QW: 448 case PCI_CHIP_RV200_QX: 449 case PCI_CHIP_RADEON_LW: 450 case PCI_CHIP_RADEON_LX: 451 screen->chip_family = CHIP_FAMILY_RV200; 452 screen->chip_flags = RADEON_CHIPSET_TCL; 453 break; 454 455 case PCI_CHIP_R200_BB: 456 case PCI_CHIP_R200_BC: 457 case PCI_CHIP_R200_QH: 458 case PCI_CHIP_R200_QL: 459 case PCI_CHIP_R200_QM: 460 screen->chip_family = CHIP_FAMILY_R200; 461 screen->chip_flags = RADEON_CHIPSET_TCL; 462 break; 463 464 case PCI_CHIP_RV250_If: 465 case PCI_CHIP_RV250_Ig: 466 case PCI_CHIP_RV250_Ld: 467 case PCI_CHIP_RV250_Lf: 468 case PCI_CHIP_RV250_Lg: 469 screen->chip_family = CHIP_FAMILY_RV250; 470 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 471 break; 472 473 case PCI_CHIP_RV280_5960: 474 case PCI_CHIP_RV280_5961: 475 case PCI_CHIP_RV280_5962: 476 case PCI_CHIP_RV280_5964: 477 case PCI_CHIP_RV280_5965: 478 case PCI_CHIP_RV280_5C61: 479 case PCI_CHIP_RV280_5C63: 480 screen->chip_family = CHIP_FAMILY_RV280; 481 screen->chip_flags = RADEON_CHIPSET_TCL; 482 break; 483 484 case PCI_CHIP_RS300_5834: 485 case PCI_CHIP_RS300_5835: 486 case PCI_CHIP_RS350_7834: 487 case PCI_CHIP_RS350_7835: 488 screen->chip_family = CHIP_FAMILY_RS300; 489 break; 490 491 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 492 case PCI_CHIP_R300_AD: 493 screen->chip_family = CHIP_FAMILY_RV350; 494 screen->chip_flags = RADEON_CHIPSET_TCL; 495 break; 496 case PCI_CHIP_R300_AE: 497 case PCI_CHIP_R300_AF: 498 case PCI_CHIP_R300_AG: 499 case PCI_CHIP_R300_ND: 500 case PCI_CHIP_R300_NE: 501 case PCI_CHIP_R300_NF: 502 case PCI_CHIP_R300_NG: 503 screen->chip_family = CHIP_FAMILY_R300; 504 screen->chip_flags = RADEON_CHIPSET_TCL; 505 break; 506 507 case PCI_CHIP_RV350_AP: 508 case PCI_CHIP_RV350_AQ: 509 case PCI_CHIP_RV350_AR: 510 case PCI_CHIP_RV350_AS: 511 case PCI_CHIP_RV350_AT: 512 case PCI_CHIP_RV350_AV: 513 case PCI_CHIP_RV350_AU: 514 case PCI_CHIP_RV350_NP: 515 case PCI_CHIP_RV350_NQ: 516 case PCI_CHIP_RV350_NR: 517 case PCI_CHIP_RV350_NS: 518 case PCI_CHIP_RV350_NT: 519 case PCI_CHIP_RV350_NV: 520 screen->chip_family = CHIP_FAMILY_RV350; 521 screen->chip_flags = RADEON_CHIPSET_TCL; 522 break; 523 524 case PCI_CHIP_R350_AH: 525 case PCI_CHIP_R350_AI: 526 case PCI_CHIP_R350_AJ: 527 case PCI_CHIP_R350_AK: 528 case PCI_CHIP_R350_NH: 529 case PCI_CHIP_R350_NI: 530 case PCI_CHIP_R360_NJ: 531 case PCI_CHIP_R350_NK: 532 screen->chip_family = CHIP_FAMILY_R350; 533 screen->chip_flags = RADEON_CHIPSET_TCL; 534 break; 535 536 case PCI_CHIP_RV370_5460: 537 case PCI_CHIP_RV370_5462: 538 case PCI_CHIP_RV370_5464: 539 case PCI_CHIP_RV370_5B60: 540 case PCI_CHIP_RV370_5B62: 541 case PCI_CHIP_RV370_5B63: 542 case PCI_CHIP_RV370_5B64: 543 case PCI_CHIP_RV370_5B65: 544 case PCI_CHIP_RV380_3150: 545 case PCI_CHIP_RV380_3152: 546 case PCI_CHIP_RV380_3154: 547 case PCI_CHIP_RV380_3E50: 548 case PCI_CHIP_RV380_3E54: 549 screen->chip_family = CHIP_FAMILY_RV380; 550 screen->chip_flags = RADEON_CHIPSET_TCL; 551 break; 552 553 case PCI_CHIP_R420_JN: 554 case PCI_CHIP_R420_JH: 555 case PCI_CHIP_R420_JI: 556 case PCI_CHIP_R420_JJ: 557 case PCI_CHIP_R420_JK: 558 case PCI_CHIP_R420_JL: 559 case PCI_CHIP_R420_JM: 560 case PCI_CHIP_R420_JO: 561 case PCI_CHIP_R420_JP: 562 case PCI_CHIP_R420_JT: 563 case PCI_CHIP_R481_4B49: 564 case PCI_CHIP_R481_4B4A: 565 case PCI_CHIP_R481_4B4B: 566 case PCI_CHIP_R481_4B4C: 567 case PCI_CHIP_R423_UH: 568 case PCI_CHIP_R423_UI: 569 case PCI_CHIP_R423_UJ: 570 case PCI_CHIP_R423_UK: 571 case PCI_CHIP_R430_554C: 572 case PCI_CHIP_R430_554D: 573 case PCI_CHIP_R430_554E: 574 case PCI_CHIP_R430_554F: 575 case PCI_CHIP_R423_5550: 576 case PCI_CHIP_R423_UQ: 577 case PCI_CHIP_R423_UR: 578 case PCI_CHIP_R423_UT: 579 case PCI_CHIP_R430_5D48: 580 case PCI_CHIP_R430_5D49: 581 case PCI_CHIP_R430_5D4A: 582 case PCI_CHIP_R480_5D4C: 583 case PCI_CHIP_R480_5D4D: 584 case PCI_CHIP_R480_5D4E: 585 case PCI_CHIP_R480_5D4F: 586 case PCI_CHIP_R480_5D50: 587 case PCI_CHIP_R480_5D52: 588 case PCI_CHIP_R423_5D57: 589 screen->chip_family = CHIP_FAMILY_R420; 590 screen->chip_flags = RADEON_CHIPSET_TCL; 591 break; 592 593 case PCI_CHIP_RV410_5E4C: 594 case PCI_CHIP_RV410_5E4F: 595 case PCI_CHIP_RV410_564A: 596 case PCI_CHIP_RV410_564B: 597 case PCI_CHIP_RV410_564F: 598 case PCI_CHIP_RV410_5652: 599 case PCI_CHIP_RV410_5653: 600 case PCI_CHIP_RV410_5657: 601 case PCI_CHIP_RV410_5E48: 602 case PCI_CHIP_RV410_5E4A: 603 case PCI_CHIP_RV410_5E4B: 604 case PCI_CHIP_RV410_5E4D: 605 screen->chip_family = CHIP_FAMILY_RV410; 606 screen->chip_flags = RADEON_CHIPSET_TCL; 607 break; 608 609 case PCI_CHIP_RS480_5954: 610 case PCI_CHIP_RS480_5955: 611 case PCI_CHIP_RS482_5974: 612 case PCI_CHIP_RS482_5975: 613 case PCI_CHIP_RS400_5A41: 614 case PCI_CHIP_RS400_5A42: 615 case PCI_CHIP_RC410_5A61: 616 case PCI_CHIP_RC410_5A62: 617 screen->chip_family = CHIP_FAMILY_RS400; 618 break; 619 620 case PCI_CHIP_RS600_793F: 621 case PCI_CHIP_RS600_7941: 622 case PCI_CHIP_RS600_7942: 623 screen->chip_family = CHIP_FAMILY_RS600; 624 break; 625 626 case PCI_CHIP_RS690_791E: 627 case PCI_CHIP_RS690_791F: 628 screen->chip_family = CHIP_FAMILY_RS690; 629 break; 630 case PCI_CHIP_RS740_796C: 631 case PCI_CHIP_RS740_796D: 632 case PCI_CHIP_RS740_796E: 633 case PCI_CHIP_RS740_796F: 634 screen->chip_family = CHIP_FAMILY_RS740; 635 break; 636 637 case PCI_CHIP_R520_7100: 638 case PCI_CHIP_R520_7101: 639 case PCI_CHIP_R520_7102: 640 case PCI_CHIP_R520_7103: 641 case PCI_CHIP_R520_7104: 642 case PCI_CHIP_R520_7105: 643 case PCI_CHIP_R520_7106: 644 case PCI_CHIP_R520_7108: 645 case PCI_CHIP_R520_7109: 646 case PCI_CHIP_R520_710A: 647 case PCI_CHIP_R520_710B: 648 case PCI_CHIP_R520_710C: 649 case PCI_CHIP_R520_710E: 650 case PCI_CHIP_R520_710F: 651 screen->chip_family = CHIP_FAMILY_R520; 652 screen->chip_flags = RADEON_CHIPSET_TCL; 653 break; 654 655 case PCI_CHIP_RV515_7140: 656 case PCI_CHIP_RV515_7141: 657 case PCI_CHIP_RV515_7142: 658 case PCI_CHIP_RV515_7143: 659 case PCI_CHIP_RV515_7144: 660 case PCI_CHIP_RV515_7145: 661 case PCI_CHIP_RV515_7146: 662 case PCI_CHIP_RV515_7147: 663 case PCI_CHIP_RV515_7149: 664 case PCI_CHIP_RV515_714A: 665 case PCI_CHIP_RV515_714B: 666 case PCI_CHIP_RV515_714C: 667 case PCI_CHIP_RV515_714D: 668 case PCI_CHIP_RV515_714E: 669 case PCI_CHIP_RV515_714F: 670 case PCI_CHIP_RV515_7151: 671 case PCI_CHIP_RV515_7152: 672 case PCI_CHIP_RV515_7153: 673 case PCI_CHIP_RV515_715E: 674 case PCI_CHIP_RV515_715F: 675 case PCI_CHIP_RV515_7180: 676 case PCI_CHIP_RV515_7181: 677 case PCI_CHIP_RV515_7183: 678 case PCI_CHIP_RV515_7186: 679 case PCI_CHIP_RV515_7187: 680 case PCI_CHIP_RV515_7188: 681 case PCI_CHIP_RV515_718A: 682 case PCI_CHIP_RV515_718B: 683 case PCI_CHIP_RV515_718C: 684 case PCI_CHIP_RV515_718D: 685 case PCI_CHIP_RV515_718F: 686 case PCI_CHIP_RV515_7193: 687 case PCI_CHIP_RV515_7196: 688 case PCI_CHIP_RV515_719B: 689 case PCI_CHIP_RV515_719F: 690 case PCI_CHIP_RV515_7200: 691 case PCI_CHIP_RV515_7210: 692 case PCI_CHIP_RV515_7211: 693 screen->chip_family = CHIP_FAMILY_RV515; 694 screen->chip_flags = RADEON_CHIPSET_TCL; 695 break; 696 697 case PCI_CHIP_RV530_71C0: 698 case PCI_CHIP_RV530_71C1: 699 case PCI_CHIP_RV530_71C2: 700 case PCI_CHIP_RV530_71C3: 701 case PCI_CHIP_RV530_71C4: 702 case PCI_CHIP_RV530_71C5: 703 case PCI_CHIP_RV530_71C6: 704 case PCI_CHIP_RV530_71C7: 705 case PCI_CHIP_RV530_71CD: 706 case PCI_CHIP_RV530_71CE: 707 case PCI_CHIP_RV530_71D2: 708 case PCI_CHIP_RV530_71D4: 709 case PCI_CHIP_RV530_71D5: 710 case PCI_CHIP_RV530_71D6: 711 case PCI_CHIP_RV530_71DA: 712 case PCI_CHIP_RV530_71DE: 713 screen->chip_family = CHIP_FAMILY_RV530; 714 screen->chip_flags = RADEON_CHIPSET_TCL; 715 break; 716 717 case PCI_CHIP_R580_7240: 718 case PCI_CHIP_R580_7243: 719 case PCI_CHIP_R580_7244: 720 case PCI_CHIP_R580_7245: 721 case PCI_CHIP_R580_7246: 722 case PCI_CHIP_R580_7247: 723 case PCI_CHIP_R580_7248: 724 case PCI_CHIP_R580_7249: 725 case PCI_CHIP_R580_724A: 726 case PCI_CHIP_R580_724B: 727 case PCI_CHIP_R580_724C: 728 case PCI_CHIP_R580_724D: 729 case PCI_CHIP_R580_724E: 730 case PCI_CHIP_R580_724F: 731 case PCI_CHIP_R580_7284: 732 screen->chip_family = CHIP_FAMILY_R580; 733 screen->chip_flags = RADEON_CHIPSET_TCL; 734 break; 735 736 case PCI_CHIP_RV570_7280: 737 case PCI_CHIP_RV560_7281: 738 case PCI_CHIP_RV560_7283: 739 case PCI_CHIP_RV560_7287: 740 case PCI_CHIP_RV570_7288: 741 case PCI_CHIP_RV570_7289: 742 case PCI_CHIP_RV570_728B: 743 case PCI_CHIP_RV570_728C: 744 case PCI_CHIP_RV560_7290: 745 case PCI_CHIP_RV560_7291: 746 case PCI_CHIP_RV560_7293: 747 case PCI_CHIP_RV560_7297: 748 screen->chip_family = CHIP_FAMILY_RV560; 749 screen->chip_flags = RADEON_CHIPSET_TCL; 750 break; 751 752 case PCI_CHIP_R600_9400: 753 case PCI_CHIP_R600_9401: 754 case PCI_CHIP_R600_9402: 755 case PCI_CHIP_R600_9403: 756 case PCI_CHIP_R600_9405: 757 case PCI_CHIP_R600_940A: 758 case PCI_CHIP_R600_940B: 759 case PCI_CHIP_R600_940F: 760 screen->chip_family = CHIP_FAMILY_R600; 761 screen->chip_flags = RADEON_CHIPSET_TCL; 762 break; 763 764 case PCI_CHIP_RV610_94C0: 765 case PCI_CHIP_RV610_94C1: 766 case PCI_CHIP_RV610_94C3: 767 case PCI_CHIP_RV610_94C4: 768 case PCI_CHIP_RV610_94C5: 769 case PCI_CHIP_RV610_94C6: 770 case PCI_CHIP_RV610_94C7: 771 case PCI_CHIP_RV610_94C8: 772 case PCI_CHIP_RV610_94C9: 773 case PCI_CHIP_RV610_94CB: 774 case PCI_CHIP_RV610_94CC: 775 case PCI_CHIP_RV610_94CD: 776 screen->chip_family = CHIP_FAMILY_RV610; 777 screen->chip_flags = RADEON_CHIPSET_TCL; 778 break; 779 780 case PCI_CHIP_RV630_9580: 781 case PCI_CHIP_RV630_9581: 782 case PCI_CHIP_RV630_9583: 783 case PCI_CHIP_RV630_9586: 784 case PCI_CHIP_RV630_9587: 785 case PCI_CHIP_RV630_9588: 786 case PCI_CHIP_RV630_9589: 787 case PCI_CHIP_RV630_958A: 788 case PCI_CHIP_RV630_958B: 789 case PCI_CHIP_RV630_958C: 790 case PCI_CHIP_RV630_958D: 791 case PCI_CHIP_RV630_958E: 792 case PCI_CHIP_RV630_958F: 793 screen->chip_family = CHIP_FAMILY_RV630; 794 screen->chip_flags = RADEON_CHIPSET_TCL; 795 break; 796 797 case PCI_CHIP_RV670_9500: 798 case PCI_CHIP_RV670_9501: 799 case PCI_CHIP_RV670_9504: 800 case PCI_CHIP_RV670_9505: 801 case PCI_CHIP_RV670_9506: 802 case PCI_CHIP_RV670_9507: 803 case PCI_CHIP_RV670_9508: 804 case PCI_CHIP_RV670_9509: 805 case PCI_CHIP_RV670_950F: 806 case PCI_CHIP_RV670_9511: 807 case PCI_CHIP_RV670_9515: 808 case PCI_CHIP_RV670_9517: 809 case PCI_CHIP_RV670_9519: 810 screen->chip_family = CHIP_FAMILY_RV670; 811 screen->chip_flags = RADEON_CHIPSET_TCL; 812 break; 813 814 case PCI_CHIP_RV620_95C0: 815 case PCI_CHIP_RV620_95C2: 816 case PCI_CHIP_RV620_95C4: 817 case PCI_CHIP_RV620_95C5: 818 case PCI_CHIP_RV620_95C6: 819 case PCI_CHIP_RV620_95C7: 820 case PCI_CHIP_RV620_95C9: 821 case PCI_CHIP_RV620_95CC: 822 case PCI_CHIP_RV620_95CD: 823 case PCI_CHIP_RV620_95CE: 824 case PCI_CHIP_RV620_95CF: 825 screen->chip_family = CHIP_FAMILY_RV620; 826 screen->chip_flags = RADEON_CHIPSET_TCL; 827 break; 828 829 case PCI_CHIP_RV635_9590: 830 case PCI_CHIP_RV635_9591: 831 case PCI_CHIP_RV635_9593: 832 case PCI_CHIP_RV635_9595: 833 case PCI_CHIP_RV635_9596: 834 case PCI_CHIP_RV635_9597: 835 case PCI_CHIP_RV635_9598: 836 case PCI_CHIP_RV635_9599: 837 case PCI_CHIP_RV635_959B: 838 screen->chip_family = CHIP_FAMILY_RV635; 839 screen->chip_flags = RADEON_CHIPSET_TCL; 840 break; 841 842 case PCI_CHIP_RS780_9611: 843 case PCI_CHIP_RS780_9612: 844 case PCI_CHIP_RS780_9613: 845 case PCI_CHIP_RS780_9614: 846 case PCI_CHIP_RS780_9615: 847 case PCI_CHIP_RS780_9616: 848 screen->chip_family = CHIP_FAMILY_RS780; 849 screen->chip_flags = RADEON_CHIPSET_TCL; 850 break; 851 852 case PCI_CHIP_RV770_9440: 853 case PCI_CHIP_RV770_9441: 854 case PCI_CHIP_RV770_9442: 855 case PCI_CHIP_RV770_9444: 856 case PCI_CHIP_RV770_9446: 857 case PCI_CHIP_RV770_944A: 858 case PCI_CHIP_RV770_944B: 859 case PCI_CHIP_RV770_944C: 860 case PCI_CHIP_RV770_944E: 861 case PCI_CHIP_RV770_9450: 862 case PCI_CHIP_RV770_9452: 863 case PCI_CHIP_RV770_9456: 864 case PCI_CHIP_RV770_945A: 865 case PCI_CHIP_RV770_945B: 866 case PCI_CHIP_RV790_9460: 867 case PCI_CHIP_RV790_9462: 868 case PCI_CHIP_RV770_946A: 869 case PCI_CHIP_RV770_946B: 870 case PCI_CHIP_RV770_947A: 871 case PCI_CHIP_RV770_947B: 872 screen->chip_family = CHIP_FAMILY_RV770; 873 screen->chip_flags = RADEON_CHIPSET_TCL; 874 break; 875 876 case PCI_CHIP_RV730_9487: 877 case PCI_CHIP_RV730_9489: 878 case PCI_CHIP_RV730_948F: 879 case PCI_CHIP_RV730_9490: 880 case PCI_CHIP_RV730_9491: 881 case PCI_CHIP_RV730_9498: 882 case PCI_CHIP_RV730_949C: 883 case PCI_CHIP_RV730_949E: 884 case PCI_CHIP_RV730_949F: 885 screen->chip_family = CHIP_FAMILY_RV730; 886 screen->chip_flags = RADEON_CHIPSET_TCL; 887 break; 888 889 case PCI_CHIP_RV710_9540: 890 case PCI_CHIP_RV710_9541: 891 case PCI_CHIP_RV710_9542: 892 case PCI_CHIP_RV710_954E: 893 case PCI_CHIP_RV710_954F: 894 case PCI_CHIP_RV710_9552: 895 case PCI_CHIP_RV710_9553: 896 case PCI_CHIP_RV710_9555: 897 screen->chip_family = CHIP_FAMILY_RV710; 898 screen->chip_flags = RADEON_CHIPSET_TCL; 899 break; 900 901 default: 902 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 903 device_id); 904 return -1; 905 } 906 907 return 0; 908} 909 910 911/* Create the device specific screen private data struct. 912 */ 913static radeonScreenPtr 914radeonCreateScreen( __DRIscreenPrivate *sPriv ) 915{ 916 radeonScreenPtr screen; 917 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 918 unsigned char *RADEONMMIO = NULL; 919 int i; 920 int ret; 921 uint32_t temp = 0; 922 923 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 924 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 925 return GL_FALSE; 926 } 927 928 /* Allocate the private area */ 929 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 930 if ( !screen ) { 931 __driUtilMessage("%s: Could not allocate memory for screen structure", 932 __FUNCTION__); 933 return NULL; 934 } 935 936#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 937 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 938#endif 939 940 /* parse information in __driConfigOptions */ 941 driParseOptionInfo (&screen->optionCache, 942 __driConfigOptions, __driNConfigOptions); 943 944 /* This is first since which regions we map depends on whether or 945 * not we are using a PCI card. 946 */ 947 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 948 { 949 int ret; 950 951#ifdef RADEON_PARAM_KERNEL_MM 952 ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm); 953 954 if (ret && ret != -EINVAL) { 955 FREE( screen ); 956 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 957 return NULL; 958 } 959 960 if (ret == -EINVAL) 961 screen->kernel_mm = 0; 962#endif 963 964 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 965 &screen->gart_buffer_offset); 966 967 if (ret) { 968 FREE( screen ); 969 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 970 return NULL; 971 } 972 973 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 974 &screen->gart_base); 975 if (ret) { 976 FREE( screen ); 977 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 978 return NULL; 979 } 980 981 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 982 &screen->irq); 983 if (ret) { 984 FREE( screen ); 985 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 986 return NULL; 987 } 988 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 989 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 990 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 991 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 992 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 993 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 994 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 995 } 996 997 if (!screen->kernel_mm) { 998 screen->mmio.handle = dri_priv->registerHandle; 999 screen->mmio.size = dri_priv->registerSize; 1000 if ( drmMap( sPriv->fd, 1001 screen->mmio.handle, 1002 screen->mmio.size, 1003 &screen->mmio.map ) ) { 1004 FREE( screen ); 1005 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1006 return NULL; 1007 } 1008 1009 RADEONMMIO = screen->mmio.map; 1010 1011 screen->status.handle = dri_priv->statusHandle; 1012 screen->status.size = dri_priv->statusSize; 1013 if ( drmMap( sPriv->fd, 1014 screen->status.handle, 1015 screen->status.size, 1016 &screen->status.map ) ) { 1017 drmUnmap( screen->mmio.map, screen->mmio.size ); 1018 FREE( screen ); 1019 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1020 return NULL; 1021 } 1022 screen->scratch = (__volatile__ uint32_t *) 1023 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1024 1025 screen->buffers = drmMapBufs( sPriv->fd ); 1026 if ( !screen->buffers ) { 1027 drmUnmap( screen->status.map, screen->status.size ); 1028 drmUnmap( screen->mmio.map, screen->mmio.size ); 1029 FREE( screen ); 1030 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1031 return NULL; 1032 } 1033 1034 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1035 screen->gartTextures.handle = dri_priv->gartTexHandle; 1036 screen->gartTextures.size = dri_priv->gartTexMapSize; 1037 if ( drmMap( sPriv->fd, 1038 screen->gartTextures.handle, 1039 screen->gartTextures.size, 1040 (drmAddressPtr)&screen->gartTextures.map ) ) { 1041 drmUnmapBufs( screen->buffers ); 1042 drmUnmap( screen->status.map, screen->status.size ); 1043 drmUnmap( screen->mmio.map, screen->mmio.size ); 1044 FREE( screen ); 1045 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1046 return NULL; 1047 } 1048 1049 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1050 } 1051 } 1052 1053 1054 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 1055 if (ret == -1) 1056 return NULL; 1057 1058 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1059 sPriv->ddx_version.minor < 2) { 1060 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1061 return NULL; 1062 } 1063 1064 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1065 fprintf(stderr, "R500 support requires a newer drm.\n"); 1066 return NULL; 1067 } 1068 1069 if (getenv("R300_NO_TCL")) 1070 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1071 1072 if (screen->chip_family <= CHIP_FAMILY_RS200) 1073 screen->chip_flags |= RADEON_CLASS_R100; 1074 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1075 screen->chip_flags |= RADEON_CLASS_R200; 1076 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1077 screen->chip_flags |= RADEON_CLASS_R300; 1078 else 1079 screen->chip_flags |= RADEON_CLASS_R600; 1080 1081 screen->cpp = dri_priv->bpp / 8; 1082 screen->AGPMode = dri_priv->AGPMode; 1083 1084 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1085 if (ret) { 1086 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1087 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1088 else { 1089 FREE( screen ); 1090 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1091 return NULL; 1092 } 1093 } else { 1094 screen->fbLocation = (temp & 0xffff) << 16; 1095 } 1096 1097 if (IS_R300_CLASS(screen)) { 1098 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1099 if (ret) { 1100 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1101 switch (screen->chip_family) { 1102 case CHIP_FAMILY_R300: 1103 case CHIP_FAMILY_R350: 1104 screen->num_gb_pipes = 2; 1105 break; 1106 case CHIP_FAMILY_R420: 1107 case CHIP_FAMILY_R520: 1108 case CHIP_FAMILY_R580: 1109 case CHIP_FAMILY_RV560: 1110 case CHIP_FAMILY_RV570: 1111 screen->num_gb_pipes = 4; 1112 break; 1113 case CHIP_FAMILY_RV350: 1114 case CHIP_FAMILY_RV515: 1115 case CHIP_FAMILY_RV530: 1116 case CHIP_FAMILY_RV410: 1117 default: 1118 screen->num_gb_pipes = 1; 1119 break; 1120 } 1121 } else { 1122 screen->num_gb_pipes = temp; 1123 } 1124 } 1125 1126 if ( sPriv->drm_version.minor >= 10 ) { 1127 drm_radeon_setparam_t sp; 1128 1129 sp.param = RADEON_SETPARAM_FB_LOCATION; 1130 sp.value = screen->fbLocation; 1131 1132 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1133 &sp, sizeof( sp ) ); 1134 } 1135 1136 screen->frontOffset = dri_priv->frontOffset; 1137 screen->frontPitch = dri_priv->frontPitch; 1138 screen->backOffset = dri_priv->backOffset; 1139 screen->backPitch = dri_priv->backPitch; 1140 screen->depthOffset = dri_priv->depthOffset; 1141 screen->depthPitch = dri_priv->depthPitch; 1142 1143 /* Check if ddx has set up a surface reg to cover depth buffer */ 1144 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1145 /* these chips don't use tiled z without hyperz. So always pretend 1146 we have set up a surface which will cause linear reads/writes */ 1147 (IS_R100_CLASS(screen) && 1148 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1149 1150 if ( dri_priv->textureSize == 0 ) { 1151 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1152 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1153 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1154 dri_priv->log2GARTTexGran; 1155 } else { 1156 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1157 + screen->fbLocation; 1158 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1159 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1160 dri_priv->log2TexGran; 1161 } 1162 1163 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1164 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1165 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1166 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1167 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1168 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1169 } else { 1170 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1171 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1172 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1173 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1174 dri_priv->log2GARTTexGran; 1175 } 1176 1177 i = 0; 1178 screen->extensions[i++] = &driCopySubBufferExtension.base; 1179 screen->extensions[i++] = &driFrameTrackingExtension.base; 1180 screen->extensions[i++] = &driReadDrawableExtension; 1181 1182 if ( screen->irq != 0 ) { 1183 screen->extensions[i++] = &driSwapControlExtension.base; 1184 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1185 } 1186 1187 if (!screen->kernel_mm) { 1188#if !RADEON_COMMON 1189 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1190#endif 1191 1192#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1193 if (IS_R200_CLASS(screen)) 1194 screen->extensions[i++] = &r200AllocateExtension.base; 1195 1196 screen->extensions[i++] = &r200texOffsetExtension.base; 1197#endif 1198 1199#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1200 screen->extensions[i++] = &r300texOffsetExtension.base; 1201#endif 1202 1203#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1204 screen->extensions[i++] = &r600texOffsetExtension.base; 1205#endif 1206 } 1207 1208 screen->extensions[i++] = NULL; 1209 sPriv->extensions = screen->extensions; 1210 1211 screen->driScreen = sPriv; 1212 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1213 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1214 screen->sarea_priv_offset); 1215 1216 if (screen->kernel_mm) 1217 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1218 else 1219 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1220 if (screen->bom == NULL) { 1221 free(screen); 1222 return NULL; 1223 } 1224 1225 return screen; 1226} 1227 1228static radeonScreenPtr 1229radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1230{ 1231 radeonScreenPtr screen; 1232 int i; 1233 int ret; 1234 uint32_t device_id; 1235 uint32_t temp = 0; 1236 1237 /* Allocate the private area */ 1238 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1239 if ( !screen ) { 1240 __driUtilMessage("%s: Could not allocate memory for screen structure", 1241 __FUNCTION__); 1242 fprintf(stderr, "leaving here\n"); 1243 return NULL; 1244 } 1245 1246#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1247 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1248#endif 1249 1250 /* parse information in __driConfigOptions */ 1251 driParseOptionInfo (&screen->optionCache, 1252 __driConfigOptions, __driNConfigOptions); 1253 1254 screen->kernel_mm = 1; 1255 screen->chip_flags = 0; 1256 1257 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); 1258 1259 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1260 if (ret) { 1261 FREE( screen ); 1262 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1263 return NULL; 1264 } 1265 1266 ret = radeon_set_screen_flags(screen, device_id); 1267 if (ret == -1) 1268 return NULL; 1269 1270 if (getenv("R300_NO_TCL")) 1271 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1272 1273 if (screen->chip_family <= CHIP_FAMILY_RS200) 1274 screen->chip_flags |= RADEON_CLASS_R100; 1275 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1276 screen->chip_flags |= RADEON_CLASS_R200; 1277 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1278 screen->chip_flags |= RADEON_CLASS_R300; 1279 else 1280 screen->chip_flags |= RADEON_CLASS_R600; 1281 1282 if (IS_R300_CLASS(screen)) { 1283 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1284 if (ret) { 1285 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1286 switch (screen->chip_family) { 1287 case CHIP_FAMILY_R300: 1288 case CHIP_FAMILY_R350: 1289 screen->num_gb_pipes = 2; 1290 break; 1291 case CHIP_FAMILY_R420: 1292 case CHIP_FAMILY_R520: 1293 case CHIP_FAMILY_R580: 1294 case CHIP_FAMILY_RV560: 1295 case CHIP_FAMILY_RV570: 1296 screen->num_gb_pipes = 4; 1297 break; 1298 case CHIP_FAMILY_RV350: 1299 case CHIP_FAMILY_RV515: 1300 case CHIP_FAMILY_RV530: 1301 case CHIP_FAMILY_RV410: 1302 default: 1303 screen->num_gb_pipes = 1; 1304 break; 1305 } 1306 } else { 1307 screen->num_gb_pipes = temp; 1308 } 1309 } 1310 1311 i = 0; 1312 screen->extensions[i++] = &driCopySubBufferExtension.base; 1313 screen->extensions[i++] = &driFrameTrackingExtension.base; 1314 screen->extensions[i++] = &driReadDrawableExtension; 1315 1316 if ( screen->irq != 0 ) { 1317 screen->extensions[i++] = &driSwapControlExtension.base; 1318 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1319 } 1320 1321#if !RADEON_COMMON 1322 screen->extensions[i++] = &radeonTexBufferExtension.base; 1323#endif 1324 1325#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1326 if (IS_R200_CLASS(screen)) 1327 screen->extensions[i++] = &r200AllocateExtension.base; 1328 1329 screen->extensions[i++] = &r200TexBufferExtension.base; 1330#endif 1331 1332#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1333 screen->extensions[i++] = &r300TexBufferExtension.base; 1334#endif 1335 1336#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1337 screen->extensions[i++] = &r600TexBufferExtension.base; 1338#endif 1339 1340 screen->extensions[i++] = NULL; 1341 sPriv->extensions = screen->extensions; 1342 1343 screen->driScreen = sPriv; 1344 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1345 if (screen->bom == NULL) { 1346 free(screen); 1347 return NULL; 1348 } 1349 return screen; 1350} 1351 1352/* Destroy the device specific screen private data struct. 1353 */ 1354static void 1355radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1356{ 1357 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1358 1359 if (!screen) 1360 return; 1361 1362 if (screen->kernel_mm) { 1363#ifdef RADEON_BO_TRACK 1364 radeon_tracker_print(&screen->bom->tracker, stderr); 1365#endif 1366 radeon_bo_manager_gem_dtor(screen->bom); 1367 } else { 1368 radeon_bo_manager_legacy_dtor(screen->bom); 1369 1370 if ( screen->gartTextures.map ) { 1371 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1372 } 1373 drmUnmapBufs( screen->buffers ); 1374 drmUnmap( screen->status.map, screen->status.size ); 1375 drmUnmap( screen->mmio.map, screen->mmio.size ); 1376 } 1377 1378 /* free all option information */ 1379 driDestroyOptionInfo (&screen->optionCache); 1380 1381 FREE( screen ); 1382 sPriv->private = NULL; 1383} 1384 1385 1386/* Initialize the driver specific screen private data. 1387 */ 1388static GLboolean 1389radeonInitDriver( __DRIscreenPrivate *sPriv ) 1390{ 1391 if (sPriv->dri2.enabled) { 1392 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1393 } else { 1394 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1395 } 1396 if ( !sPriv->private ) { 1397 radeonDestroyScreen( sPriv ); 1398 return GL_FALSE; 1399 } 1400 1401 return GL_TRUE; 1402} 1403 1404 1405 1406/** 1407 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1408 * 1409 * \todo This function (and its interface) will need to be updated to support 1410 * pbuffers. 1411 */ 1412static GLboolean 1413radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1414 __DRIdrawablePrivate *driDrawPriv, 1415 const __GLcontextModes *mesaVis, 1416 GLboolean isPixmap ) 1417{ 1418 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1419 1420 const GLboolean swDepth = GL_FALSE; 1421 const GLboolean swAlpha = GL_FALSE; 1422 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1423 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1424 mesaVis->depthBits != 24; 1425 GLenum rgbFormat; 1426 struct radeon_framebuffer *rfb; 1427 1428 if (isPixmap) 1429 return GL_FALSE; /* not implemented */ 1430 1431 rfb = CALLOC_STRUCT(radeon_framebuffer); 1432 if (!rfb) 1433 return GL_FALSE; 1434 1435 _mesa_initialize_framebuffer(&rfb->base, mesaVis); 1436 1437 if (mesaVis->redBits == 5) 1438 rgbFormat = GL_RGB5; 1439 else if (mesaVis->alphaBits == 0) 1440 rgbFormat = GL_RGB8; 1441 else 1442 rgbFormat = GL_RGBA8; 1443 1444 /* front color renderbuffer */ 1445 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1446 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1447 rfb->color_rb[0]->has_surface = 1; 1448 1449 /* back color renderbuffer */ 1450 if (mesaVis->doubleBufferMode) { 1451 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1452 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1453 rfb->color_rb[1]->has_surface = 1; 1454 } 1455 1456 if (mesaVis->depthBits == 24) { 1457 if (mesaVis->stencilBits == 8) { 1458 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); 1459 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1460 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1461 depthStencilRb->has_surface = screen->depthHasSurface; 1462 } else { 1463 /* depth renderbuffer */ 1464 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); 1465 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1466 depth->has_surface = screen->depthHasSurface; 1467 } 1468 } else if (mesaVis->depthBits == 16) { 1469 /* just 16-bit depth buffer, no hw stencil */ 1470 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); 1471 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1472 depth->has_surface = screen->depthHasSurface; 1473 } 1474 1475 _mesa_add_soft_renderbuffers(&rfb->base, 1476 GL_FALSE, /* color */ 1477 swDepth, 1478 swStencil, 1479 swAccum, 1480 swAlpha, 1481 GL_FALSE /* aux */); 1482 driDrawPriv->driverPrivate = (void *) rfb; 1483 1484 return (driDrawPriv->driverPrivate != NULL); 1485} 1486 1487 1488static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1489{ 1490 struct radeon_renderbuffer *rb; 1491 1492 rb = rfb->color_rb[0]; 1493 if (rb && rb->bo) { 1494 radeon_bo_unref(rb->bo); 1495 rb->bo = NULL; 1496 } 1497 rb = rfb->color_rb[1]; 1498 if (rb && rb->bo) { 1499 radeon_bo_unref(rb->bo); 1500 rb->bo = NULL; 1501 } 1502 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1503 if (rb && rb->bo) { 1504 radeon_bo_unref(rb->bo); 1505 rb->bo = NULL; 1506 } 1507} 1508 1509void 1510radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1511{ 1512 struct radeon_framebuffer *rfb; 1513 if (!driDrawPriv) 1514 return; 1515 1516 rfb = (void*)driDrawPriv->driverPrivate; 1517 if (!rfb) 1518 return; 1519 radeon_cleanup_renderbuffers(rfb); 1520 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1521} 1522 1523/** 1524 * Choose the appropriate CreateContext function based on the chipset. 1525 * Eventually, all drivers will go through this process. 1526 */ 1527static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1528 __DRIcontextPrivate * driContextPriv, 1529 void *sharedContextPriv) 1530{ 1531 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1532 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1533#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1534 if (IS_R600_CLASS(screen)) 1535 return r600CreateContext(glVisual, driContextPriv, sharedContextPriv); 1536#endif 1537 1538#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1539 if (IS_R300_CLASS(screen)) 1540 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1541#endif 1542 1543#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1544 if (IS_R200_CLASS(screen)) 1545 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); 1546#endif 1547 1548#if !RADEON_COMMON 1549 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); 1550#endif 1551 return GL_FALSE; 1552} 1553 1554 1555/** 1556 * This is the driver specific part of the createNewScreen entry point. 1557 * 1558 * \todo maybe fold this into intelInitDriver 1559 * 1560 * \return the __GLcontextModes supported by this driver 1561 */ 1562static const __DRIconfig ** 1563radeonInitScreen(__DRIscreenPrivate *psp) 1564{ 1565#if !RADEON_COMMON 1566 static const char *driver_name = "Radeon"; 1567 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1568 static const __DRIversion dri_expected = { 4, 0, 0 }; 1569 static const __DRIversion drm_expected = { 1, 6, 0 }; 1570#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1571 static const char *driver_name = "R200"; 1572 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1573 static const __DRIversion dri_expected = { 4, 0, 0 }; 1574 static const __DRIversion drm_expected = { 1, 6, 0 }; 1575#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1576 static const char *driver_name = "R300"; 1577 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1578 static const __DRIversion dri_expected = { 4, 0, 0 }; 1579 static const __DRIversion drm_expected = { 1, 24, 0 }; 1580#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1581 static const char *driver_name = "R600"; 1582 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1583 static const __DRIversion dri_expected = { 4, 0, 0 }; 1584 static const __DRIversion drm_expected = { 1, 24, 0 }; 1585#endif 1586 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1587 1588 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1589 &psp->dri_version, & dri_expected, 1590 &psp->ddx_version, & ddx_expected, 1591 &psp->drm_version, & drm_expected ) ) { 1592 return NULL; 1593 } 1594 1595 /* Calling driInitExtensions here, with a NULL context pointer, 1596 * does not actually enable the extensions. It just makes sure 1597 * that all the dispatch offsets for all the extensions that 1598 * *might* be enables are known. This is needed because the 1599 * dispatch offsets need to be known when _mesa_context_create 1600 * is called, but we can't enable the extensions until we have a 1601 * context pointer. 1602 * 1603 * Hello chicken. Hello egg. How are you two today? 1604 */ 1605 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1606#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1607 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1608 driInitSingleExtension( NULL, ARB_vp_extension ); 1609 driInitSingleExtension( NULL, NV_vp_extension ); 1610 driInitSingleExtension( NULL, ATI_fs_extension ); 1611 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1612#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 1613 driInitSingleExtension( NULL, gl_20_extension ); 1614#endif 1615 1616 if (!radeonInitDriver(psp)) 1617 return NULL; 1618 1619 /* for now fill in all modes */ 1620 return radeonFillInModes( psp, 1621 dri_priv->bpp, 1622 (dri_priv->bpp == 16) ? 16 : 24, 1623 (dri_priv->bpp == 16) ? 0 : 8, 1); 1624} 1625#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1626 1627/** 1628 * This is the driver specific part of the createNewScreen entry point. 1629 * Called when using DRI2. 1630 * 1631 * \return the __GLcontextModes supported by this driver 1632 */ 1633static const 1634__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1635{ 1636 GLenum fb_format[3]; 1637 GLenum fb_type[3]; 1638 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1639 * support pageflipping at all. 1640 */ 1641 static const GLenum back_buffer_modes[] = { 1642 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1643 }; 1644 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1645 int color; 1646 __DRIconfig **configs = NULL; 1647 1648 /* Calling driInitExtensions here, with a NULL context pointer, 1649 * does not actually enable the extensions. It just makes sure 1650 * that all the dispatch offsets for all the extensions that 1651 * *might* be enables are known. This is needed because the 1652 * dispatch offsets need to be known when _mesa_context_create 1653 * is called, but we can't enable the extensions until we have a 1654 * context pointer. 1655 * 1656 * Hello chicken. Hello egg. How are you two today? 1657 */ 1658 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1659 driInitExtensions( NULL, mm_extensions, GL_FALSE ); 1660#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1661 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1662 driInitSingleExtension( NULL, ARB_vp_extension ); 1663 driInitSingleExtension( NULL, NV_vp_extension ); 1664 driInitSingleExtension( NULL, ATI_fs_extension ); 1665 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1666#endif 1667 1668 if (!radeonInitDriver(psp)) { 1669 return NULL; 1670 } 1671 depth_bits[0] = 0; 1672 stencil_bits[0] = 0; 1673 depth_bits[1] = 16; 1674 stencil_bits[1] = 0; 1675 depth_bits[2] = 24; 1676 stencil_bits[2] = 0; 1677 depth_bits[3] = 24; 1678 stencil_bits[3] = 8; 1679 1680 msaa_samples_array[0] = 0; 1681 1682 fb_format[0] = GL_RGB; 1683 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1684 1685 fb_format[1] = GL_BGR; 1686 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1687 1688 fb_format[2] = GL_BGRA; 1689 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1690 1691 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1692 __DRIconfig **new_configs; 1693 1694 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1695 depth_bits, 1696 stencil_bits, 1697 ARRAY_SIZE(depth_bits), 1698 back_buffer_modes, 1699 ARRAY_SIZE(back_buffer_modes), 1700 msaa_samples_array, 1701 ARRAY_SIZE(msaa_samples_array)); 1702 if (configs == NULL) 1703 configs = new_configs; 1704 else 1705 configs = driConcatConfigs(configs, new_configs); 1706 } 1707 1708 if (configs == NULL) { 1709 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1710 __LINE__); 1711 return NULL; 1712 } 1713 1714 return (const __DRIconfig **)configs; 1715} 1716 1717/** 1718 * Get information about previous buffer swaps. 1719 */ 1720static int 1721getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1722{ 1723 struct radeon_framebuffer *rfb; 1724 1725 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1726 || (dPriv->driContextPriv->driverPrivate == NULL) 1727 || (sInfo == NULL) ) { 1728 return -1; 1729 } 1730 1731 rfb = dPriv->driverPrivate; 1732 sInfo->swap_count = rfb->swap_count; 1733 sInfo->swap_ust = rfb->swap_ust; 1734 sInfo->swap_missed_count = rfb->swap_missed_count; 1735 1736 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1737 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1738 : 0.0; 1739 1740 return 0; 1741} 1742 1743const struct __DriverAPIRec driDriverAPI = { 1744 .InitScreen = radeonInitScreen, 1745 .DestroyScreen = radeonDestroyScreen, 1746 .CreateContext = radeonCreateContext, 1747 .DestroyContext = radeonDestroyContext, 1748 .CreateBuffer = radeonCreateBuffer, 1749 .DestroyBuffer = radeonDestroyBuffer, 1750 .SwapBuffers = radeonSwapBuffers, 1751 .MakeCurrent = radeonMakeCurrent, 1752 .UnbindContext = radeonUnbindContext, 1753 .GetSwapInfo = getSwapInfo, 1754 .GetDrawableMSC = driDrawableGetMSC32, 1755 .WaitForMSC = driWaitForMSC32, 1756 .WaitForSBC = NULL, 1757 .SwapBuffersMSC = NULL, 1758 .CopySubBuffer = radeonCopySubBuffer, 1759 /* DRI2 */ 1760 .InitScreen2 = radeonInitScreen2, 1761}; 1762 1763