radeon_screen.c revision e5bed439be4fd7c3a349aedc4bff7eec4e4d363e
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_tex.h" 61#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 62#include "r600_context.h" 63#include "r700_driconf.h" /* +r6/r7 */ 64#include "r600_tex.h" /* +r6/r7 */ 65#endif 66 67#include "utils.h" 68#include "vblank.h" 69#include "drirenderbuffer.h" 70 71#include "radeon_bocs_wrapper.h" 72 73#include "GL/internal/dri_interface.h" 74 75/* Radeon configuration 76 */ 77#include "xmlpool.h" 78 79#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 80DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 81 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 82 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 83DRI_CONF_OPT_END 84 85#if !RADEON_COMMON /* R100 */ 86PUBLIC const char __driConfigOptions[] = 87DRI_CONF_BEGIN 88 DRI_CONF_SECTION_PERFORMANCE 89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 91 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 92 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 93 DRI_CONF_HYPERZ(false) 94 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 95 DRI_CONF_SECTION_END 96 DRI_CONF_SECTION_QUALITY 97 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 98 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 99 DRI_CONF_NO_NEG_LOD_BIAS(false) 100 DRI_CONF_FORCE_S3TC_ENABLE(false) 101 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 102 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 103 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 104 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 105 DRI_CONF_SECTION_END 106 DRI_CONF_SECTION_DEBUG 107 DRI_CONF_NO_RAST(false) 108 DRI_CONF_SECTION_END 109DRI_CONF_END; 110static const GLuint __driNConfigOptions = 15; 111 112#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 113 114PUBLIC const char __driConfigOptions[] = 115DRI_CONF_BEGIN 116 DRI_CONF_SECTION_PERFORMANCE 117 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 118 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 119 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 121 DRI_CONF_HYPERZ(false) 122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 123 DRI_CONF_SECTION_END 124 DRI_CONF_SECTION_QUALITY 125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 127 DRI_CONF_NO_NEG_LOD_BIAS(false) 128 DRI_CONF_FORCE_S3TC_ENABLE(false) 129 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 130 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 131 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 132 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 133 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_DEBUG 136 DRI_CONF_NO_RAST(false) 137 DRI_CONF_SECTION_END 138 DRI_CONF_SECTION_SOFTWARE 139 DRI_CONF_NV_VERTEX_PROGRAM(false) 140 DRI_CONF_SECTION_END 141DRI_CONF_END; 142static const GLuint __driNConfigOptions = 17; 143 144extern const struct dri_extension blend_extensions[]; 145extern const struct dri_extension ARB_vp_extension[]; 146extern const struct dri_extension NV_vp_extension[]; 147extern const struct dri_extension ATI_fs_extension[]; 148extern const struct dri_extension point_extensions[]; 149 150#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 151 152#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 153#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 154 155/* TODO: integrate these into xmlpool.h! */ 156#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 157DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 158 DRI_CONF_DESC(en,"Number of texture image units") \ 159 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 160DRI_CONF_OPT_END 161 162#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 163DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 164 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 165 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 166DRI_CONF_OPT_END 167 168 169 170#define DRI_CONF_DISABLE_S3TC(def) \ 171DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 172 DRI_CONF_DESC(en,"Disable S3TC compression") \ 173DRI_CONF_OPT_END 174 175#define DRI_CONF_DISABLE_FALLBACK(def) \ 176DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 177 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 178DRI_CONF_OPT_END 179 180#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 181DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 182 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 183DRI_CONF_OPT_END 184 185#define DRI_CONF_FP_OPTIMIZATION(def) \ 186DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 187 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 188 DRI_CONF_ENUM(0,"Optimize for Speed") \ 189 DRI_CONF_ENUM(1,"Optimize for Quality") \ 190 DRI_CONF_DESC_END \ 191DRI_CONF_OPT_END 192 193PUBLIC const char __driConfigOptions[] = 194DRI_CONF_BEGIN 195 DRI_CONF_SECTION_PERFORMANCE 196 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 197 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 198 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 199 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 200 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 201 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 202 DRI_CONF_DISABLE_FALLBACK(true) 203 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 204 DRI_CONF_SECTION_END 205 DRI_CONF_SECTION_QUALITY 206 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 207 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 208 DRI_CONF_FORCE_S3TC_ENABLE(false) 209 DRI_CONF_DISABLE_S3TC(false) 210 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 211 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 212 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 213 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 214 DRI_CONF_SECTION_END 215 DRI_CONF_SECTION_DEBUG 216 DRI_CONF_NO_RAST(false) 217 DRI_CONF_SECTION_END 218DRI_CONF_END; 219static const GLuint __driNConfigOptions = 17; 220 221extern const struct dri_extension gl_20_extension[]; 222 223#ifndef RADEON_DEBUG 224 225static const struct dri_debug_control debug_control[] = { 226 {"fall", DEBUG_FALLBACKS}, 227 {"tex", DEBUG_TEXTURE}, 228 {"ioctl", DEBUG_IOCTL}, 229 {"prim", DEBUG_PRIMS}, 230 {"vert", DEBUG_VERTS}, 231 {"state", DEBUG_STATE}, 232 {"code", DEBUG_CODEGEN}, 233 {"vfmt", DEBUG_VFMT}, 234 {"vtxf", DEBUG_VFMT}, 235 {"verb", DEBUG_VERBOSE}, 236 {"dri", DEBUG_DRI}, 237 {"dma", DEBUG_DMA}, 238 {"san", DEBUG_SANITY}, 239 {"sync", DEBUG_SYNC}, 240 {"pix", DEBUG_PIXEL}, 241 {"mem", DEBUG_MEMORY}, 242 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 243 {NULL, 0} 244}; 245#endif /* RADEON_DEBUG */ 246 247#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 248 249extern const struct dri_extension card_extensions[]; 250extern const struct dri_extension mm_extensions[]; 251 252static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 253 254static int 255radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) 256{ 257 int ret; 258 drm_radeon_getparam_t gp = { 0 }; 259 struct drm_radeon_info info = { 0 }; 260 261 if (sPriv->drm_version.major >= 2) { 262 info.value = (uint64_t)value; 263 switch (param) { 264 case RADEON_PARAM_DEVICE_ID: 265 info.request = RADEON_INFO_DEVICE_ID; 266 break; 267 case RADEON_PARAM_NUM_GB_PIPES: 268 info.request = RADEON_INFO_NUM_GB_PIPES; 269 break; 270 default: 271 return -EINVAL; 272 } 273 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 274 } else { 275 gp.param = param; 276 gp.value = value; 277 278 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 279 } 280 return ret; 281} 282 283static const __DRIconfig ** 284radeonFillInModes( __DRIscreenPrivate *psp, 285 unsigned pixel_bits, unsigned depth_bits, 286 unsigned stencil_bits, GLboolean have_back_buffer ) 287{ 288 __DRIconfig **configs; 289 __GLcontextModes *m; 290 unsigned depth_buffer_factor; 291 unsigned back_buffer_factor; 292 int i; 293 294 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 295 * enough to add support. Basically, if a context is created with an 296 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 297 * will never be used. 298 */ 299 static const GLenum back_buffer_modes[] = { 300 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 301 }; 302 303 uint8_t depth_bits_array[2]; 304 uint8_t stencil_bits_array[2]; 305 uint8_t msaa_samples_array[1]; 306 307 depth_bits_array[0] = depth_bits; 308 depth_bits_array[1] = depth_bits; 309 310 /* Just like with the accumulation buffer, always provide some modes 311 * with a stencil buffer. It will be a sw fallback, but some apps won't 312 * care about that. 313 */ 314 stencil_bits_array[0] = stencil_bits; 315 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 316 317 msaa_samples_array[0] = 0; 318 319 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1; 320 back_buffer_factor = (have_back_buffer) ? 2 : 1; 321 322 if (pixel_bits == 16) { 323 __DRIconfig **configs_a8r8g8b8; 324 __DRIconfig **configs_r5g6b5; 325 326 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 327 depth_bits_array, stencil_bits_array, 328 depth_buffer_factor, back_buffer_modes, 329 back_buffer_factor, msaa_samples_array, 330 1); 331 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 332 depth_bits_array, stencil_bits_array, 333 1, back_buffer_modes, 1, 334 msaa_samples_array, 1); 335 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 336 } else 337 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 338 depth_bits_array, stencil_bits_array, 339 depth_buffer_factor, 340 back_buffer_modes, back_buffer_factor, 341 msaa_samples_array, 1); 342 343 if (configs == NULL) { 344 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 345 __func__, __LINE__ ); 346 return NULL; 347 } 348 349 /* Mark the visual as slow if there are "fake" stencil bits. 350 */ 351 for (i = 0; configs[i]; i++) { 352 m = &configs[i]->modes; 353 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 354 m->visualRating = GLX_SLOW_CONFIG; 355 } 356 } 357 358 return (const __DRIconfig **) configs; 359} 360 361#if !RADEON_COMMON 362static const __DRItexOffsetExtension radeonTexOffsetExtension = { 363 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 364 radeonSetTexOffset, 365}; 366 367static const __DRItexBufferExtension radeonTexBufferExtension = { 368 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 369 radeonSetTexBuffer, 370 radeonSetTexBuffer2, 371}; 372#endif 373 374#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 375static const __DRIallocateExtension r200AllocateExtension = { 376 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 377 r200AllocateMemoryMESA, 378 r200FreeMemoryMESA, 379 r200GetMemoryOffsetMESA 380}; 381 382static const __DRItexOffsetExtension r200texOffsetExtension = { 383 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 384 r200SetTexOffset, 385}; 386 387static const __DRItexBufferExtension r200TexBufferExtension = { 388 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 389 r200SetTexBuffer, 390 r200SetTexBuffer2, 391}; 392#endif 393 394#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 395static const __DRItexOffsetExtension r300texOffsetExtension = { 396 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 397 r300SetTexOffset, 398}; 399 400static const __DRItexBufferExtension r300TexBufferExtension = { 401 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 402 r300SetTexBuffer, 403 r300SetTexBuffer2, 404}; 405#endif 406 407#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 408static const __DRItexOffsetExtension r600texOffsetExtension = { 409 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 410 r600SetTexOffset, /* +r6/r7 */ 411}; 412 413static const __DRItexBufferExtension r600TexBufferExtension = { 414 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 415 r600SetTexBuffer, /* +r6/r7 */ 416 r600SetTexBuffer2, /* +r6/r7 */ 417}; 418#endif 419 420static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 421{ 422 screen->device_id = device_id; 423 screen->chip_flags = 0; 424 switch ( device_id ) { 425 case PCI_CHIP_RADEON_LY: 426 case PCI_CHIP_RADEON_LZ: 427 case PCI_CHIP_RADEON_QY: 428 case PCI_CHIP_RADEON_QZ: 429 case PCI_CHIP_RN50_515E: 430 case PCI_CHIP_RN50_5969: 431 screen->chip_family = CHIP_FAMILY_RV100; 432 break; 433 434 case PCI_CHIP_RS100_4136: 435 case PCI_CHIP_RS100_4336: 436 screen->chip_family = CHIP_FAMILY_RS100; 437 break; 438 439 case PCI_CHIP_RS200_4137: 440 case PCI_CHIP_RS200_4337: 441 case PCI_CHIP_RS250_4237: 442 case PCI_CHIP_RS250_4437: 443 screen->chip_family = CHIP_FAMILY_RS200; 444 break; 445 446 case PCI_CHIP_RADEON_QD: 447 case PCI_CHIP_RADEON_QE: 448 case PCI_CHIP_RADEON_QF: 449 case PCI_CHIP_RADEON_QG: 450 /* all original radeons (7200) presumably have a stencil op bug */ 451 screen->chip_family = CHIP_FAMILY_R100; 452 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 453 break; 454 455 case PCI_CHIP_RV200_QW: 456 case PCI_CHIP_RV200_QX: 457 case PCI_CHIP_RADEON_LW: 458 case PCI_CHIP_RADEON_LX: 459 screen->chip_family = CHIP_FAMILY_RV200; 460 screen->chip_flags = RADEON_CHIPSET_TCL; 461 break; 462 463 case PCI_CHIP_R200_BB: 464 case PCI_CHIP_R200_BC: 465 case PCI_CHIP_R200_QH: 466 case PCI_CHIP_R200_QL: 467 case PCI_CHIP_R200_QM: 468 screen->chip_family = CHIP_FAMILY_R200; 469 screen->chip_flags = RADEON_CHIPSET_TCL; 470 break; 471 472 case PCI_CHIP_RV250_If: 473 case PCI_CHIP_RV250_Ig: 474 case PCI_CHIP_RV250_Ld: 475 case PCI_CHIP_RV250_Lf: 476 case PCI_CHIP_RV250_Lg: 477 screen->chip_family = CHIP_FAMILY_RV250; 478 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 479 break; 480 481 case PCI_CHIP_RV280_5960: 482 case PCI_CHIP_RV280_5961: 483 case PCI_CHIP_RV280_5962: 484 case PCI_CHIP_RV280_5964: 485 case PCI_CHIP_RV280_5965: 486 case PCI_CHIP_RV280_5C61: 487 case PCI_CHIP_RV280_5C63: 488 screen->chip_family = CHIP_FAMILY_RV280; 489 screen->chip_flags = RADEON_CHIPSET_TCL; 490 break; 491 492 case PCI_CHIP_RS300_5834: 493 case PCI_CHIP_RS300_5835: 494 case PCI_CHIP_RS350_7834: 495 case PCI_CHIP_RS350_7835: 496 screen->chip_family = CHIP_FAMILY_RS300; 497 break; 498 499 case PCI_CHIP_R300_AD: 500 case PCI_CHIP_R300_AE: 501 case PCI_CHIP_R300_AF: 502 case PCI_CHIP_R300_AG: 503 case PCI_CHIP_R300_ND: 504 case PCI_CHIP_R300_NE: 505 case PCI_CHIP_R300_NF: 506 case PCI_CHIP_R300_NG: 507 screen->chip_family = CHIP_FAMILY_R300; 508 screen->chip_flags = RADEON_CHIPSET_TCL; 509 break; 510 511 case PCI_CHIP_RV350_AP: 512 case PCI_CHIP_RV350_AQ: 513 case PCI_CHIP_RV350_AR: 514 case PCI_CHIP_RV350_AS: 515 case PCI_CHIP_RV350_AT: 516 case PCI_CHIP_RV350_AV: 517 case PCI_CHIP_RV350_AU: 518 case PCI_CHIP_RV350_NP: 519 case PCI_CHIP_RV350_NQ: 520 case PCI_CHIP_RV350_NR: 521 case PCI_CHIP_RV350_NS: 522 case PCI_CHIP_RV350_NT: 523 case PCI_CHIP_RV350_NV: 524 screen->chip_family = CHIP_FAMILY_RV350; 525 screen->chip_flags = RADEON_CHIPSET_TCL; 526 break; 527 528 case PCI_CHIP_R350_AH: 529 case PCI_CHIP_R350_AI: 530 case PCI_CHIP_R350_AJ: 531 case PCI_CHIP_R350_AK: 532 case PCI_CHIP_R350_NH: 533 case PCI_CHIP_R350_NI: 534 case PCI_CHIP_R360_NJ: 535 case PCI_CHIP_R350_NK: 536 screen->chip_family = CHIP_FAMILY_R350; 537 screen->chip_flags = RADEON_CHIPSET_TCL; 538 break; 539 540 case PCI_CHIP_RV370_5460: 541 case PCI_CHIP_RV370_5462: 542 case PCI_CHIP_RV370_5464: 543 case PCI_CHIP_RV370_5B60: 544 case PCI_CHIP_RV370_5B62: 545 case PCI_CHIP_RV370_5B63: 546 case PCI_CHIP_RV370_5B64: 547 case PCI_CHIP_RV370_5B65: 548 case PCI_CHIP_RV380_3150: 549 case PCI_CHIP_RV380_3152: 550 case PCI_CHIP_RV380_3154: 551 case PCI_CHIP_RV380_3E50: 552 case PCI_CHIP_RV380_3E54: 553 screen->chip_family = CHIP_FAMILY_RV380; 554 screen->chip_flags = RADEON_CHIPSET_TCL; 555 break; 556 557 case PCI_CHIP_R420_JN: 558 case PCI_CHIP_R420_JH: 559 case PCI_CHIP_R420_JI: 560 case PCI_CHIP_R420_JJ: 561 case PCI_CHIP_R420_JK: 562 case PCI_CHIP_R420_JL: 563 case PCI_CHIP_R420_JM: 564 case PCI_CHIP_R420_JO: 565 case PCI_CHIP_R420_JP: 566 case PCI_CHIP_R420_JT: 567 case PCI_CHIP_R481_4B49: 568 case PCI_CHIP_R481_4B4A: 569 case PCI_CHIP_R481_4B4B: 570 case PCI_CHIP_R481_4B4C: 571 case PCI_CHIP_R423_UH: 572 case PCI_CHIP_R423_UI: 573 case PCI_CHIP_R423_UJ: 574 case PCI_CHIP_R423_UK: 575 case PCI_CHIP_R430_554C: 576 case PCI_CHIP_R430_554D: 577 case PCI_CHIP_R430_554E: 578 case PCI_CHIP_R430_554F: 579 case PCI_CHIP_R423_5550: 580 case PCI_CHIP_R423_UQ: 581 case PCI_CHIP_R423_UR: 582 case PCI_CHIP_R423_UT: 583 case PCI_CHIP_R430_5D48: 584 case PCI_CHIP_R430_5D49: 585 case PCI_CHIP_R430_5D4A: 586 case PCI_CHIP_R480_5D4C: 587 case PCI_CHIP_R480_5D4D: 588 case PCI_CHIP_R480_5D4E: 589 case PCI_CHIP_R480_5D4F: 590 case PCI_CHIP_R480_5D50: 591 case PCI_CHIP_R480_5D52: 592 case PCI_CHIP_R423_5D57: 593 screen->chip_family = CHIP_FAMILY_R420; 594 screen->chip_flags = RADEON_CHIPSET_TCL; 595 break; 596 597 case PCI_CHIP_RV410_5E4C: 598 case PCI_CHIP_RV410_5E4F: 599 case PCI_CHIP_RV410_564A: 600 case PCI_CHIP_RV410_564B: 601 case PCI_CHIP_RV410_564F: 602 case PCI_CHIP_RV410_5652: 603 case PCI_CHIP_RV410_5653: 604 case PCI_CHIP_RV410_5657: 605 case PCI_CHIP_RV410_5E48: 606 case PCI_CHIP_RV410_5E4A: 607 case PCI_CHIP_RV410_5E4B: 608 case PCI_CHIP_RV410_5E4D: 609 screen->chip_family = CHIP_FAMILY_RV410; 610 screen->chip_flags = RADEON_CHIPSET_TCL; 611 break; 612 613 case PCI_CHIP_RS480_5954: 614 case PCI_CHIP_RS480_5955: 615 case PCI_CHIP_RS482_5974: 616 case PCI_CHIP_RS482_5975: 617 case PCI_CHIP_RS400_5A41: 618 case PCI_CHIP_RS400_5A42: 619 case PCI_CHIP_RC410_5A61: 620 case PCI_CHIP_RC410_5A62: 621 screen->chip_family = CHIP_FAMILY_RS400; 622 break; 623 624 case PCI_CHIP_RS600_793F: 625 case PCI_CHIP_RS600_7941: 626 case PCI_CHIP_RS600_7942: 627 screen->chip_family = CHIP_FAMILY_RS600; 628 break; 629 630 case PCI_CHIP_RS690_791E: 631 case PCI_CHIP_RS690_791F: 632 screen->chip_family = CHIP_FAMILY_RS690; 633 break; 634 case PCI_CHIP_RS740_796C: 635 case PCI_CHIP_RS740_796D: 636 case PCI_CHIP_RS740_796E: 637 case PCI_CHIP_RS740_796F: 638 screen->chip_family = CHIP_FAMILY_RS740; 639 break; 640 641 case PCI_CHIP_R520_7100: 642 case PCI_CHIP_R520_7101: 643 case PCI_CHIP_R520_7102: 644 case PCI_CHIP_R520_7103: 645 case PCI_CHIP_R520_7104: 646 case PCI_CHIP_R520_7105: 647 case PCI_CHIP_R520_7106: 648 case PCI_CHIP_R520_7108: 649 case PCI_CHIP_R520_7109: 650 case PCI_CHIP_R520_710A: 651 case PCI_CHIP_R520_710B: 652 case PCI_CHIP_R520_710C: 653 case PCI_CHIP_R520_710E: 654 case PCI_CHIP_R520_710F: 655 screen->chip_family = CHIP_FAMILY_R520; 656 screen->chip_flags = RADEON_CHIPSET_TCL; 657 break; 658 659 case PCI_CHIP_RV515_7140: 660 case PCI_CHIP_RV515_7141: 661 case PCI_CHIP_RV515_7142: 662 case PCI_CHIP_RV515_7143: 663 case PCI_CHIP_RV515_7144: 664 case PCI_CHIP_RV515_7145: 665 case PCI_CHIP_RV515_7146: 666 case PCI_CHIP_RV515_7147: 667 case PCI_CHIP_RV515_7149: 668 case PCI_CHIP_RV515_714A: 669 case PCI_CHIP_RV515_714B: 670 case PCI_CHIP_RV515_714C: 671 case PCI_CHIP_RV515_714D: 672 case PCI_CHIP_RV515_714E: 673 case PCI_CHIP_RV515_714F: 674 case PCI_CHIP_RV515_7151: 675 case PCI_CHIP_RV515_7152: 676 case PCI_CHIP_RV515_7153: 677 case PCI_CHIP_RV515_715E: 678 case PCI_CHIP_RV515_715F: 679 case PCI_CHIP_RV515_7180: 680 case PCI_CHIP_RV515_7181: 681 case PCI_CHIP_RV515_7183: 682 case PCI_CHIP_RV515_7186: 683 case PCI_CHIP_RV515_7187: 684 case PCI_CHIP_RV515_7188: 685 case PCI_CHIP_RV515_718A: 686 case PCI_CHIP_RV515_718B: 687 case PCI_CHIP_RV515_718C: 688 case PCI_CHIP_RV515_718D: 689 case PCI_CHIP_RV515_718F: 690 case PCI_CHIP_RV515_7193: 691 case PCI_CHIP_RV515_7196: 692 case PCI_CHIP_RV515_719B: 693 case PCI_CHIP_RV515_719F: 694 case PCI_CHIP_RV515_7200: 695 case PCI_CHIP_RV515_7210: 696 case PCI_CHIP_RV515_7211: 697 screen->chip_family = CHIP_FAMILY_RV515; 698 screen->chip_flags = RADEON_CHIPSET_TCL; 699 break; 700 701 case PCI_CHIP_RV530_71C0: 702 case PCI_CHIP_RV530_71C1: 703 case PCI_CHIP_RV530_71C2: 704 case PCI_CHIP_RV530_71C3: 705 case PCI_CHIP_RV530_71C4: 706 case PCI_CHIP_RV530_71C5: 707 case PCI_CHIP_RV530_71C6: 708 case PCI_CHIP_RV530_71C7: 709 case PCI_CHIP_RV530_71CD: 710 case PCI_CHIP_RV530_71CE: 711 case PCI_CHIP_RV530_71D2: 712 case PCI_CHIP_RV530_71D4: 713 case PCI_CHIP_RV530_71D5: 714 case PCI_CHIP_RV530_71D6: 715 case PCI_CHIP_RV530_71DA: 716 case PCI_CHIP_RV530_71DE: 717 screen->chip_family = CHIP_FAMILY_RV530; 718 screen->chip_flags = RADEON_CHIPSET_TCL; 719 break; 720 721 case PCI_CHIP_R580_7240: 722 case PCI_CHIP_R580_7243: 723 case PCI_CHIP_R580_7244: 724 case PCI_CHIP_R580_7245: 725 case PCI_CHIP_R580_7246: 726 case PCI_CHIP_R580_7247: 727 case PCI_CHIP_R580_7248: 728 case PCI_CHIP_R580_7249: 729 case PCI_CHIP_R580_724A: 730 case PCI_CHIP_R580_724B: 731 case PCI_CHIP_R580_724C: 732 case PCI_CHIP_R580_724D: 733 case PCI_CHIP_R580_724E: 734 case PCI_CHIP_R580_724F: 735 case PCI_CHIP_R580_7284: 736 screen->chip_family = CHIP_FAMILY_R580; 737 screen->chip_flags = RADEON_CHIPSET_TCL; 738 break; 739 740 case PCI_CHIP_RV570_7280: 741 case PCI_CHIP_RV560_7281: 742 case PCI_CHIP_RV560_7283: 743 case PCI_CHIP_RV560_7287: 744 case PCI_CHIP_RV570_7288: 745 case PCI_CHIP_RV570_7289: 746 case PCI_CHIP_RV570_728B: 747 case PCI_CHIP_RV570_728C: 748 case PCI_CHIP_RV560_7290: 749 case PCI_CHIP_RV560_7291: 750 case PCI_CHIP_RV560_7293: 751 case PCI_CHIP_RV560_7297: 752 screen->chip_family = CHIP_FAMILY_RV560; 753 screen->chip_flags = RADEON_CHIPSET_TCL; 754 break; 755 756 case PCI_CHIP_R600_9400: 757 case PCI_CHIP_R600_9401: 758 case PCI_CHIP_R600_9402: 759 case PCI_CHIP_R600_9403: 760 case PCI_CHIP_R600_9405: 761 case PCI_CHIP_R600_940A: 762 case PCI_CHIP_R600_940B: 763 case PCI_CHIP_R600_940F: 764 screen->chip_family = CHIP_FAMILY_R600; 765 screen->chip_flags = RADEON_CHIPSET_TCL; 766 break; 767 768 case PCI_CHIP_RV610_94C0: 769 case PCI_CHIP_RV610_94C1: 770 case PCI_CHIP_RV610_94C3: 771 case PCI_CHIP_RV610_94C4: 772 case PCI_CHIP_RV610_94C5: 773 case PCI_CHIP_RV610_94C6: 774 case PCI_CHIP_RV610_94C7: 775 case PCI_CHIP_RV610_94C8: 776 case PCI_CHIP_RV610_94C9: 777 case PCI_CHIP_RV610_94CB: 778 case PCI_CHIP_RV610_94CC: 779 case PCI_CHIP_RV610_94CD: 780 screen->chip_family = CHIP_FAMILY_RV610; 781 screen->chip_flags = RADEON_CHIPSET_TCL; 782 break; 783 784 case PCI_CHIP_RV630_9580: 785 case PCI_CHIP_RV630_9581: 786 case PCI_CHIP_RV630_9583: 787 case PCI_CHIP_RV630_9586: 788 case PCI_CHIP_RV630_9587: 789 case PCI_CHIP_RV630_9588: 790 case PCI_CHIP_RV630_9589: 791 case PCI_CHIP_RV630_958A: 792 case PCI_CHIP_RV630_958B: 793 case PCI_CHIP_RV630_958C: 794 case PCI_CHIP_RV630_958D: 795 case PCI_CHIP_RV630_958E: 796 case PCI_CHIP_RV630_958F: 797 screen->chip_family = CHIP_FAMILY_RV630; 798 screen->chip_flags = RADEON_CHIPSET_TCL; 799 break; 800 801 case PCI_CHIP_RV670_9500: 802 case PCI_CHIP_RV670_9501: 803 case PCI_CHIP_RV670_9504: 804 case PCI_CHIP_RV670_9505: 805 case PCI_CHIP_RV670_9506: 806 case PCI_CHIP_RV670_9507: 807 case PCI_CHIP_RV670_9508: 808 case PCI_CHIP_RV670_9509: 809 case PCI_CHIP_RV670_950F: 810 case PCI_CHIP_RV670_9511: 811 case PCI_CHIP_RV670_9515: 812 case PCI_CHIP_RV670_9517: 813 case PCI_CHIP_RV670_9519: 814 screen->chip_family = CHIP_FAMILY_RV670; 815 screen->chip_flags = RADEON_CHIPSET_TCL; 816 break; 817 818 case PCI_CHIP_RV620_95C0: 819 case PCI_CHIP_RV620_95C2: 820 case PCI_CHIP_RV620_95C4: 821 case PCI_CHIP_RV620_95C5: 822 case PCI_CHIP_RV620_95C6: 823 case PCI_CHIP_RV620_95C7: 824 case PCI_CHIP_RV620_95C9: 825 case PCI_CHIP_RV620_95CC: 826 case PCI_CHIP_RV620_95CD: 827 case PCI_CHIP_RV620_95CE: 828 case PCI_CHIP_RV620_95CF: 829 screen->chip_family = CHIP_FAMILY_RV620; 830 screen->chip_flags = RADEON_CHIPSET_TCL; 831 break; 832 833 case PCI_CHIP_RV635_9590: 834 case PCI_CHIP_RV635_9591: 835 case PCI_CHIP_RV635_9593: 836 case PCI_CHIP_RV635_9595: 837 case PCI_CHIP_RV635_9596: 838 case PCI_CHIP_RV635_9597: 839 case PCI_CHIP_RV635_9598: 840 case PCI_CHIP_RV635_9599: 841 case PCI_CHIP_RV635_959B: 842 screen->chip_family = CHIP_FAMILY_RV635; 843 screen->chip_flags = RADEON_CHIPSET_TCL; 844 break; 845 846 case PCI_CHIP_RS780_9610: 847 case PCI_CHIP_RS780_9611: 848 case PCI_CHIP_RS780_9612: 849 case PCI_CHIP_RS780_9613: 850 case PCI_CHIP_RS780_9614: 851 case PCI_CHIP_RS780_9615: 852 case PCI_CHIP_RS780_9616: 853 screen->chip_family = CHIP_FAMILY_RS780; 854 screen->chip_flags = RADEON_CHIPSET_TCL; 855 break; 856 857 case PCI_CHIP_RV770_9440: 858 case PCI_CHIP_RV770_9441: 859 case PCI_CHIP_RV770_9442: 860 case PCI_CHIP_RV770_9444: 861 case PCI_CHIP_RV770_9446: 862 case PCI_CHIP_RV770_944A: 863 case PCI_CHIP_RV770_944B: 864 case PCI_CHIP_RV770_944C: 865 case PCI_CHIP_RV770_944E: 866 case PCI_CHIP_RV770_9450: 867 case PCI_CHIP_RV770_9452: 868 case PCI_CHIP_RV770_9456: 869 case PCI_CHIP_RV770_945A: 870 case PCI_CHIP_RV770_945B: 871 case PCI_CHIP_RV790_9460: 872 case PCI_CHIP_RV790_9462: 873 case PCI_CHIP_RV770_946A: 874 case PCI_CHIP_RV770_946B: 875 case PCI_CHIP_RV770_947A: 876 case PCI_CHIP_RV770_947B: 877 screen->chip_family = CHIP_FAMILY_RV770; 878 screen->chip_flags = RADEON_CHIPSET_TCL; 879 break; 880 881 case PCI_CHIP_RV730_9487: 882 case PCI_CHIP_RV730_9489: 883 case PCI_CHIP_RV730_948F: 884 case PCI_CHIP_RV730_9490: 885 case PCI_CHIP_RV730_9491: 886 case PCI_CHIP_RV730_9498: 887 case PCI_CHIP_RV730_949C: 888 case PCI_CHIP_RV730_949E: 889 case PCI_CHIP_RV730_949F: 890 screen->chip_family = CHIP_FAMILY_RV730; 891 screen->chip_flags = RADEON_CHIPSET_TCL; 892 break; 893 894 case PCI_CHIP_RV710_9540: 895 case PCI_CHIP_RV710_9541: 896 case PCI_CHIP_RV710_9542: 897 case PCI_CHIP_RV710_954E: 898 case PCI_CHIP_RV710_954F: 899 case PCI_CHIP_RV710_9552: 900 case PCI_CHIP_RV710_9553: 901 case PCI_CHIP_RV710_9555: 902 screen->chip_family = CHIP_FAMILY_RV710; 903 screen->chip_flags = RADEON_CHIPSET_TCL; 904 break; 905 906 case PCI_CHIP_RV740_94A0: 907 case PCI_CHIP_RV740_94A1: 908 case PCI_CHIP_RV740_94B1: 909 case PCI_CHIP_RV740_94B3: 910 case PCI_CHIP_RV740_94B5: 911 screen->chip_family = CHIP_FAMILY_RV740; 912 screen->chip_flags = RADEON_CHIPSET_TCL; 913 break; 914 915 default: 916 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 917 device_id); 918 return -1; 919 } 920 921 return 0; 922} 923 924 925/* Create the device specific screen private data struct. 926 */ 927static radeonScreenPtr 928radeonCreateScreen( __DRIscreenPrivate *sPriv ) 929{ 930 radeonScreenPtr screen; 931 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 932 unsigned char *RADEONMMIO = NULL; 933 int i; 934 int ret; 935 uint32_t temp = 0; 936 937 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 938 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 939 return GL_FALSE; 940 } 941 942 /* Allocate the private area */ 943 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 944 if ( !screen ) { 945 __driUtilMessage("%s: Could not allocate memory for screen structure", 946 __FUNCTION__); 947 return NULL; 948 } 949 950#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 951 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 952#endif 953 /* parse information in __driConfigOptions */ 954 driParseOptionInfo (&screen->optionCache, 955 __driConfigOptions, __driNConfigOptions); 956 957 /* This is first since which regions we map depends on whether or 958 * not we are using a PCI card. 959 */ 960 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 961 { 962 int ret; 963 964 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 965 &screen->gart_buffer_offset); 966 967 if (ret) { 968 FREE( screen ); 969 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 970 return NULL; 971 } 972 973 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 974 &screen->gart_base); 975 if (ret) { 976 FREE( screen ); 977 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 978 return NULL; 979 } 980 981 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 982 &screen->irq); 983 if (ret) { 984 FREE( screen ); 985 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 986 return NULL; 987 } 988 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 989 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 990 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 991 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 992 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 993 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 994 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 995 } 996 997 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 998 if (ret == -1) 999 return NULL; 1000 1001 screen->mmio.handle = dri_priv->registerHandle; 1002 screen->mmio.size = dri_priv->registerSize; 1003 if ( drmMap( sPriv->fd, 1004 screen->mmio.handle, 1005 screen->mmio.size, 1006 &screen->mmio.map ) ) { 1007 FREE( screen ); 1008 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1009 return NULL; 1010 } 1011 1012 RADEONMMIO = screen->mmio.map; 1013 1014 screen->status.handle = dri_priv->statusHandle; 1015 screen->status.size = dri_priv->statusSize; 1016 if ( drmMap( sPriv->fd, 1017 screen->status.handle, 1018 screen->status.size, 1019 &screen->status.map ) ) { 1020 drmUnmap( screen->mmio.map, screen->mmio.size ); 1021 FREE( screen ); 1022 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1023 return NULL; 1024 } 1025 if (screen->chip_family < CHIP_FAMILY_R600) 1026 screen->scratch = (__volatile__ uint32_t *) 1027 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1028 else 1029 screen->scratch = (__volatile__ uint32_t *) 1030 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1031 1032 screen->buffers = drmMapBufs( sPriv->fd ); 1033 if ( !screen->buffers ) { 1034 drmUnmap( screen->status.map, screen->status.size ); 1035 drmUnmap( screen->mmio.map, screen->mmio.size ); 1036 FREE( screen ); 1037 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1038 return NULL; 1039 } 1040 1041 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1042 screen->gartTextures.handle = dri_priv->gartTexHandle; 1043 screen->gartTextures.size = dri_priv->gartTexMapSize; 1044 if ( drmMap( sPriv->fd, 1045 screen->gartTextures.handle, 1046 screen->gartTextures.size, 1047 (drmAddressPtr)&screen->gartTextures.map ) ) { 1048 drmUnmapBufs( screen->buffers ); 1049 drmUnmap( screen->status.map, screen->status.size ); 1050 drmUnmap( screen->mmio.map, screen->mmio.size ); 1051 FREE( screen ); 1052 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1053 return NULL; 1054 } 1055 1056 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1057 } 1058 1059 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1060 sPriv->ddx_version.minor < 2) { 1061 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1062 return NULL; 1063 } 1064 1065 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1066 fprintf(stderr, "R500 support requires a newer drm.\n"); 1067 return NULL; 1068 } 1069 1070 if (getenv("R300_NO_TCL")) 1071 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1072 1073 if (screen->chip_family <= CHIP_FAMILY_RS200) 1074 screen->chip_flags |= RADEON_CLASS_R100; 1075 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1076 screen->chip_flags |= RADEON_CLASS_R200; 1077 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1078 screen->chip_flags |= RADEON_CLASS_R300; 1079 else 1080 screen->chip_flags |= RADEON_CLASS_R600; 1081 1082 screen->cpp = dri_priv->bpp / 8; 1083 screen->AGPMode = dri_priv->AGPMode; 1084 1085 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1086 1087 /* +r6/r7 */ 1088 if(screen->chip_family >= CHIP_FAMILY_R600) 1089 { 1090 if (ret) 1091 { 1092 FREE( screen ); 1093 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1094 return NULL; 1095 } 1096 else 1097 { 1098 screen->fbLocation = (temp & 0xffff) << 24; 1099 } 1100 } 1101 else 1102 { 1103 if (ret) 1104 { 1105 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1106 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1107 else 1108 { 1109 FREE( screen ); 1110 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1111 return NULL; 1112 } 1113 } 1114 else 1115 { 1116 screen->fbLocation = (temp & 0xffff) << 16; 1117 } 1118 } 1119 1120 if (IS_R300_CLASS(screen)) { 1121 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1122 if (ret) { 1123 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1124 switch (screen->chip_family) { 1125 case CHIP_FAMILY_R300: 1126 case CHIP_FAMILY_R350: 1127 screen->num_gb_pipes = 2; 1128 break; 1129 case CHIP_FAMILY_R420: 1130 case CHIP_FAMILY_R520: 1131 case CHIP_FAMILY_R580: 1132 case CHIP_FAMILY_RV560: 1133 case CHIP_FAMILY_RV570: 1134 screen->num_gb_pipes = 4; 1135 break; 1136 case CHIP_FAMILY_RV350: 1137 case CHIP_FAMILY_RV515: 1138 case CHIP_FAMILY_RV530: 1139 case CHIP_FAMILY_RV410: 1140 default: 1141 screen->num_gb_pipes = 1; 1142 break; 1143 } 1144 } else { 1145 screen->num_gb_pipes = temp; 1146 } 1147 1148 /* pipe overrides */ 1149 switch (dri_priv->deviceID) { 1150 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1151 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1152 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1153 screen->num_gb_pipes = 1; 1154 break; 1155 default: 1156 break; 1157 } 1158 } 1159 1160 if ( sPriv->drm_version.minor >= 10 ) { 1161 drm_radeon_setparam_t sp; 1162 1163 sp.param = RADEON_SETPARAM_FB_LOCATION; 1164 sp.value = screen->fbLocation; 1165 1166 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1167 &sp, sizeof( sp ) ); 1168 } 1169 1170 screen->frontOffset = dri_priv->frontOffset; 1171 screen->frontPitch = dri_priv->frontPitch; 1172 screen->backOffset = dri_priv->backOffset; 1173 screen->backPitch = dri_priv->backPitch; 1174 screen->depthOffset = dri_priv->depthOffset; 1175 screen->depthPitch = dri_priv->depthPitch; 1176 1177 /* Check if ddx has set up a surface reg to cover depth buffer */ 1178 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1179 /* these chips don't use tiled z without hyperz. So always pretend 1180 we have set up a surface which will cause linear reads/writes */ 1181 (IS_R100_CLASS(screen) && 1182 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1183 1184 if ( dri_priv->textureSize == 0 ) { 1185 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1186 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1187 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1188 dri_priv->log2GARTTexGran; 1189 } else { 1190 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1191 + screen->fbLocation; 1192 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1193 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1194 dri_priv->log2TexGran; 1195 } 1196 1197 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1198 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1199 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1200 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1201 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1202 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1203 } else { 1204 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1205 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1206 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1207 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1208 dri_priv->log2GARTTexGran; 1209 } 1210 1211 i = 0; 1212 screen->extensions[i++] = &driCopySubBufferExtension.base; 1213 screen->extensions[i++] = &driFrameTrackingExtension.base; 1214 screen->extensions[i++] = &driReadDrawableExtension; 1215 1216 if ( screen->irq != 0 ) { 1217 screen->extensions[i++] = &driSwapControlExtension.base; 1218 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1219 } 1220 1221#if !RADEON_COMMON 1222 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1223#endif 1224 1225#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1226 if (IS_R200_CLASS(screen)) 1227 screen->extensions[i++] = &r200AllocateExtension.base; 1228 1229 screen->extensions[i++] = &r200texOffsetExtension.base; 1230#endif 1231 1232#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1233 screen->extensions[i++] = &r300texOffsetExtension.base; 1234#endif 1235 1236#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1237 screen->extensions[i++] = &r600texOffsetExtension.base; 1238#endif 1239 1240 screen->extensions[i++] = NULL; 1241 sPriv->extensions = screen->extensions; 1242 1243 screen->driScreen = sPriv; 1244 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1245 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1246 screen->sarea_priv_offset); 1247 1248 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1249 if (screen->bom == NULL) { 1250 free(screen); 1251 return NULL; 1252 } 1253 1254 return screen; 1255} 1256 1257static radeonScreenPtr 1258radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1259{ 1260 radeonScreenPtr screen; 1261 int i; 1262 int ret; 1263 uint32_t device_id = 0; 1264 uint32_t temp = 0; 1265 1266 /* Allocate the private area */ 1267 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1268 if ( !screen ) { 1269 __driUtilMessage("%s: Could not allocate memory for screen structure", 1270 __FUNCTION__); 1271 fprintf(stderr, "leaving here\n"); 1272 return NULL; 1273 } 1274 1275#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1276 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1277#endif 1278 1279 /* parse information in __driConfigOptions */ 1280 driParseOptionInfo (&screen->optionCache, 1281 __driConfigOptions, __driNConfigOptions); 1282 1283 screen->kernel_mm = 1; 1284 screen->chip_flags = 0; 1285 1286 /* if we have kms we can support all of these */ 1287 screen->drmSupportsCubeMapsR200 = 1; 1288 screen->drmSupportsBlendColor = 1; 1289 screen->drmSupportsTriPerf = 1; 1290 screen->drmSupportsFragShader = 1; 1291 screen->drmSupportsPointSprites = 1; 1292 screen->drmSupportsCubeMapsR100 = 1; 1293 screen->drmSupportsVertexProgram = 1; 1294 screen->irq = 1; 1295 1296 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1297 if (ret) { 1298 FREE( screen ); 1299 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1300 return NULL; 1301 } 1302 1303 ret = radeon_set_screen_flags(screen, device_id); 1304 if (ret == -1) 1305 return NULL; 1306 1307 if (getenv("R300_NO_TCL")) 1308 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1309 1310 if (screen->chip_family <= CHIP_FAMILY_RS200) 1311 screen->chip_flags |= RADEON_CLASS_R100; 1312 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1313 screen->chip_flags |= RADEON_CLASS_R200; 1314 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1315 screen->chip_flags |= RADEON_CLASS_R300; 1316 else 1317 screen->chip_flags |= RADEON_CLASS_R600; 1318 1319 if (IS_R300_CLASS(screen)) { 1320 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1321 if (ret) { 1322 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1323 switch (screen->chip_family) { 1324 case CHIP_FAMILY_R300: 1325 case CHIP_FAMILY_R350: 1326 screen->num_gb_pipes = 2; 1327 break; 1328 case CHIP_FAMILY_R420: 1329 case CHIP_FAMILY_R520: 1330 case CHIP_FAMILY_R580: 1331 case CHIP_FAMILY_RV560: 1332 case CHIP_FAMILY_RV570: 1333 screen->num_gb_pipes = 4; 1334 break; 1335 case CHIP_FAMILY_RV350: 1336 case CHIP_FAMILY_RV515: 1337 case CHIP_FAMILY_RV530: 1338 case CHIP_FAMILY_RV410: 1339 default: 1340 screen->num_gb_pipes = 1; 1341 break; 1342 } 1343 } else { 1344 screen->num_gb_pipes = temp; 1345 } 1346 1347 /* pipe overrides */ 1348 switch (device_id) { 1349 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1350 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1351 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1352 screen->num_gb_pipes = 1; 1353 break; 1354 default: 1355 break; 1356 } 1357 1358 } 1359 1360 i = 0; 1361 screen->extensions[i++] = &driCopySubBufferExtension.base; 1362 screen->extensions[i++] = &driFrameTrackingExtension.base; 1363 screen->extensions[i++] = &driReadDrawableExtension; 1364 1365 if ( screen->irq != 0 ) { 1366 screen->extensions[i++] = &driSwapControlExtension.base; 1367 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1368 } 1369 1370#if !RADEON_COMMON 1371 screen->extensions[i++] = &radeonTexBufferExtension.base; 1372#endif 1373 1374#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1375 if (IS_R200_CLASS(screen)) 1376 screen->extensions[i++] = &r200AllocateExtension.base; 1377 1378 screen->extensions[i++] = &r200TexBufferExtension.base; 1379#endif 1380 1381#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1382 screen->extensions[i++] = &r300TexBufferExtension.base; 1383#endif 1384 1385#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1386 screen->extensions[i++] = &r600TexBufferExtension.base; 1387#endif 1388 1389 screen->extensions[i++] = NULL; 1390 sPriv->extensions = screen->extensions; 1391 1392 screen->driScreen = sPriv; 1393 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1394 if (screen->bom == NULL) { 1395 free(screen); 1396 return NULL; 1397 } 1398 return screen; 1399} 1400 1401/* Destroy the device specific screen private data struct. 1402 */ 1403static void 1404radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1405{ 1406 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1407 1408 if (!screen) 1409 return; 1410 1411 if (screen->kernel_mm) { 1412#ifdef RADEON_BO_TRACK 1413 radeon_tracker_print(&screen->bom->tracker, stderr); 1414#endif 1415 radeon_bo_manager_gem_dtor(screen->bom); 1416 } else { 1417 radeon_bo_manager_legacy_dtor(screen->bom); 1418 1419 if ( screen->gartTextures.map ) { 1420 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1421 } 1422 drmUnmapBufs( screen->buffers ); 1423 drmUnmap( screen->status.map, screen->status.size ); 1424 drmUnmap( screen->mmio.map, screen->mmio.size ); 1425 } 1426 1427 /* free all option information */ 1428 driDestroyOptionInfo (&screen->optionCache); 1429 1430 FREE( screen ); 1431 sPriv->private = NULL; 1432} 1433 1434 1435/* Initialize the driver specific screen private data. 1436 */ 1437static GLboolean 1438radeonInitDriver( __DRIscreenPrivate *sPriv ) 1439{ 1440 if (sPriv->dri2.enabled) { 1441 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1442 } else { 1443 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1444 } 1445 if ( !sPriv->private ) { 1446 radeonDestroyScreen( sPriv ); 1447 return GL_FALSE; 1448 } 1449 1450 return GL_TRUE; 1451} 1452 1453 1454 1455/** 1456 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1457 * 1458 * \todo This function (and its interface) will need to be updated to support 1459 * pbuffers. 1460 */ 1461static GLboolean 1462radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1463 __DRIdrawablePrivate *driDrawPriv, 1464 const __GLcontextModes *mesaVis, 1465 GLboolean isPixmap ) 1466{ 1467 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1468 1469 const GLboolean swDepth = GL_FALSE; 1470 const GLboolean swAlpha = GL_FALSE; 1471 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1472 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1473 mesaVis->depthBits != 24; 1474 GLenum rgbFormat; 1475 struct radeon_framebuffer *rfb; 1476 1477 if (isPixmap) 1478 return GL_FALSE; /* not implemented */ 1479 1480 rfb = CALLOC_STRUCT(radeon_framebuffer); 1481 if (!rfb) 1482 return GL_FALSE; 1483 1484 _mesa_initialize_framebuffer(&rfb->base, mesaVis); 1485 1486 if (mesaVis->redBits == 5) 1487 rgbFormat = GL_RGB5; 1488 else if (mesaVis->alphaBits == 0) 1489 rgbFormat = GL_RGB8; 1490 else 1491 rgbFormat = GL_RGBA8; 1492 1493 /* front color renderbuffer */ 1494 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1495 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1496 rfb->color_rb[0]->has_surface = 1; 1497 1498 /* back color renderbuffer */ 1499 if (mesaVis->doubleBufferMode) { 1500 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1501 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1502 rfb->color_rb[1]->has_surface = 1; 1503 } 1504 1505 if (mesaVis->depthBits == 24) { 1506 if (mesaVis->stencilBits == 8) { 1507 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); 1508 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1509 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1510 depthStencilRb->has_surface = screen->depthHasSurface; 1511 } else { 1512 /* depth renderbuffer */ 1513 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); 1514 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1515 depth->has_surface = screen->depthHasSurface; 1516 } 1517 } else if (mesaVis->depthBits == 16) { 1518 /* just 16-bit depth buffer, no hw stencil */ 1519 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); 1520 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1521 depth->has_surface = screen->depthHasSurface; 1522 } 1523 1524 _mesa_add_soft_renderbuffers(&rfb->base, 1525 GL_FALSE, /* color */ 1526 swDepth, 1527 swStencil, 1528 swAccum, 1529 swAlpha, 1530 GL_FALSE /* aux */); 1531 driDrawPriv->driverPrivate = (void *) rfb; 1532 1533 return (driDrawPriv->driverPrivate != NULL); 1534} 1535 1536 1537static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1538{ 1539 struct radeon_renderbuffer *rb; 1540 1541 rb = rfb->color_rb[0]; 1542 if (rb && rb->bo) { 1543 radeon_bo_unref(rb->bo); 1544 rb->bo = NULL; 1545 } 1546 rb = rfb->color_rb[1]; 1547 if (rb && rb->bo) { 1548 radeon_bo_unref(rb->bo); 1549 rb->bo = NULL; 1550 } 1551 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1552 if (rb && rb->bo) { 1553 radeon_bo_unref(rb->bo); 1554 rb->bo = NULL; 1555 } 1556} 1557 1558void 1559radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1560{ 1561 struct radeon_framebuffer *rfb; 1562 if (!driDrawPriv) 1563 return; 1564 1565 rfb = (void*)driDrawPriv->driverPrivate; 1566 if (!rfb) 1567 return; 1568 radeon_cleanup_renderbuffers(rfb); 1569 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1570} 1571 1572/** 1573 * Choose the appropriate CreateContext function based on the chipset. 1574 * Eventually, all drivers will go through this process. 1575 */ 1576static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1577 __DRIcontextPrivate * driContextPriv, 1578 void *sharedContextPriv) 1579{ 1580 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1581 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1582#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1583 if (IS_R600_CLASS(screen)) 1584 return r600CreateContext(glVisual, driContextPriv, sharedContextPriv); 1585#endif 1586 1587#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1588 if (IS_R300_CLASS(screen)) 1589 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1590#endif 1591 1592#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1593 if (IS_R200_CLASS(screen)) 1594 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); 1595#endif 1596 1597#if !RADEON_COMMON 1598 (void)screen; 1599 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); 1600#endif 1601 return GL_FALSE; 1602} 1603 1604 1605/** 1606 * This is the driver specific part of the createNewScreen entry point. 1607 * 1608 * \todo maybe fold this into intelInitDriver 1609 * 1610 * \return the __GLcontextModes supported by this driver 1611 */ 1612static const __DRIconfig ** 1613radeonInitScreen(__DRIscreenPrivate *psp) 1614{ 1615#if !RADEON_COMMON 1616 static const char *driver_name = "Radeon"; 1617 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1618 static const __DRIversion dri_expected = { 4, 0, 0 }; 1619 static const __DRIversion drm_expected = { 1, 6, 0 }; 1620#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1621 static const char *driver_name = "R200"; 1622 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1623 static const __DRIversion dri_expected = { 4, 0, 0 }; 1624 static const __DRIversion drm_expected = { 1, 6, 0 }; 1625#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1626 static const char *driver_name = "R300"; 1627 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1628 static const __DRIversion dri_expected = { 4, 0, 0 }; 1629 static const __DRIversion drm_expected = { 1, 24, 0 }; 1630#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1631 static const char *driver_name = "R600"; 1632 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1633 static const __DRIversion dri_expected = { 4, 0, 0 }; 1634 static const __DRIversion drm_expected = { 1, 24, 0 }; 1635#endif 1636 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1637 1638 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1639 &psp->dri_version, & dri_expected, 1640 &psp->ddx_version, & ddx_expected, 1641 &psp->drm_version, & drm_expected ) ) { 1642 return NULL; 1643 } 1644 1645 /* Calling driInitExtensions here, with a NULL context pointer, 1646 * does not actually enable the extensions. It just makes sure 1647 * that all the dispatch offsets for all the extensions that 1648 * *might* be enables are known. This is needed because the 1649 * dispatch offsets need to be known when _mesa_context_create 1650 * is called, but we can't enable the extensions until we have a 1651 * context pointer. 1652 * 1653 * Hello chicken. Hello egg. How are you two today? 1654 */ 1655 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1656#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1657 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1658 driInitSingleExtension( NULL, ARB_vp_extension ); 1659 driInitSingleExtension( NULL, NV_vp_extension ); 1660 driInitSingleExtension( NULL, ATI_fs_extension ); 1661 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1662#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 1663 driInitSingleExtension( NULL, gl_20_extension ); 1664#endif 1665 1666 if (!radeonInitDriver(psp)) 1667 return NULL; 1668 1669 /* for now fill in all modes */ 1670 return radeonFillInModes( psp, 1671 dri_priv->bpp, 1672 (dri_priv->bpp == 16) ? 16 : 24, 1673 (dri_priv->bpp == 16) ? 0 : 8, 1); 1674} 1675#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1676 1677/** 1678 * This is the driver specific part of the createNewScreen entry point. 1679 * Called when using DRI2. 1680 * 1681 * \return the __GLcontextModes supported by this driver 1682 */ 1683static const 1684__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1685{ 1686 GLenum fb_format[3]; 1687 GLenum fb_type[3]; 1688 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1689 * support pageflipping at all. 1690 */ 1691 static const GLenum back_buffer_modes[] = { 1692 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1693 }; 1694 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1695 int color; 1696 __DRIconfig **configs = NULL; 1697 1698 /* Calling driInitExtensions here, with a NULL context pointer, 1699 * does not actually enable the extensions. It just makes sure 1700 * that all the dispatch offsets for all the extensions that 1701 * *might* be enables are known. This is needed because the 1702 * dispatch offsets need to be known when _mesa_context_create 1703 * is called, but we can't enable the extensions until we have a 1704 * context pointer. 1705 * 1706 * Hello chicken. Hello egg. How are you two today? 1707 */ 1708 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1709 driInitExtensions( NULL, mm_extensions, GL_FALSE ); 1710#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1711 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1712 driInitSingleExtension( NULL, ARB_vp_extension ); 1713 driInitSingleExtension( NULL, NV_vp_extension ); 1714 driInitSingleExtension( NULL, ATI_fs_extension ); 1715 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1716#endif 1717 1718 if (!radeonInitDriver(psp)) { 1719 return NULL; 1720 } 1721 depth_bits[0] = 0; 1722 stencil_bits[0] = 0; 1723 depth_bits[1] = 16; 1724 stencil_bits[1] = 0; 1725 depth_bits[2] = 24; 1726 stencil_bits[2] = 0; 1727 depth_bits[3] = 24; 1728 stencil_bits[3] = 8; 1729 1730 msaa_samples_array[0] = 0; 1731 1732 fb_format[0] = GL_RGB; 1733 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1734 1735 fb_format[1] = GL_BGR; 1736 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1737 1738 fb_format[2] = GL_BGRA; 1739 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1740 1741 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1742 __DRIconfig **new_configs; 1743 1744 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1745 depth_bits, 1746 stencil_bits, 1747 ARRAY_SIZE(depth_bits), 1748 back_buffer_modes, 1749 ARRAY_SIZE(back_buffer_modes), 1750 msaa_samples_array, 1751 ARRAY_SIZE(msaa_samples_array)); 1752 if (configs == NULL) 1753 configs = new_configs; 1754 else 1755 configs = driConcatConfigs(configs, new_configs); 1756 } 1757 1758 if (configs == NULL) { 1759 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1760 __LINE__); 1761 return NULL; 1762 } 1763 1764 return (const __DRIconfig **)configs; 1765} 1766 1767/** 1768 * Get information about previous buffer swaps. 1769 */ 1770static int 1771getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1772{ 1773 struct radeon_framebuffer *rfb; 1774 1775 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1776 || (dPriv->driContextPriv->driverPrivate == NULL) 1777 || (sInfo == NULL) ) { 1778 return -1; 1779 } 1780 1781 rfb = dPriv->driverPrivate; 1782 sInfo->swap_count = rfb->swap_count; 1783 sInfo->swap_ust = rfb->swap_ust; 1784 sInfo->swap_missed_count = rfb->swap_missed_count; 1785 1786 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1787 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1788 : 0.0; 1789 1790 return 0; 1791} 1792 1793const struct __DriverAPIRec driDriverAPI = { 1794 .InitScreen = radeonInitScreen, 1795 .DestroyScreen = radeonDestroyScreen, 1796 .CreateContext = radeonCreateContext, 1797 .DestroyContext = radeonDestroyContext, 1798 .CreateBuffer = radeonCreateBuffer, 1799 .DestroyBuffer = radeonDestroyBuffer, 1800 .SwapBuffers = radeonSwapBuffers, 1801 .MakeCurrent = radeonMakeCurrent, 1802 .UnbindContext = radeonUnbindContext, 1803 .GetSwapInfo = getSwapInfo, 1804 .GetDrawableMSC = driDrawableGetMSC32, 1805 .WaitForMSC = driWaitForMSC32, 1806 .WaitForSBC = NULL, 1807 .SwapBuffersMSC = NULL, 1808 .CopySubBuffer = radeonCopySubBuffer, 1809 /* DRI2 */ 1810 .InitScreen2 = radeonInitScreen2, 1811}; 1812 1813