15df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * All Rights Reserved. 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Permission is hereby granted, free of charge, to any person obtaining a 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * copy of this software and associated documentation files (the "Software"), 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * to deal in the Software without restriction, including without limitation 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * on the rights to use, copy, modify, merge, publish, distribute, sub 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * license, and/or sell copies of the Software, and to permit persons to whom 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * the Software is furnished to do so, subject to the following conditions: 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * The above copyright notice and this permission notice (including the next 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * paragraph) shall be included in all copies or substantial portions of the 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Software. 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * OTHER DEALINGS IN THE SOFTWARE. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Authors: 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Gareth Hughes <gareth@valinux.com> 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Keith Whitwell <keith@tungstengraphics.com> 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 30ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/glheader.h" 31ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/imports.h" 32ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/api_arrayelt.h" 335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "swrast/swrast.h" 3580c88304fc9d09531b2530b74973821e47b46753Keith Whitwell#include "vbo/vbo.h" 365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "tnl/t_pipeline.h" 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "swrast_setup/swrast_setup.h" 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_context.h" 403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#include "radeon_mipmap_tree.h" 415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_ioctl.h" 425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_state.h" 43674835f184b37ad378ce2e35f1a8326af0facc77Dave Airlie#include "radeon_queryobj.h" 445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#include "../r200/r200_reg.h" 463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4799ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane#include "xmlpool.h" 4899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie * 1.3 cmdbuffers allow all previous state to be updated as well as 513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie * the tcl scalar and vector areas. 523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie */ 533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic struct { 543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int start; 553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int len; 563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie const char *name; 573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} packet[RADEON_MAX_STATE_PACKETS] = { 583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 643fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 653fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 763fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 773fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 943fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 1003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 1013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 1023fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 1033fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 1043fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 1053fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 1063fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 1073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 1083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 1093fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 1103fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 1113fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 1123fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 1133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 1143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 1153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 1163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 1173fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 1183fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 1193fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 1203fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 1213fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 1223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 1233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 1243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 1253fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 1263fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 1273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 1283fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 1293fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 1303fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 1313fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 1323fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 1333fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 1343fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 1353fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 1363fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 1373fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 1383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 1393fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 1403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 1413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 1423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 1433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 1443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 1453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 1463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 1473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 1483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 1493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 1503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 1513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 1523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 1533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 1543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 1553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 1563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie}; 1573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 1585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ============================================================= 1595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * State initialization 1605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 1613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic int cmdpkt( r100ContextPtr rmesa, int id ) 1625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 1630973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt return CP_PACKET0(packet[id].start, packet[id].len - 1); 1645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int cmdvec( int offset, int stride, int count ) 1675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 168ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t h; 1695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.i = 0; 1705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.cmd_type = RADEON_CMD_VECTORS; 1715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.offset = offset; 1725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.stride = stride; 1735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.count = count; 1745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return h.i; 1755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int cmdscl( int offset, int stride, int count ) 1785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 179ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t h; 1805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.i = 0; 1815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.cmd_type = RADEON_CMD_SCALARS; 1825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.offset = offset; 1835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.stride = stride; 1845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.count = count; 1855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return h.i; 1865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 188d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen#define CHECK( NM, FLAG, ADD ) \ 189f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 190b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie{ \ 191d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen return FLAG ? atom->cmd_size + (ADD) : 0; \ 1925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 194d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen#define TCL_CHECK( NM, FLAG, ADD ) \ 195f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 1965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ \ 1974637235183b80963536f2364e4d50fcb894886ddDave Airlie r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 198d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 1995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 202d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( always, GL_TRUE, 0 ) 203d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( always_add2, GL_TRUE, 2 ) 204ccde2768380efbdde467cc37e1a248c447f46d20Pauli NieminenCHECK( always_add4, GL_TRUE, 4 ) 205fd7fcfcc2dffb73ac3159a04ccd164b527c11a8fDave AirlieCHECK( tex0_mm, GL_TRUE, 3 ) 206fd7fcfcc2dffb73ac3159a04ccd164b527c11a8fDave AirlieCHECK( tex1_mm, GL_TRUE, 3 ) 207247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ 208fd7fcfcc2dffb73ac3159a04ccd164b527c11a8fDave AirlieCHECK( tex2_mm, GL_TRUE, 3 ) 209d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 210d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 211d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE ) 212d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( fog_add4, ctx->Fog.Enabled, 4 ) 213d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_add4, GL_TRUE, 4 ) 214d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._ReallyEnabled, 4 ) 215d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._ReallyEnabled, 4 ) 216d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._ReallyEnabled, 4 ) 217d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) 218d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) 219d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 ) 220d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 ) 221d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 ) 222d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 ) 223d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 ) 224d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 ) 225d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 ) 226d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 ) 227d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 ) 228d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 ) 229d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 ) 230d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 ) 231d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 ) 232d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 ) 233d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 ) 234d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenTCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 ) 235d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 236d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 237d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 238d1a0ece9077b3de49c293a04c220b995424cef28Pauli NieminenCHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 ) 2395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#define OUT_VEC(hdr, data) do { \ 2413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie drm_radeon_cmd_header_t h; \ 2423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.i = hdr; \ 2433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 2443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(0); \ 2453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 2463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 2473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 2483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((data), h.vectors.count); \ 2493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } while(0) 2503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#define OUT_SCL(hdr, data) do { \ 2523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie drm_radeon_cmd_header_t h; \ 2533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.i = hdr; \ 2543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 2553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 2563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 2573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((data), h.scalars.count); \ 2583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } while(0) 2593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 260f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 2613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 2623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 2633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 264d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords = atom->check(ctx, atom); 2656d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 2663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 2673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_SCL(atom->cmd[0], atom->cmd+1); 2683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 2693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 2703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 272f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 2733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 2743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 2753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 276d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords = atom->check(ctx, atom); 2773fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 2793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_VEC(atom->cmd[0], atom->cmd+1); 2803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 2813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 2823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2836d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 284f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 2856d7164705b933c754dddea6015b653a3bacc75bfDave Airlie{ 2866d7164705b933c754dddea6015b653a3bacc75bfDave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 2876d7164705b933c754dddea6015b653a3bacc75bfDave Airlie BATCH_LOCALS(&r100->radeon); 288d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords = atom->check(ctx, atom); 2896d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 2906d7164705b933c754dddea6015b653a3bacc75bfDave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 2916d7164705b933c754dddea6015b653a3bacc75bfDave Airlie OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); 2926d7164705b933c754dddea6015b653a3bacc75bfDave Airlie OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); 2936d7164705b933c754dddea6015b653a3bacc75bfDave Airlie END_BATCH(); 2946d7164705b933c754dddea6015b653a3bacc75bfDave Airlie} 2956d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 296f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) 297d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen{ 298d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen r100ContextPtr r100 = R100_CONTEXT(ctx); 299d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen struct radeon_renderbuffer *rrb, *drb; 300d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords; 301d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 302d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen rrb = radeon_get_colorbuffer(&r100->radeon); 303d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen if (!rrb || !rrb->bo) { 304d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen return 0; 305d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen } 306d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 307d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen drb = radeon_get_depthbuffer(&r100->radeon); 308d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 309d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen dwords = 10; 310d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen if (drb) 311d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen dwords += 6; 312d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen if (rrb) 313d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen dwords += 8; 314d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 315d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen return dwords; 316d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen} 317d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen 318f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 3193fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 3203fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 3213fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 3223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie struct radeon_renderbuffer *rrb, *drb; 3233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t cbpitch = 0; 3243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t zbpitch = 0; 325d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords = atom->check(ctx, atom); 326925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie uint32_t depth_fmt; 3273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 328925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie rrb = radeon_get_colorbuffer(&r100->radeon); 329925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie if (!rrb || !rrb->bo) { 330925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie fprintf(stderr, "no rrb\n"); 331925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie return; 3323fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 333925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie 334925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 335925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie if (rrb->cpp == 4) 336925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 337c080202db5363a18a759a9a7c82b40ac558c8abeBrian Paul else switch (rrb->base.Base.Format) { 33845e76d2665b38ba3787548310efc59e969124c01Brian Paul case MESA_FORMAT_RGB565: 339925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 34033f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer break; 34145e76d2665b38ba3787548310efc59e969124c01Brian Paul case MESA_FORMAT_ARGB4444: 34233f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; 34333f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer break; 34445e76d2665b38ba3787548310efc59e969124c01Brian Paul case MESA_FORMAT_ARGB1555: 34533f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; 34633f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer break; 34745e76d2665b38ba3787548310efc59e969124c01Brian Paul default: 34845e76d2665b38ba3787548310efc59e969124c01Brian Paul _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); 34933f56b4612e506999a2be8391ba82c0174afa1b3Michel Dänzer } 350925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie 351925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie cbpitch = (rrb->pitch / rrb->cpp); 352925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 3533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cbpitch |= R200_COLOR_TILE_ENABLE; 3545c666bdfdb7681c2250b801ff286c4837ea36893Dave Airlie if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 3555c666bdfdb7681c2250b801ff286c4837ea36893Dave Airlie cbpitch |= RADEON_COLOR_MICROTILE_ENABLE; 3563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 357925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie drb = radeon_get_depthbuffer(&r100->radeon); 358925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie if (drb) { 3593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie zbpitch = (drb->pitch / drb->cpp); 360925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie if (drb->cpp == 4) 361925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 362925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie else 363925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 364925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 365925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 366925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie 367925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie } 3686d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 3693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 3703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie /* In the CS case we need to split this up */ 3723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 3733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((atom->cmd + 1), 4); 3743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (drb) { 3763fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 37726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 3783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 3803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(zbpitch); 3813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 3843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 3853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 3863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 3873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 3883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb) { 3903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 391f7bab47e6c7cf877acf6d9bb85453851e5aa7f19Dave Airlie OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); 3923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 3947247446ba81b6bafede9ead750e5b5e81f3f1a10Jerome Glisse OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); 3953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 3983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // OUT_BATCH_TABLE((atom->cmd + 14), 4); 3993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // } 4003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 4028181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse BEGIN_BATCH_NO_AUTOSTATE(4); 4038181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 4048181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse OUT_BATCH(0); 4058181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 4068181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse if (rrb) { 407c080202db5363a18a759a9a7c82b40ac558c8abeBrian Paul OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | 408c080202db5363a18a759a9a7c82b40ac558c8abeBrian Paul ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); 4098181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse } else { 4108181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse OUT_BATCH(0); 4118181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse } 4128181f8fbf9c3d0f60191ee874248b8113b215e30Jerome Glisse END_BATCH(); 4133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 4143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 415f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 4164d2b392a0ac597f8b7f88006746660e8f0fe09eaRoland Scheidegger{ 4174d2b392a0ac597f8b7f88006746660e8f0fe09eaRoland Scheidegger r100ContextPtr r100 = R100_CONTEXT(ctx); 4184d2b392a0ac597f8b7f88006746660e8f0fe09eaRoland Scheidegger BATCH_LOCALS(&r100->radeon); 419d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen uint32_t dwords = atom->check(ctx, atom); 420cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie int i = atom->idx, j; 421cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie radeonTexObj *t = r100->state.texture.unit[i].texobj; 422cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie radeon_mipmap_level *lvl; 4237f65fea95e56fe0dee91ba726358896c9899780aDave Airlie uint32_t base_reg; 424cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 425cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) 426cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 427cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 428cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!t) 429cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 430cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 431cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!t->mt) 432cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 433cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 4347f65fea95e56fe0dee91ba726358896c9899780aDave Airlie switch(i) { 4357f65fea95e56fe0dee91ba726358896c9899780aDave Airlie case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 4367f65fea95e56fe0dee91ba726358896c9899780aDave Airlie case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 4377f65fea95e56fe0dee91ba726358896c9899780aDave Airlie default: 4387f65fea95e56fe0dee91ba726358896c9899780aDave Airlie case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 4397f65fea95e56fe0dee91ba726358896c9899780aDave Airlie }; 440d1a0ece9077b3de49c293a04c220b995424cef28Pauli Nieminen BEGIN_BATCH_NO_AUTOSTATE(dwords); 4417f65fea95e56fe0dee91ba726358896c9899780aDave Airlie OUT_BATCH_TABLE(atom->cmd, 2); 442cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie lvl = &t->mt->levels[0]; 443cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie for (j = 0; j < 5; j++) { 4444d2b392a0ac597f8b7f88006746660e8f0fe09eaRoland Scheidegger OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); 445cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 446a2bd13fec9ac2bd77ee21cb85a636fde80ce0368Dave Airlie RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 447cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie } 448cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie END_BATCH(); 449cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie} 450cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 451f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 45226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie{ 45326d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 45426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie BATCH_LOCALS(&r100->radeon); 45526d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie uint32_t dwords = atom->cmd_size; 45626d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie int i = atom->idx; 45726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie radeonTexObj *t = r100->state.texture.unit[i].texobj; 45826d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie radeon_mipmap_level *lvl; 45926d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie int hastexture = 1; 46026d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie 46126d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if (!t) 46226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie hastexture = 0; 46326d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie else { 46426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if (!t->mt && !t->bo) 46526d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie hastexture = 0; 46626d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } 46726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie dwords += 1; 46826d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if (hastexture) 46926d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie dwords += 2; 47026d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie else 47126d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie dwords -= 2; 47226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 47326d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie 47426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1)); 47526d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH_TABLE((atom->cmd + 1), 2); 47626d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie 47726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if (hastexture) { 47826d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); 479924bf0d8d3db28941efa97911bdcdd01a3f33b7cDave Airlie if (t->mt && !t->image_override) { 48026d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { 48193eb2ab8c395f81e40fa298d78805bb2c777f891Maciej Cencora lvl = &t->mt->levels[t->minLod]; 48226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, 48326d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 48426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } else { 48593eb2ab8c395f81e40fa298d78805bb2c777f891Maciej Cencora OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), 48626d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 48726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } 48826d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } else { 48926d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie if (t->bo) 49026d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 49126d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 49226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } 49326d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } 49426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie 49526d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1)); 49626d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH_TABLE((atom->cmd+4), 2); 49726d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0)); 49826d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR])); 49926d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie END_BATCH(); 50026d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie} 50126d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie 5025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Initialize the context's hardware state. 5035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5044637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonInitState( r100ContextPtr rmesa ) 5055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 506f9995b30756140724f41daf963fa06167912be7fKristian Høgsberg struct gl_context *ctx = rmesa->radeon.glCtx; 507925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie GLuint i; 5085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5094637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.Fallback = 0; 5105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5121090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.max_state_size = 0; 5135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 514ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ 5155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul do { \ 5165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.cmd_size = SZ; \ 5174637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 518b1df5ed6db4d79de895e37bcdd12dfbaae7bd4f6Dave Airlie rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 519ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.name = NM; \ 5205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.is_tcl = FLAG; \ 5215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.check = check_##CHK; \ 522ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.dirty = GL_TRUE; \ 523ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.idx = IDX; \ 5241090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 5255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } while (0) 526ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie 527ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 528ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) 529ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie 5305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Allocate state buffers: 5315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 532ccde2768380efbdde467cc37e1a248c447f46d20Pauli Nieminen ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 ); 5330973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.ctx.emit = ctx_emit_cs; 5340973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.ctx.check = check_always_ctx; 5355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 5365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 5375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 5385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 5395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 5405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 5415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 5425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 5430973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 5440973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 ); 5450973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 ); 5460973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 5470973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); 5480973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); 5490973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2); 5500973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 5510973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 ); 5520973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 5530973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 5540973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 5550973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 ); 5560973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 ); 5570973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); 5580973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 ); 5590973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 ); 5600973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 ); 5610973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 ); 5620973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 5630973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 ); 5640973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 5650973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 5660973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 5670973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 5680973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 5690973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 5700973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 ); 5713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 57226d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie for (i = 0; i < 3; i++) { 5730973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.tex[i].emit = tex_emit_cs; 57426d0172a5bc5b733e839e3ccb8d497cab2bcce98Dave Airlie } 57556d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); 57656d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); 57756d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); 57856d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie for (i = 0; i < 3; i++) 57956d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie rmesa->hw.cube[i].emit = cube_emit_cs; 58056d30bb00d40cd391d7a469604792a27ddcc459cDave Airlie 581ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); 582ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); 583ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); 5845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5855562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt radeonSetUpAtomList( rmesa ); 5865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Fill in the packet headers: 5885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 5903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 5913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 5923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 5933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 5943fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 5953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 5963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 5973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS); 5983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 5993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0); 6003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0); 6013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1); 6023fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1); 6033fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2); 6043fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2); 6053fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0); 6063fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0); 6073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1); 6083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1); 6093fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2); 6103fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); 6113fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 6123fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 6135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.mtl.cmd[MTL_CMD_0] = 6143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 6153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); 6163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); 6173fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); 6185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_CMD_0] = 6195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 6205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.fog.cmd[FOG_CMD_0] = 6215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 6225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.glt.cmd[GLT_CMD_0] = 6235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 6245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_CMD_0] = 6255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 6265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 62730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger for (i = 0 ; i < 6; i++) { 6285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.mat[i].cmd[MAT_CMD_0] = 6295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 6305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 8; i++) { 6335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lit[i].cmd[LIT_CMD_0] = 6345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 6355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lit[i].cmd[LIT_CMD_1] = 6365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 6375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 6; i++) { 6405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 6415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 6425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6440973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); 6450973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.stp.cmd[STP_DATA_0] = 0; 6460973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); 6477d361537661b93a501c9533271458a41b965ea79Dave Airlie 6480973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.grd.emit = scl_emit; 6490973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.fog.emit = vec_emit; 6500973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.glt.emit = vec_emit; 6510973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.eye.emit = vec_emit; 6520973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt for (i = 0; i < 6; i++) 6530973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.mat[i].emit = vec_emit; 6546d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 6550973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt for (i = 0; i < 8; i++) 6560973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.lit[i].emit = lit_emit; 6576d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 6580973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt for (i = 0; i < 6; i++) 6590973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->hw.ucp[i].emit = vec_emit; 6606d7164705b933c754dddea6015b653a3bacc75bfDave Airlie 6615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->last_ReallyEnabled = -1; 6625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Initial Harware state: 6645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 6665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CHROMA_FUNC_FAIL | 6675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CHROMA_KEY_NEAREST | 6685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SHADOW_FUNC_EQUAL | 66930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger RADEON_SHADOW_PASS_1 /*| 67030daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger RADEON_RIGHT_HAND_CUBE_OGL */); 6715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 6732d61d301171620efe624d83a5457f4094eb49cbaRoland Scheidegger /* this bit unused for vertex fog */ 6745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FOG_USE_DEPTH); 6755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 6775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 6795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SRC_BLEND_GL_ONE | 6805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DST_BLEND_GL_ZERO ); 6815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 682925ea2d9a5096dbad1d82dc1afffb13a650de799Dave Airlie rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS | 6835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_TEST_ALWAYS | 6845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_FAIL_KEEP | 6855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_ZPASS_KEEP | 6865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_ZFAIL_KEEP | 6875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_Z_WRITE_ENABLE); 6885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 689b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger if (rmesa->using_hyperz) { 690b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | 691b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger RADEON_Z_DECOMPRESSION_ENABLE; 6924637235183b80963536f2364e4d50fcb894886ddDave Airlie if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 693b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger /* works for q3, but slight rendering errors with glxgears ? */ 694b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 695b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger /* need this otherwise get lots of lockups with q3 ??? */ 696b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; 697b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 698b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 699b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger 7005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 7015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ANTI_ALIAS_NONE); 7025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 7040cbc25480f3108a9a49277d57ba2b9e2332d3ccdRoland Scheidegger RADEON_ZBLOCK16); 7055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7064637235183b80963536f2364e4d50fcb894886ddDave Airlie switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 70799ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane case DRI_CONF_DITHER_XERRORDIFFRESET: 70899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 70999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane break; 71099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane case DRI_CONF_DITHER_ORDERED: 71199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 71299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane break; 71399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane } 7144637235183b80963536f2364e4d50fcb894886ddDave Airlie if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 71599ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane DRI_CONF_ROUND_ROUND ) 716d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE; 71799ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane else 718d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.color.roundEnable = 0; 7194637235183b80963536f2364e4d50fcb894886ddDave Airlie if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 72099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane DRI_CONF_COLOR_REDUCTION_DITHER ) 72199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 72299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane else 723d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 72499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 7255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 7275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BFACE_SOLID | 7285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FFACE_SOLID | 7295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* RADEON_BADVTX_CULL_DISABLE | */ 7305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FLAT_SHADE_VTX_LAST | 7315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DIFFUSE_SHADE_GOURAUD | 7325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_SHADE_GOURAUD | 7335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SPECULAR_SHADE_GOURAUD | 7345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FOG_SHADE_GOURAUD | 7355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VPORT_XY_XFORM_ENABLE | 7365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VPORT_Z_XFORM_ENABLE | 7375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VTX_PIX_CENTER_OGL | 7385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ROUND_MODE_TRUNC | 7395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ROUND_PREC_8TH_PIX); 7405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 7425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#ifdef MESA_BIG_ENDIAN 7435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VC_32BIT_SWAP; 7445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 7455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VC_NO_SWAP; 7465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 7475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7484637235183b80963536f2364e4d50fcb894886ddDave Airlie if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 7495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 7505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 7515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 7535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 7545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TEX1_W_ROUTING_USE_Q1); 7555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 7585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 7605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 7615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 7625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 7645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 7665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0x00 << RADEON_STENCIL_REF_SHIFT) | 7675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0xff << RADEON_STENCIL_MASK_SHIFT) | 7685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 7695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 7715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 7725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msc.cmd[MSC_RE_MISC] = 7745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 7755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 7765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STIPPLE_BIG_BIT_ORDER); 7775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 7795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 7805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 7815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 7825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 7835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 7845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 7865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 7875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 7885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 7895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 7905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 7915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 7925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 7935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 79499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane /* Initialize the texture offset to the start of the card texture heap */ 795ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 796ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 7975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 7995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 8005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_COLOR_ARG_A_ZERO | 8015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLOR_ARG_B_ZERO | 8025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLOR_ARG_C_CURRENT_COLOR | 8035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BLEND_CTL_ADD | 8045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SCALE_1X | 8055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CLAMP_TX); 8065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 8075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_ALPHA_ARG_A_ZERO | 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_ARG_B_ZERO | 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BLEND_CTL_ADD | 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SCALE_1X | 8125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CLAMP_TX); 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 814247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger 815247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 816247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = 8174637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 818247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = 8194637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 820247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = 8214637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 822247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = 8234637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 824247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = 8254637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 8265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Can only add ST1 at the time of doing some multitex but can keep 8295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * it after that. Errors if DIFFUSE is missing. 8305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 8325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_VTX_Z0 | 8335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TCL_VTX_W0 | 8345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TCL_VTX_PK_DIFFUSE 8355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ); /* need to keep this uptodate */ 8365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 8385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ( RADEON_TCL_COMPUTE_XYZW | 8395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 8405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 8415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 8425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* XXX */ 8455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 8465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 8475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 8485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 8505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 8515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 85230daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | 85330daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); 8545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 8565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_UCP_IN_CLIP_SPACE | 8575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CULL_FRONT_IS_CCW); 8585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 8605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 8625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_SPECULAR_LIGHTS | 8635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DIFFUSE_SPECULAR_COMBINE | 8645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_LOCAL_LIGHT_VEC_GL | 865f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 866f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 867f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 868f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 8695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 8; i++) { 8715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct gl_light *l = &ctx->Light.Light[i]; 8725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum p = GL_LIGHT0 + i; 8735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 8745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 8765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 8775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 8782c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 8792c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 8805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 8815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 8825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 8835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->ConstantAttenuation ); 8845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 8855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->LinearAttenuation ); 8865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 8875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->QuadraticAttenuation ); 8885d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 8895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 8925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Light.Model.Ambient ); 8935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 8955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 6; i++) { 8975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 8985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9002c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 9015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 9025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 9035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 9045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 9052c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 9065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 9085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 9095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 9105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 9115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_X] = 0; 9135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_Y] = 0; 9145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 9155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 9167d361537661b93a501c9533271458a41b965ea79Dave Airlie 9170973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); 9180973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); 9190973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; 9205484428d7267388fde868e64531dcdf98b55fafcDave Airlie 9211090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.all_dirty = GL_TRUE; 92236d3f3e74a809ad346e981805a2f61710d3a380bDave Airlie 9231090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rcommonInitCmdBuf(&rmesa->radeon); 9245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 925