radeon_state_init.c revision cd4e37c8fb7c03e8331a9487d46043eea70fea31
15df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California. 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * All Rights Reserved. 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Permission is hereby granted, free of charge, to any person obtaining a 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * copy of this software and associated documentation files (the "Software"), 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * to deal in the Software without restriction, including without limitation 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * on the rights to use, copy, modify, merge, publish, distribute, sub 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * license, and/or sell copies of the Software, and to permit persons to whom 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * the Software is furnished to do so, subject to the following conditions: 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * The above copyright notice and this permission notice (including the next 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * paragraph) shall be included in all copies or substantial portions of the 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Software. 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * OTHER DEALINGS IN THE SOFTWARE. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Authors: 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Gareth Hughes <gareth@valinux.com> 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Keith Whitwell <keith@tungstengraphics.com> 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 30ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/glheader.h" 31ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/imports.h" 32ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/api_arrayelt.h" 335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "swrast/swrast.h" 3580c88304fc9d09531b2530b74973821e47b46753Keith Whitwell#include "vbo/vbo.h" 365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "tnl/tnl.h" 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "tnl/t_pipeline.h" 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "swrast_setup/swrast_setup.h" 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_context.h" 413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#include "radeon_mipmap_tree.h" 425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_ioctl.h" 435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_state.h" 445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_tcl.h" 455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_tex.h" 465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_swtcl.h" 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#include "../r200/r200_reg.h" 493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 5099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane#include "xmlpool.h" 5199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie * 1.3 cmdbuffers allow all previous state to be updated as well as 543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie * the tcl scalar and vector areas. 553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie */ 563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic struct { 573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int start; 583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int len; 593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie const char *name; 603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} packet[RADEON_MAX_STATE_PACKETS] = { 613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 643fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 653fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 763fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 773fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 943fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 1003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 1013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 1023fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 1033fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 1043fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 1053fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 1063fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 1073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 1083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 1093fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 1103fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 1113fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 1123fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 1133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 1143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 1153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 1163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 1173fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 1183fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 1193fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 1203fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 1213fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 1223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 1233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 1243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 1253fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 1263fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 1273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 1283fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 1293fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 1303fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 1313fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 1323fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 1333fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 1343fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 1353fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 1363fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 1373fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 1383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 1393fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 1403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 1413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 1423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 1433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 1443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 1453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 1463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 1473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 1483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 1493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 1503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 1513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 1523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 1533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 1543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 1553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 1563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 1573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 1583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 1593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie}; 1603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 1615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ============================================================= 1625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * State initialization 1635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 1645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1654637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) 1665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 1675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom *l; 1685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, msg); 1705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, ": "); 1715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1721090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie foreach(l, &rmesa->radeon.hw.atomlist) { 1731090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie if (l->dirty || rmesa->radeon.hw.all_dirty) 1745562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt fprintf(stderr, "%s, ", l->name); 1755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 1765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "\n"); 1785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic int cmdpkt( r100ContextPtr rmesa, int id ) 1815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 182ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t h; 1833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 1843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rmesa->radeon.radeonScreen->kernel_mm) { 1853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie return CP_PACKET0(packet[id].start, packet[id].len - 1); 1863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } else { 1873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.i = 0; 1883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.packet.cmd_type = RADEON_CMD_PACKET; 1893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.packet.packet_id = id; 1903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 1915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return h.i; 1925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int cmdvec( int offset, int stride, int count ) 1955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 196ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t h; 1975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.i = 0; 1985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.cmd_type = RADEON_CMD_VECTORS; 1995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.offset = offset; 2005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.stride = stride; 2015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.vectors.count = count; 2025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return h.i; 2035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int cmdscl( int offset, int stride, int count ) 2065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 207ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t h; 2085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.i = 0; 2095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.cmd_type = RADEON_CMD_SCALARS; 2105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.offset = offset; 2115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.stride = stride; 2125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul h.scalars.count = count; 2135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return h.i; 2145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 216b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie#define CHECK( NM, FLAG ) \ 2174637235183b80963536f2364e4d50fcb894886ddDave Airliestatic int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ 218b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie{ \ 2190c0a55a21158e1f97cf140c0a1c0531c06751873Dave Airlie return FLAG ? atom->cmd_size : 0; \ 2205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_CHECK( NM, FLAG ) \ 2234637235183b80963536f2364e4d50fcb894886ddDave Airliestatic int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ 2245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ \ 2254637235183b80963536f2364e4d50fcb894886ddDave Airlie r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 2260c0a55a21158e1f97cf140c0a1c0531c06751873Dave Airlie return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \ 2275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( always, GL_TRUE ) 231247f3b3e81fffa86c50531070fab573e26ffb452Roland ScheideggerCHECK( never, GL_FALSE ) 2325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 2335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 234247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */ 235247f3b3e81fffa86c50531070fab573e26ffb452Roland ScheideggerCHECK( tex2, ctx->Texture._EnabledUnits ) 236247f3b3e81fffa86c50531070fab573e26ffb452Roland ScheideggerCHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT)) 237247f3b3e81fffa86c50531070fab573e26ffb452Roland ScheideggerCHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT)) 238247f3b3e81fffa86c50531070fab573e26ffb452Roland ScheideggerCHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT)) 2395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( fog, ctx->Fog.Enabled ) 2405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl, GL_TRUE ) 2415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled ) 2425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled ) 24330daa7529331057ecb470efb500152e9c4aa1ae5Roland ScheideggerTCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled ) 2445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lighting, ctx->Light.Enabled ) 2455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled ) 2465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled ) 2475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled ) 2485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled ) 2495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled ) 2505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled ) 2515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled ) 2525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled ) 2535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled ) 2545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) ) 2555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) ) 2565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) ) 2575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) ) 2585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) ) 2595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) ) 2605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled ) 2615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) 2635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) 26430daa7529331057ecb470efb500152e9c4aa1ae5Roland ScheideggerCHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) 2655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#define OUT_VEC(hdr, data) do { \ 2673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie drm_radeon_cmd_header_t h; \ 2683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.i = hdr; \ 2693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 2703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(0); \ 2713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 2723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 2733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 2743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((data), h.vectors.count); \ 2753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } while(0) 2763fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2773fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#define OUT_SCL(hdr, data) do { \ 2783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie drm_radeon_cmd_header_t h; \ 2793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie h.i = hdr; \ 2803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 2813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 2823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 2833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((data), h.scalars.count); \ 2843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } while(0) 2853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) 2873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 2883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 2893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 2903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t dwords = atom->cmd_size; 2913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 2933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_SCL(atom->cmd[0], atom->cmd+1); 2943fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 2953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 2963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) 2993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 3003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 3013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 3023fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t dwords = atom->cmd_size; 3033fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3043fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 3053fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_VEC(atom->cmd[0], atom->cmd+1); 3063fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 3073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 3083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3093fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) 3103fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 3113fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 3123fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 3133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie struct radeon_renderbuffer *rrb; 3143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t cbpitch; 3153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t zbpitch; 3163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t dwords = atom->cmd_size; 3173fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; 3183fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3193fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie /* output the first 7 bytes of context */ 3203fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords + 4); 3213fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE(atom->cmd, 5); 3223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rrb = r100->radeon.state.depth.rrb; 3243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (!rrb) { 3253fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(0); 3263fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(0); 3273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } else { 3283fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie zbpitch = (rrb->pitch / rrb->cpp); 3293fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 3303fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(zbpitch); 3313fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3323fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3333fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 3343fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_CMD_1]); 3353fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 3363fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 3373fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rrb = r100->radeon.state.color.rrb; 3393fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { 3403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 3413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (!rrb || !rrb->bo) { 3433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); 3443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } else { 3453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 3463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_CMD_2]); 3495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (!rrb || !rrb->bo) { 3513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); 3523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } else { 3533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cbpitch = (rrb->pitch / rrb->cpp); 3543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb->cpp == 4) 3553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie ; 3563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie else 3573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie ; 3583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (r100->radeon.sarea->tiling_enabled) 3593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cbpitch |= R200_COLOR_TILE_ENABLE; 3603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(cbpitch); 3613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 3643fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 365cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 3663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) 3673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 3683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 3693fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 3703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie struct radeon_renderbuffer *rrb, *drb; 3713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t cbpitch = 0; 3723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t zbpitch = 0; 3733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t dwords = atom->cmd_size; 3743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate; 3753fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3763fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rrb = r100->radeon.state.color.rrb; 3773fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (r100->radeon.radeonScreen->driScreen->dri2.enabled) { 3783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 3793fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3803fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb) { 3813fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie assert(rrb->bo != NULL); 3823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cbpitch = (rrb->pitch / rrb->cpp); 3833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (r100->radeon.sarea->tiling_enabled) 3843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cbpitch |= R200_COLOR_TILE_ENABLE; 3853fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3863fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3873fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie drb = r100->radeon.state.depth.rrb; 3883fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (drb) 3893fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie zbpitch = (drb->pitch / drb->cpp); 3903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie /* output the first 7 bytes of context */ 3923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 3933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3943fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie /* In the CS case we need to split this up */ 3953fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 3963fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((atom->cmd + 1), 4); 3973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (drb) { 3993fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 4003fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 4013fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4023fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 4033fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(zbpitch); 4043fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 4053fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4063fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 4073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 4083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 4093fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 4103fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 4113fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4123fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb) { 4143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 4153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 4163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 4173fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4183fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb) { 4193fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rrb->cpp == 4) 4203fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie ; 4213fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie else 4223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie ; 4233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 4243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(cbpitch); 4253fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 4263fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 4283fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // OUT_BATCH_TABLE((atom->cmd + 14), 4); 4293fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // } 4303fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4313fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 4323fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 4333fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 434cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airliestatic void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) 435cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie{ 436cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 437cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie BATCH_LOCALS(&r100->radeon); 438cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie uint32_t dwords = atom->cmd_size; 439cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie int i = atom->idx, j; 440cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie radeonTexObj *t = r100->state.texture.unit[i].texobj; 441cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie radeon_mipmap_level *lvl; 442cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 443cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) 444cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 445cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 446cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!t) 447cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 448cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 449cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if (!t->mt) 450cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie return; 451cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 452cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords + 10); 453cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie OUT_BATCH_TABLE(atom->cmd, 3); 454cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie lvl = &t->mt->levels[0]; 455cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie for (j = 0; j < 5; j++) { 456cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 457cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie RADEON_GEM_DOMAIN_VRAM, 0, 0); 458cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie } 459cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie END_BATCH(); 460cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie} 461cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie 4623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airliestatic void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) 4633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie{ 4643fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie r100ContextPtr r100 = R100_CONTEXT(ctx); 4653fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&r100->radeon); 4663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t dwords = atom->cmd_size; 4673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int i = atom->idx; 4683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie radeonTexObj *t = r100->state.texture.unit[i].texobj; 469cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie radeon_mipmap_level *lvl; 4703fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 471639b5fca0c5cea26a9dc393b538508aece16ce6bDave Airlie if (t && t->mt && !t->image_override) 472ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie dwords += 2; 473ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(dwords); 4743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE(atom->cmd, 3); 475639b5fca0c5cea26a9dc393b538508aece16ce6bDave Airlie if (t && t->mt && !t->image_override) { 476cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { 477cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie lvl = &t->mt->levels[0]; 478cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, 479cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie RADEON_GEM_DOMAIN_VRAM, 0, 0); 480cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie } else { 481cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 4823fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_GEM_DOMAIN_VRAM, 0, 0); 483cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie } 4842753dd42fd42a3383d2e74ab231d0b1373a2d46dDave Airlie } else if (!t) { 485ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie /* workaround for old CS mechanism */ 486ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); 487ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie // OUT_BATCH(r100->radeon.radeonScreen); 4882753dd42fd42a3383d2e74ab231d0b1373a2d46dDave Airlie } else if (t->image_override) 4892753dd42fd42a3383d2e74ab231d0b1373a2d46dDave Airlie OUT_BATCH(atom->cmd[4]); 4903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 4913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_TABLE((atom->cmd+4), 5); 4923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 4933fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 4945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Initialize the context's hardware state. 4965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4974637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonInitState( r100ContextPtr rmesa ) 4985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 4994637235183b80963536f2364e4d50fcb894886ddDave Airlie GLcontext *ctx = rmesa->radeon.glCtx; 5005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint color_fmt, depth_fmt, i; 501982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul GLint drawPitch, drawOffset; 5025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5034637235183b80963536f2364e4d50fcb894886ddDave Airlie switch ( rmesa->radeon.radeonScreen->cpp ) { 5045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 2: 5055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_fmt = RADEON_COLOR_FORMAT_RGB565; 5065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 4: 5085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 5095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul default: 5115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); 5125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( -1 ); 5135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 515d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.color.clear = 0x00000000; 5165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul switch ( ctx->Visual.depthBits ) { 5185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 16: 519d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.depth.clear = 0x0000ffff; 520d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff; 5215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 522d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.stencil.clear = 0x00000000; 5235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 24: 525d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.depth.clear = 0x00ffffff; 526d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff; 5275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 528d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.stencil.clear = 0xffff0000; 5295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul default: 5315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "Error: Unsupported depth %d... exiting\n", 5325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Visual.depthBits ); 5335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( -1 ); 5345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Only have hw stencil when depth buffer is 24 bits deep */ 537d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && 5385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Visual.depthBits == 24 ); 5395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5404637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.Fallback = 0; 5415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5424637235183b80963536f2364e4d50fcb894886ddDave Airlie if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) { 5434637235183b80963536f2364e4d50fcb894886ddDave Airlie drawOffset = rmesa->radeon.radeonScreen->backOffset; 5444637235183b80963536f2364e4d50fcb894886ddDave Airlie drawPitch = rmesa->radeon.radeonScreen->backPitch; 5455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else { 5464637235183b80963536f2364e4d50fcb894886ddDave Airlie drawOffset = rmesa->radeon.radeonScreen->frontOffset; 5474637235183b80963536f2364e4d50fcb894886ddDave Airlie drawPitch = rmesa->radeon.radeonScreen->frontPitch; 5485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5501090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.max_state_size = 0; 5515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 552ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie#define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ 5535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul do { \ 5545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.cmd_size = SZ; \ 5554637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 556b1df5ed6db4d79de895e37bcdd12dfbaae7bd4f6Dave Airlie rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 557ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.name = NM; \ 5585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.is_tcl = FLAG; \ 5595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ATOM.check = check_##CHK; \ 560ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.dirty = GL_TRUE; \ 561ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->hw.ATOM.idx = IDX; \ 5621090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 5635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } while (0) 564ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie 565ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ 566ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0) 567ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie 5685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Allocate state buffers: 5695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 ); 5713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (rmesa->radeon.radeonScreen->kernel_mm) 5723fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.emit = ctx_emit_cs; 5733fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie else 5743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.emit = ctx_emit; 5755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 5765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 5775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 5785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 5795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 5805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 5815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); 5825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 ); 5835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 ); 5845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 ); 5855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 ); 5865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); 587ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0); 588ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1); 589ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 ); 5903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 5913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie for (i = 0; i < 3; i++) 5923fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[i].emit = tex_emit; 5934637235183b80963536f2364e4d50fcb894886ddDave Airlie if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100) 594247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger { 595ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); 596ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); 597ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); 598cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie for (i = 0; i < 3; i++) 599cd4e37c8fb7c03e8331a9487d46043eea70fea31Dave Airlie rmesa->hw.cube[i].emit = cube_emit; 600247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger } 601247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger else 602247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger { 603ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 ); 604ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); 605ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); 606247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger } 6075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); 6085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); 6095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); 6105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 ); 6115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 61230daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 ); 6135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); 6145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 6155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); 6165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 ); 6175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 ); 6185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 ); 6195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 ); 6205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 ); 6215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 ); 6225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 ); 6235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 ); 6245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 ); 6255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 ); 6265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); 627ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 ); 628ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 ); 629ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 ); 6305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6315562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt radeonSetUpAtomList( rmesa ); 6325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Fill in the packet headers: 6345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6353fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 6363fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 6373fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 6383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 6393fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 6403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 6413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 6423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 6433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS); 6443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 6453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0); 6463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0); 6473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1); 6483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1); 6493fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2); 6503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2); 6513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0); 6523fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0); 6533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1); 6543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1); 6553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2); 6563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2); 6573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 6583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); 6595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.mtl.cmd[MTL_CMD_0] = 6603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); 6613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0); 6623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1); 6633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2); 6645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_CMD_0] = 6655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 6665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.fog.cmd[FOG_CMD_0] = 6675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 ); 6685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.glt.cmd[GLT_CMD_0] = 6695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 6705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_CMD_0] = 6715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); 6725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 67330daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger for (i = 0 ; i < 6; i++) { 6745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.mat[i].cmd[MAT_CMD_0] = 6755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); 6765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 8; i++) { 6795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lit[i].cmd[LIT_CMD_0] = 6805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 6815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lit[i].cmd[LIT_CMD_1] = 6825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 ); 6835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 6; i++) { 6865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 6875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 ); 6885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->last_ReallyEnabled = -1; 6915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Initial Harware state: 6935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS | 6955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CHROMA_FUNC_FAIL | 6965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CHROMA_KEY_NEAREST | 6975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SHADOW_FUNC_EQUAL | 69830daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger RADEON_SHADOW_PASS_1 /*| 69930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger RADEON_RIGHT_HAND_CUBE_OGL */); 7005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | 7022d61d301171620efe624d83a5457f4094eb49cbaRoland Scheidegger /* this bit unused for vertex fog */ 7035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FOG_USE_DEPTH); 7045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 7065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP | 7085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SRC_BLEND_GL_ONE | 7095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DST_BLEND_GL_ZERO ); 7105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 7124637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; 7135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 7154637235183b80963536f2364e4d50fcb894886ddDave Airlie ((rmesa->radeon.radeonScreen->depthPitch & 7165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DEPTHPITCH_MASK) | 7175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DEPTH_ENDIAN_NO_SWAP); 718b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger 719b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger if (rmesa->using_hyperz) 720b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ; 7215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | 7235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_Z_TEST_LESS | 7245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_TEST_ALWAYS | 7255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_FAIL_KEEP | 7265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_ZPASS_KEEP | 7275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STENCIL_ZFAIL_KEEP | 7285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_Z_WRITE_ENABLE); 7295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 730b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger if (rmesa->using_hyperz) { 731b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | 732b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger RADEON_Z_DECOMPRESSION_ENABLE; 7334637235183b80963536f2364e4d50fcb894886ddDave Airlie if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 734b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger /* works for q3, but slight rendering errors with glxgears ? */ 735b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 736b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger /* need this otherwise get lots of lockups with q3 ??? */ 737b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; 738b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 739b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 740b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger 7415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | 7425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ANTI_ALIAS_NONE); 7435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | 7455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_fmt | 7460cbc25480f3108a9a49277d57ba2b9e2332d3ccdRoland Scheidegger RADEON_ZBLOCK16); 7475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7484637235183b80963536f2364e4d50fcb894886ddDave Airlie switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 74999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane case DRI_CONF_DITHER_XERRORDIFFRESET: 75099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; 75199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane break; 75299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane case DRI_CONF_DITHER_ORDERED: 75399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; 75499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane break; 75599ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane } 7564637235183b80963536f2364e4d50fcb894886ddDave Airlie if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 75799ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane DRI_CONF_ROUND_ROUND ) 758d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE; 75999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane else 760d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->radeon.state.color.roundEnable = 0; 7614637235183b80963536f2364e4d50fcb894886ddDave Airlie if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 76299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane DRI_CONF_COLOR_REDUCTION_DITHER ) 76399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; 76499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane else 765d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 76699ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 767982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + 7684637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->fbLocation) 76999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane & RADEON_COLOROFFSET_MASK); 7705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 771982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & 7725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLORPITCH_MASK) | 7735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLOR_ENDIAN_NO_SWAP); 774982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul 775982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul 776a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ 7774637235183b80963536f2364e4d50fcb894886ddDave Airlie if (rmesa->radeon.sarea->tiling_enabled) { 778a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; 779a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger } 7805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | 7825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BFACE_SOLID | 7835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FFACE_SOLID | 7845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* RADEON_BADVTX_CULL_DISABLE | */ 7855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FLAT_SHADE_VTX_LAST | 7865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DIFFUSE_SHADE_GOURAUD | 7875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_SHADE_GOURAUD | 7885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SPECULAR_SHADE_GOURAUD | 7895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FOG_SHADE_GOURAUD | 7905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VPORT_XY_XFORM_ENABLE | 7915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VPORT_Z_XFORM_ENABLE | 7925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VTX_PIX_CENTER_OGL | 7935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ROUND_MODE_TRUNC | 7945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ROUND_PREC_8TH_PIX); 7955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] = 7975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#ifdef MESA_BIG_ENDIAN 7985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VC_32BIT_SWAP; 7995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 8005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VC_NO_SWAP; 8015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 8025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8034637235183b80963536f2364e4d50fcb894886ddDave Airlie if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 8045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS; 8055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.set.cmd[SET_SE_COORDFMT] = ( 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TEX1_W_ROUTING_USE_Q1); 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 8155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) | 8165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (1 << RADEON_LINE_CURRENT_COUNT_SHIFT)); 8175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 8195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 8215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0x00 << RADEON_STENCIL_REF_SHIFT) | 8225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0xff << RADEON_STENCIL_MASK_SHIFT) | 8235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0xff << RADEON_STENCIL_WRITEMASK_SHIFT)); 8245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY; 8265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 8275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.msc.cmd[MSC_RE_MISC] = 8295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) | 8305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) | 8315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_STIPPLE_BIG_BIT_ORDER); 8325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 8345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 8355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 8365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 8375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 8385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 8395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 8415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL; 8425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 8435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TXFORMAT_ENDIAN_NO_SWAP | 8445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TXFORMAT_PERSPECTIVE_ENABLE | 8455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */ 8465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | 8475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); 8485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 84999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane /* Initialize the texture offset to the start of the card texture heap */ 850ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 851ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 8525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 8545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = 8555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_COLOR_ARG_A_ZERO | 8565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLOR_ARG_B_ZERO | 8575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_COLOR_ARG_C_CURRENT_COLOR | 8585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BLEND_CTL_ADD | 8595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SCALE_1X | 8605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CLAMP_TX); 8615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 8625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_ALPHA_ARG_A_ZERO | 8635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_ARG_B_ZERO | 8645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ALPHA_ARG_C_CURRENT_ALPHA | 8655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_BLEND_CTL_ADD | 8665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_SCALE_1X | 8675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CLAMP_TX); 8685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0; 869247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger 870247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 871247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] = 8724637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 873247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] = 8744637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 875247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] = 8764637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 877247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] = 8784637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 879247f3b3e81fffa86c50531070fab573e26ffb452Roland Scheidegger rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] = 8804637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 8815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Can only add ST1 at the time of doing some multitex but can keep 8845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * it after that. Errors if DIFFUSE is missing. 8855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 8875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_VTX_Z0 | 8885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TCL_VTX_W0 | 8895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_TCL_VTX_PK_DIFFUSE 8905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ); /* need to keep this uptodate */ 8915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = 8935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ( RADEON_TCL_COMPUTE_XYZW | 8945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | 8955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | 8965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); 8975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* XXX */ 9005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 9015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((MODEL << RADEON_MODELVIEW_0_SHIFT) | 9025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT)); 9035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 9055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | 9065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | 90730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | 90830daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); 9095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 9115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_UCP_IN_CLIP_SPACE | 9125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CULL_FRONT_IS_CCW); 9135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 9155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 9175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (RADEON_SPECULAR_LIGHTS | 9185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DIFFUSE_SPECULAR_COMBINE | 9195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_LOCAL_LIGHT_VEC_GL | 920f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) | 921f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) | 922f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) | 923f64f940281f0d716e0ddc641e7ef1728f143d67fRoland Scheidegger (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT)); 9245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 8; i++) { 9265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct gl_light *l = &ctx->Light.Light[i]; 9275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum p = GL_LIGHT0 + i; 9285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 9295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 9315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 9325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 9332c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 9342c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 9355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 9365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 9375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 9385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->ConstantAttenuation ); 9395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 9405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->LinearAttenuation ); 9415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 9425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &l->QuadraticAttenuation ); 9435d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 9445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 9475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Light.Model.Ambient ); 9485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 9505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < 6; i++) { 9525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 9535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9552c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 9565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 9575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 9585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 9595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 9602c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 9615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 9635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 9645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 9655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 9665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_X] = 0; 9685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_Y] = 0; 9695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 9705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 9715562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 9721090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.all_dirty = GL_TRUE; 97336d3f3e74a809ad346e981805a2f61710d3a380bDave Airlie 9741090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rcommonInitCmdBuf(&rmesa->radeon); 9755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 976