radeon_swtcl.c revision 247f3b3e81fffa86c50531070fab573e26ffb452
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Keith Whitwell <keith@tungstengraphics.com> 34 */ 35 36#include "glheader.h" 37#include "mtypes.h" 38#include "colormac.h" 39#include "enums.h" 40#include "imports.h" 41#include "macros.h" 42 43#include "swrast_setup/swrast_setup.h" 44#include "math/m_translate.h" 45#include "tnl/tnl.h" 46#include "tnl/t_context.h" 47#include "tnl/t_pipeline.h" 48#include "tnl/t_vtx_api.h" /* for _tnl_FlushVertices */ 49 50#include "radeon_context.h" 51#include "radeon_ioctl.h" 52#include "radeon_state.h" 53#include "radeon_swtcl.h" 54#include "radeon_tcl.h" 55 56 57static void flush_last_swtcl_prim( radeonContextPtr rmesa ); 58 59/* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */ 60/* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */ 61#define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */ 62 63/*********************************************************************** 64 * Initialization 65 ***********************************************************************/ 66 67#define EMIT_ATTR( ATTR, STYLE, F0 ) \ 68do { \ 69 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ 70 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ 71 rmesa->swtcl.vertex_attr_count++; \ 72 fmt_0 |= F0; \ 73} while (0) 74 75#define EMIT_PAD( N ) \ 76do { \ 77 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ 78 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ 79 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ 80 rmesa->swtcl.vertex_attr_count++; \ 81} while (0) 82 83static GLuint radeon_cp_vc_frmts[3][2] = 84{ 85 { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 }, 86 { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 }, 87 { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 }, 88}; 89 90static void radeonSetVertexFormat( GLcontext *ctx ) 91{ 92 radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); 93 TNLcontext *tnl = TNL_CONTEXT(ctx); 94 struct vertex_buffer *VB = &tnl->vb; 95 GLuint index = tnl->render_inputs; 96 int fmt_0 = 0; 97 int offset = 0; 98 99 100 /* Important: 101 */ 102 if ( VB->NdcPtr != NULL ) { 103 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; 104 } 105 else { 106 VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; 107 } 108 109 assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); 110 rmesa->swtcl.vertex_attr_count = 0; 111 112 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to 113 * build up a hardware vertex. 114 */ 115 if ( !rmesa->swtcl.needproj || 116 (index & _TNL_BITS_TEX_ANY)) { /* for projtex */ 117 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, 118 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 ); 119 offset = 4; 120 } 121 else { 122 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F, 123 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z ); 124 offset = 3; 125 } 126 127 rmesa->swtcl.coloroffset = offset; 128#if MESA_LITTLE_ENDIAN 129 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, 130 RADEON_CP_VC_FRMT_PKCOLOR ); 131#else 132 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, 133 RADEON_CP_VC_FRMT_PKCOLOR ); 134#endif 135 offset += 1; 136 137 rmesa->swtcl.specoffset = 0; 138 if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) { 139 140#if MESA_LITTLE_ENDIAN 141 if (index & _TNL_BIT_COLOR1) { 142 rmesa->swtcl.specoffset = offset; 143 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, 144 RADEON_CP_VC_FRMT_PKSPEC ); 145 } 146 else { 147 EMIT_PAD( 3 ); 148 } 149 150 if (index & _TNL_BIT_FOG) { 151 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, 152 RADEON_CP_VC_FRMT_PKSPEC ); 153 } 154 else { 155 EMIT_PAD( 1 ); 156 } 157#else 158 if (index & _TNL_BIT_FOG) { 159 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, 160 RADEON_CP_VC_FRMT_PKSPEC ); 161 } 162 else { 163 EMIT_PAD( 1 ); 164 } 165 166 if (index & _TNL_BIT_COLOR1) { 167 rmesa->swtcl.specoffset = offset; 168 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, 169 RADEON_CP_VC_FRMT_PKSPEC ); 170 } 171 else { 172 EMIT_PAD( 3 ); 173 } 174#endif 175 } 176 177 if (index & _TNL_BITS_TEX_ANY) { 178 int i; 179 180 for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { 181 if (index & _TNL_BIT_TEX(i)) { 182 GLuint sz = VB->TexCoordPtr[i]->size; 183 184 switch (sz) { 185 case 1: 186 case 2: 187 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F, 188 radeon_cp_vc_frmts[i][0] ); 189 break; 190 case 3: 191 case 4: 192 if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) { 193 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F, 194 radeon_cp_vc_frmts[i][1] ); 195 } else { 196 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW, 197 radeon_cp_vc_frmts[i][1] ); 198 } 199 break; 200 default: 201 continue; 202 }; 203 } 204 } 205 } 206 207 if ( rmesa->tnl_index != index || 208 fmt_0 != rmesa->swtcl.vertex_format) { 209 RADEON_NEWPRIM(rmesa); 210 rmesa->swtcl.vertex_format = fmt_0; 211 rmesa->swtcl.vertex_size = 212 _tnl_install_attrs( ctx, 213 rmesa->swtcl.vertex_attrs, 214 rmesa->swtcl.vertex_attr_count, 215 NULL, 0 ); 216 rmesa->swtcl.vertex_size /= 4; 217 rmesa->tnl_index = index; 218 if (RADEON_DEBUG & DEBUG_VERTS) 219 fprintf( stderr, "%s: vertex_size= %d floats\n", 220 __FUNCTION__, rmesa->swtcl.vertex_size); 221 } 222} 223 224 225static void radeonRenderStart( GLcontext *ctx ) 226{ 227 radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); 228 229 radeonSetVertexFormat( ctx ); 230 231 if (rmesa->dma.flush != 0 && 232 rmesa->dma.flush != flush_last_swtcl_prim) 233 rmesa->dma.flush( rmesa ); 234} 235 236 237/** 238 * Set vertex state for SW TCL. The primary purpose of this function is to 239 * determine in advance whether or not the hardware can / should do the 240 * projection divide or Mesa should do it. 241 */ 242void radeonChooseVertexState( GLcontext *ctx ) 243{ 244 radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); 245 TNLcontext *tnl = TNL_CONTEXT(ctx); 246 247 GLuint se_coord_fmt; 248 249 /* We must ensure that we don't do _tnl_need_projected_coords while in a 250 * rasterization fallback. As this function will be called again when we 251 * leave a rasterization fallback, we can just skip it for now. 252 */ 253 if (rmesa->Fallback != 0) 254 return; 255 256 /* HW perspective divide is a win, but tiny vertex formats are a 257 * bigger one. 258 */ 259 260 if ( ((tnl->render_inputs & (_TNL_BITS_TEX_ANY|_TNL_BIT_COLOR1) ) == 0) 261 || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) { 262 rmesa->swtcl.needproj = GL_TRUE; 263 se_coord_fmt = (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 264 RADEON_VTX_Z_PRE_MULT_1_OVER_W0 | 265 RADEON_TEX1_W_ROUTING_USE_Q1); 266 } 267 else { 268 rmesa->swtcl.needproj = GL_FALSE; 269 se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 | 270 RADEON_TEX1_W_ROUTING_USE_Q1); 271 } 272 273 _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj ); 274 275 if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) { 276 RADEON_STATECHANGE( rmesa, set ); 277 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt; 278 } 279} 280 281 282/* Flush vertices in the current dma region. 283 */ 284static void flush_last_swtcl_prim( radeonContextPtr rmesa ) 285{ 286 if (RADEON_DEBUG & DEBUG_IOCTL) 287 fprintf(stderr, "%s\n", __FUNCTION__); 288 289 rmesa->dma.flush = NULL; 290 291 if (rmesa->dma.current.buf) { 292 struct radeon_dma_region *current = &rmesa->dma.current; 293 GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset + 294 current->buf->buf->idx * RADEON_BUFFER_SIZE + 295 current->start); 296 297 assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); 298 299 assert (current->start + 300 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == 301 current->ptr); 302 303 if (rmesa->dma.current.start != rmesa->dma.current.ptr) { 304 radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ + 305 rmesa->hw.max_state_size + VBUF_BUFSZ ); 306 307 radeonEmitVertexAOS( rmesa, 308 rmesa->swtcl.vertex_size, 309 current_offset); 310 311 radeonEmitVbufPrim( rmesa, 312 rmesa->swtcl.vertex_format, 313 rmesa->swtcl.hw_primitive, 314 rmesa->swtcl.numverts); 315 } 316 317 rmesa->swtcl.numverts = 0; 318 current->start = current->ptr; 319 } 320} 321 322 323/* Alloc space in the current dma region. 324 */ 325static INLINE void * 326radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) 327{ 328 GLuint bytes = vsize * nverts; 329 330 if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) 331 radeonRefillCurrentDmaRegion( rmesa ); 332 333 if (!rmesa->dma.flush) { 334 rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; 335 rmesa->dma.flush = flush_last_swtcl_prim; 336 } 337 338 assert( vsize == rmesa->swtcl.vertex_size * 4 ); 339 assert( rmesa->dma.flush == flush_last_swtcl_prim ); 340 assert (rmesa->dma.current.start + 341 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == 342 rmesa->dma.current.ptr); 343 344 345 { 346 GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr); 347 rmesa->dma.current.ptr += bytes; 348 rmesa->swtcl.numverts += nverts; 349 return head; 350 } 351 352} 353 354 355/* 356 * Render unclipped vertex buffers by emitting vertices directly to 357 * dma buffers. Use strip/fan hardware primitives where possible. 358 * Try to simulate missing primitives with indexed vertices. 359 */ 360#define HAVE_POINTS 1 361#define HAVE_LINES 1 362#define HAVE_LINE_STRIPS 1 363#define HAVE_TRIANGLES 1 364#define HAVE_TRI_STRIPS 1 365#define HAVE_TRI_STRIP_1 0 366#define HAVE_TRI_FANS 1 367#define HAVE_QUADS 0 368#define HAVE_QUAD_STRIPS 0 369#define HAVE_POLYGONS 0 370/* \todo: is it possible to make "ELTS" work with t_vertex code ? */ 371#define HAVE_ELTS 0 372 373static const GLuint hw_prim[GL_POLYGON+1] = { 374 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT, 375 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 376 0, 377 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP, 378 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 379 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP, 380 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN, 381 0, 382 0, 383 0 384}; 385 386static INLINE void 387radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim ) 388{ 389 RADEON_NEWPRIM( rmesa ); 390 rmesa->swtcl.hw_primitive = hw_prim[prim]; 391 assert(rmesa->dma.current.ptr == rmesa->dma.current.start); 392} 393 394#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx); (void)rmesa 395#define INIT( prim ) radeonDmaPrimitive( rmesa, prim ) 396#define FLUSH() RADEON_NEWPRIM( rmesa ) 397#define GET_CURRENT_VB_MAX_VERTS() \ 398 (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4)) 399#define GET_SUBSEQUENT_VB_MAX_VERTS() \ 400 ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4)) 401#define ALLOC_VERTS( nr ) \ 402 radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 ) 403#define EMIT_VERTS( ctx, j, nr, buf ) \ 404 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf) 405 406#define TAG(x) radeon_dma_##x 407#include "tnl_dd/t_dd_dmatmp.h" 408 409 410/**********************************************************************/ 411/* Render pipeline stage */ 412/**********************************************************************/ 413 414 415static GLboolean radeon_run_render( GLcontext *ctx, 416 struct tnl_pipeline_stage *stage ) 417{ 418 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 419 TNLcontext *tnl = TNL_CONTEXT(ctx); 420 struct vertex_buffer *VB = &tnl->vb; 421 tnl_render_func *tab = TAG(render_tab_verts); 422 GLuint i; 423 424 if (rmesa->swtcl.indexed_verts.buf) 425 RELEASE_ELT_VERTS(); 426 427 if (rmesa->swtcl.RenderIndex != 0 || 428 !radeon_dma_validate_render( ctx, VB )) 429 return GL_TRUE; 430 431 tnl->Driver.Render.Start( ctx ); 432 433 for (i = 0 ; i < VB->PrimitiveCount ; i++) 434 { 435 GLuint prim = VB->Primitive[i].mode; 436 GLuint start = VB->Primitive[i].start; 437 GLuint length = VB->Primitive[i].count; 438 439 if (!length) 440 continue; 441 442 if (RADEON_DEBUG & DEBUG_PRIMS) 443 fprintf(stderr, "radeon_render.c: prim %s %d..%d\n", 444 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK), 445 start, start+length); 446 447 if (length) 448 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim ); 449 } 450 451 tnl->Driver.Render.Finish( ctx ); 452 453 return GL_FALSE; /* finished the pipe */ 454} 455 456 457 458 459const struct tnl_pipeline_stage _radeon_render_stage = 460{ 461 "radeon render", 462 NULL, 463 NULL, 464 NULL, 465 NULL, 466 radeon_run_render /* run */ 467}; 468 469 470/**************************************************************************/ 471 472/* Radeon texture rectangle expects coords in 0..1 range, not 0..dimension 473 * as in the extension spec. Need to translate here. 474 * 475 * Note that swrast expects 0..dimension, so if a fallback is active, 476 * don't do anything. (Maybe need to configure swrast to match hw) 477 */ 478struct texrect_stage_data { 479 GLvector4f texcoord[MAX_TEXTURE_UNITS]; 480}; 481 482#define TEXRECT_STAGE_DATA(stage) ((struct texrect_stage_data *)stage->privatePtr) 483 484 485static GLboolean run_texrect_stage( GLcontext *ctx, 486 struct tnl_pipeline_stage *stage ) 487{ 488 struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage); 489 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 490 TNLcontext *tnl = TNL_CONTEXT(ctx); 491 struct vertex_buffer *VB = &tnl->vb; 492 GLuint i; 493 494 if (rmesa->Fallback) 495 return GL_TRUE; 496 497 for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++) { 498 if (ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_RECT_BIT) { 499 struct gl_texture_object *texObj = ctx->Texture.Unit[i].CurrentRect; 500 struct gl_texture_image *texImage = texObj->Image[0][texObj->BaseLevel]; 501 const GLfloat iw = 1.0/texImage->Width; 502 const GLfloat ih = 1.0/texImage->Height; 503 GLfloat *in = (GLfloat *)VB->TexCoordPtr[i]->data; 504 GLint instride = VB->TexCoordPtr[i]->stride; 505 GLfloat (*out)[4] = store->texcoord[i].data; 506 GLint j; 507 508 store->texcoord[i].size = VB->TexCoordPtr[i]->size; 509 for (j = 0 ; j < VB->Count ; j++) { 510 switch (VB->TexCoordPtr[i]->size) { 511 case 4: 512 out[j][3] = in[3]; 513 /* fallthrough */ 514 case 3: 515 out[j][2] = in[2]; 516 /* fallthrough */ 517 default: 518 out[j][0] = in[0] * iw; 519 out[j][1] = in[1] * ih; 520 } 521 in = (GLfloat *)((GLubyte *)in + instride); 522 } 523 524 VB->AttribPtr[VERT_ATTRIB_TEX0+i] = VB->TexCoordPtr[i] = &store->texcoord[i]; 525 } 526 } 527 528 return GL_TRUE; 529} 530 531 532/* Called the first time stage->run() is invoked. 533 */ 534static GLboolean alloc_texrect_data( GLcontext *ctx, 535 struct tnl_pipeline_stage *stage ) 536{ 537 struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; 538 struct texrect_stage_data *store; 539 GLuint i; 540 541 stage->privatePtr = CALLOC(sizeof(*store)); 542 store = TEXRECT_STAGE_DATA(stage); 543 if (!store) 544 return GL_FALSE; 545 546 for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++) 547 _mesa_vector4f_alloc( &store->texcoord[i], 0, VB->Size, 32 ); 548 549 return GL_TRUE; 550} 551 552static void free_texrect_data( struct tnl_pipeline_stage *stage ) 553{ 554 struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage); 555 GLuint i; 556 557 if (store) { 558 for (i = 0 ; i < MAX_TEXTURE_UNITS ; i++) 559 if (store->texcoord[i].data) 560 _mesa_vector4f_free( &store->texcoord[i] ); 561 FREE( store ); 562 stage->privatePtr = NULL; 563 } 564} 565 566const struct tnl_pipeline_stage _radeon_texrect_stage = 567{ 568 "radeon texrect stage", /* name */ 569 NULL, 570 alloc_texrect_data, 571 free_texrect_data, 572 NULL, 573 run_texrect_stage 574}; 575 576 577/**************************************************************************/ 578 579 580static const GLuint reduced_hw_prim[GL_POLYGON+1] = { 581 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT, 582 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 583 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 584 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 585 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 586 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 587 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 588 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 589 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 590 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 591}; 592 593static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim ); 594static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim ); 595static void radeonResetLineStipple( GLcontext *ctx ); 596 597 598/*********************************************************************** 599 * Emit primitives as inline vertices * 600 ***********************************************************************/ 601 602#undef LOCAL_VARS 603#undef ALLOC_VERTS 604#define CTX_ARG radeonContextPtr rmesa 605#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size 606#define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 ) 607#undef LOCAL_VARS 608#define LOCAL_VARS \ 609 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ 610 const char *radeonverts = (char *)rmesa->swtcl.verts; 611#define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int))) 612#define VERTEX radeonVertex 613#undef TAG 614#define TAG(x) radeon_##x 615#include "tnl_dd/t_dd_triemit.h" 616 617 618/*********************************************************************** 619 * Macros for t_dd_tritmp.h to draw basic primitives * 620 ***********************************************************************/ 621 622#define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d ) 623#define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c ) 624#define LINE( a, b ) radeon_line( rmesa, a, b ) 625#define POINT( a ) radeon_point( rmesa, a ) 626 627/*********************************************************************** 628 * Build render functions from dd templates * 629 ***********************************************************************/ 630 631#define RADEON_TWOSIDE_BIT 0x01 632#define RADEON_UNFILLED_BIT 0x02 633#define RADEON_MAX_TRIFUNC 0x04 634 635 636static struct { 637 tnl_points_func points; 638 tnl_line_func line; 639 tnl_triangle_func triangle; 640 tnl_quad_func quad; 641} rast_tab[RADEON_MAX_TRIFUNC]; 642 643 644#define DO_FALLBACK 0 645#define DO_OFFSET 0 646#define DO_UNFILLED (IND & RADEON_UNFILLED_BIT) 647#define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT) 648#define DO_FLAT 0 649#define DO_TRI 1 650#define DO_QUAD 1 651#define DO_LINE 1 652#define DO_POINTS 1 653#define DO_FULL_QUAD 1 654 655#define HAVE_RGBA 1 656#define HAVE_SPEC 1 657#define HAVE_BACK_COLORS 0 658#define HAVE_HW_FLATSHADE 1 659#define TAB rast_tab 660 661#define DEPTH_SCALE 1.0 662#define UNFILLED_TRI unfilled_tri 663#define UNFILLED_QUAD unfilled_quad 664#define VERT_X(_v) _v->v.x 665#define VERT_Y(_v) _v->v.y 666#define VERT_Z(_v) _v->v.z 667#define AREA_IS_CCW( a ) (a < 0) 668#define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int))) 669 670#define VERT_SET_RGBA( v, c ) \ 671do { \ 672 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \ 673 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ 674 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ 675 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ 676 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ 677} while (0) 678 679#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] 680 681#define VERT_SET_SPEC( v, c ) \ 682do { \ 683 if (specoffset) { \ 684 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \ 685 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \ 686 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \ 687 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \ 688 } \ 689} while (0) 690#define VERT_COPY_SPEC( v0, v1 ) \ 691do { \ 692 if (specoffset) { \ 693 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \ 694 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \ 695 spec0->red = spec1->red; \ 696 spec0->green = spec1->green; \ 697 spec0->blue = spec1->blue; \ 698 } \ 699} while (0) 700 701/* These don't need LE32_TO_CPU() as they used to save and restore 702 * colors which are already in the correct format. 703 */ 704#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] 705#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] 706#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] 707#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] 708 709#undef LOCAL_VARS 710#undef TAG 711#undef INIT 712 713#define LOCAL_VARS(n) \ 714 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ 715 GLuint color[n], spec[n]; \ 716 GLuint coloroffset = rmesa->swtcl.coloroffset; \ 717 GLuint specoffset = rmesa->swtcl.specoffset; \ 718 (void) color; (void) spec; (void) coloroffset; (void) specoffset; 719 720/*********************************************************************** 721 * Helpers for rendering unfilled primitives * 722 ***********************************************************************/ 723 724#define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] ) 725#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive 726#undef TAG 727#define TAG(x) x 728#include "tnl_dd/t_dd_unfilled.h" 729#undef IND 730 731 732/*********************************************************************** 733 * Generate GL render functions * 734 ***********************************************************************/ 735 736 737#define IND (0) 738#define TAG(x) x 739#include "tnl_dd/t_dd_tritmp.h" 740 741#define IND (RADEON_TWOSIDE_BIT) 742#define TAG(x) x##_twoside 743#include "tnl_dd/t_dd_tritmp.h" 744 745#define IND (RADEON_UNFILLED_BIT) 746#define TAG(x) x##_unfilled 747#include "tnl_dd/t_dd_tritmp.h" 748 749#define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT) 750#define TAG(x) x##_twoside_unfilled 751#include "tnl_dd/t_dd_tritmp.h" 752 753 754static void init_rast_tab( void ) 755{ 756 init(); 757 init_twoside(); 758 init_unfilled(); 759 init_twoside_unfilled(); 760} 761 762/**********************************************************************/ 763/* Render unclipped begin/end objects */ 764/**********************************************************************/ 765 766#define RENDER_POINTS( start, count ) \ 767 for ( ; start < count ; start++) \ 768 radeon_point( rmesa, VERT(start) ) 769#define RENDER_LINE( v0, v1 ) \ 770 radeon_line( rmesa, VERT(v0), VERT(v1) ) 771#define RENDER_TRI( v0, v1, v2 ) \ 772 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) 773#define RENDER_QUAD( v0, v1, v2, v3 ) \ 774 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) 775#undef INIT 776#define INIT(x) do { \ 777 radeonRenderPrimitive( ctx, x ); \ 778} while (0) 779#undef LOCAL_VARS 780#define LOCAL_VARS \ 781 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ 782 const GLuint vertsize = rmesa->swtcl.vertex_size; \ 783 const char *radeonverts = (char *)rmesa->swtcl.verts; \ 784 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ 785 const GLboolean stipple = ctx->Line.StippleFlag; \ 786 (void) elt; (void) stipple; 787#define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx ); 788#define RESET_OCCLUSION 789#define PRESERVE_VB_DEFS 790#define ELT(x) (x) 791#define TAG(x) radeon_##x##_verts 792#include "tnl/t_vb_rendertmp.h" 793#undef ELT 794#undef TAG 795#define TAG(x) radeon_##x##_elts 796#define ELT(x) elt[x] 797#include "tnl/t_vb_rendertmp.h" 798 799 800 801/**********************************************************************/ 802/* Choose render functions */ 803/**********************************************************************/ 804 805void radeonChooseRenderState( GLcontext *ctx ) 806{ 807 TNLcontext *tnl = TNL_CONTEXT(ctx); 808 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 809 GLuint index = 0; 810 GLuint flags = ctx->_TriangleCaps; 811 812 if (!rmesa->TclFallback || rmesa->Fallback) 813 return; 814 815 if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT; 816 if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT; 817 818 if (index != rmesa->swtcl.RenderIndex) { 819 tnl->Driver.Render.Points = rast_tab[index].points; 820 tnl->Driver.Render.Line = rast_tab[index].line; 821 tnl->Driver.Render.ClippedLine = rast_tab[index].line; 822 tnl->Driver.Render.Triangle = rast_tab[index].triangle; 823 tnl->Driver.Render.Quad = rast_tab[index].quad; 824 825 if (index == 0) { 826 tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts; 827 tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts; 828 tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly; 829 } else { 830 tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; 831 tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; 832 tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; 833 } 834 835 rmesa->swtcl.RenderIndex = index; 836 } 837} 838 839 840/**********************************************************************/ 841/* High level hooks for t_vb_render.c */ 842/**********************************************************************/ 843 844 845static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim ) 846{ 847 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 848 849 if (rmesa->swtcl.hw_primitive != hwprim) { 850 RADEON_NEWPRIM( rmesa ); 851 rmesa->swtcl.hw_primitive = hwprim; 852 } 853} 854 855static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim ) 856{ 857 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 858 rmesa->swtcl.render_primitive = prim; 859 if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) 860 radeonRasterPrimitive( ctx, reduced_hw_prim[prim] ); 861} 862 863static void radeonRenderFinish( GLcontext *ctx ) 864{ 865} 866 867static void radeonResetLineStipple( GLcontext *ctx ) 868{ 869 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 870 RADEON_STATECHANGE( rmesa, lin ); 871} 872 873 874/**********************************************************************/ 875/* Transition to/from hardware rasterization. */ 876/**********************************************************************/ 877 878static const char * const fallbackStrings[] = { 879 "Texture mode", 880 "glDrawBuffer(GL_FRONT_AND_BACK)", 881 "glEnable(GL_STENCIL) without hw stencil buffer", 882 "glRenderMode(selection or feedback)", 883 "glBlendEquation", 884 "glBlendFunc", 885 "RADEON_NO_RAST", 886 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)" 887}; 888 889 890static const char *getFallbackString(GLuint bit) 891{ 892 int i = 0; 893 while (bit > 1) { 894 i++; 895 bit >>= 1; 896 } 897 return fallbackStrings[i]; 898} 899 900 901void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) 902{ 903 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 904 TNLcontext *tnl = TNL_CONTEXT(ctx); 905 GLuint oldfallback = rmesa->Fallback; 906 907 if (mode) { 908 rmesa->Fallback |= bit; 909 if (oldfallback == 0) { 910 RADEON_FIREVERTICES( rmesa ); 911 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); 912 _swsetup_Wakeup( ctx ); 913 rmesa->swtcl.RenderIndex = ~0; 914 if (RADEON_DEBUG & DEBUG_FALLBACKS) { 915 fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n", 916 bit, getFallbackString(bit)); 917 } 918 } 919 } 920 else { 921 rmesa->Fallback &= ~bit; 922 if (oldfallback == bit) { 923 _swrast_flush( ctx ); 924 tnl->Driver.Render.Start = radeonRenderStart; 925 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive; 926 tnl->Driver.Render.Finish = radeonRenderFinish; 927 928 tnl->Driver.Render.BuildVertices = _tnl_build_vertices; 929 tnl->Driver.Render.CopyPV = _tnl_copy_pv; 930 tnl->Driver.Render.Interp = _tnl_interp; 931 932 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple; 933 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE ); 934 if (rmesa->TclFallback) { 935 /* These are already done if rmesa->TclFallback goes to 936 * zero above. But not if it doesn't (RADEON_NO_TCL for 937 * example?) 938 */ 939 radeonChooseVertexState( ctx ); 940 radeonChooseRenderState( ctx ); 941 } 942 if (RADEON_DEBUG & DEBUG_FALLBACKS) { 943 fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n", 944 bit, getFallbackString(bit)); 945 } 946 } 947 } 948} 949 950 951void radeonFlushVertices( GLcontext *ctx, GLuint flags ) 952{ 953 _tnl_FlushVertices( ctx, flags ); 954 955 if (flags & FLUSH_STORED_VERTICES) 956 RADEON_NEWPRIM( RADEON_CONTEXT( ctx ) ); 957} 958 959/**********************************************************************/ 960/* Initialization. */ 961/**********************************************************************/ 962 963void radeonInitSwtcl( GLcontext *ctx ) 964{ 965 TNLcontext *tnl = TNL_CONTEXT(ctx); 966 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 967 static int firsttime = 1; 968 969 if (firsttime) { 970 init_rast_tab(); 971 firsttime = 0; 972 } 973 974 tnl->Driver.Render.Start = radeonRenderStart; 975 tnl->Driver.Render.Finish = radeonRenderFinish; 976 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive; 977 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple; 978 tnl->Driver.Render.BuildVertices = _tnl_build_vertices; 979 tnl->Driver.Render.CopyPV = _tnl_copy_pv; 980 tnl->Driver.Render.Interp = _tnl_interp; 981 982 _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 983 RADEON_MAX_TNL_VERTEX_SIZE); 984 985 rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; 986 rmesa->swtcl.RenderIndex = ~0; 987 rmesa->swtcl.render_primitive = GL_TRIANGLES; 988 rmesa->swtcl.hw_primitive = 0; 989} 990 991 992void radeonDestroySwtcl( GLcontext *ctx ) 993{ 994 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 995 996 if (rmesa->swtcl.indexed_verts.buf) 997 radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, 998 __FUNCTION__ ); 999} 1000