radeon_texstate.c revision 83e93b6008213ad86607027e8434ecaccc8b1a2c
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Kevin E. Martin <martin@valinux.com> 33 * Gareth Hughes <gareth@valinux.com> 34 */ 35 36#include "main/glheader.h" 37#include "main/imports.h" 38#include "main/colormac.h" 39#include "main/context.h" 40#include "main/macros.h" 41#include "main/teximage.h" 42#include "main/texstate.h" 43#include "main/texobj.h" 44#include "main/enums.h" 45 46#include "radeon_context.h" 47#include "radeon_mipmap_tree.h" 48#include "radeon_state.h" 49#include "radeon_ioctl.h" 50#include "radeon_swtcl.h" 51#include "radeon_tex.h" 52#include "radeon_tcl.h" 53 54 55#define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8 56#define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8 57#define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88 58#define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422 59#define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422 60#define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1 61#define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1 62#define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23 63#define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45 64 65#define _COLOR(f) \ 66 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 } 67#define _COLOR_REV(f) \ 68 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 } 69#define _ALPHA(f) \ 70 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 } 71#define _ALPHA_REV(f) \ 72 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 } 73#define _YUV(f) \ 74 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB } 75#define _INVALID(f) \ 76 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 } 77#define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \ 78 && (tx_table[f].format != 0xffffffff) ) 79 80struct tx_table { 81 GLuint format, filter; 82}; 83 84/* XXX verify this table against MESA_FORMAT_x values */ 85static const struct tx_table tx_table[] = 86{ 87 _INVALID(NONE), /* MESA_FORMAT_NONE */ 88 _ALPHA(RGBA8888), 89 _ALPHA_REV(RGBA8888), 90 _ALPHA(ARGB8888), 91 _ALPHA_REV(ARGB8888), 92 [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 }, 93 _COLOR(RGB565), 94 _COLOR_REV(RGB565), 95 _ALPHA(ARGB4444), 96 _ALPHA_REV(ARGB4444), 97 _ALPHA(ARGB1555), 98 _ALPHA_REV(ARGB1555), 99 _ALPHA(AL88), 100 _ALPHA_REV(AL88), 101 _ALPHA(A8), 102 _COLOR(L8), 103 _ALPHA(I8), 104 _INVALID(CI8), 105 _YUV(YCBCR), 106 _YUV(YCBCR_REV), 107 _INVALID(RGB_FXT1), 108 _INVALID(RGBA_FXT1), 109 _COLOR(RGB_DXT1), 110 _ALPHA(RGBA_DXT1), 111 _ALPHA(RGBA_DXT3), 112 _ALPHA(RGBA_DXT5), 113}; 114 115#undef _COLOR 116#undef _ALPHA 117#undef _INVALID 118 119/* ================================================================ 120 * Texture combine functions 121 */ 122 123/* GL_ARB_texture_env_combine support 124 */ 125 126/* The color tables have combine functions for GL_SRC_COLOR, 127 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA. 128 */ 129static GLuint radeon_texture_color[][RADEON_MAX_TEXTURE_UNITS] = 130{ 131 { 132 RADEON_COLOR_ARG_A_T0_COLOR, 133 RADEON_COLOR_ARG_A_T1_COLOR, 134 RADEON_COLOR_ARG_A_T2_COLOR 135 }, 136 { 137 RADEON_COLOR_ARG_A_T0_COLOR | RADEON_COMP_ARG_A, 138 RADEON_COLOR_ARG_A_T1_COLOR | RADEON_COMP_ARG_A, 139 RADEON_COLOR_ARG_A_T2_COLOR | RADEON_COMP_ARG_A 140 }, 141 { 142 RADEON_COLOR_ARG_A_T0_ALPHA, 143 RADEON_COLOR_ARG_A_T1_ALPHA, 144 RADEON_COLOR_ARG_A_T2_ALPHA 145 }, 146 { 147 RADEON_COLOR_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A, 148 RADEON_COLOR_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A, 149 RADEON_COLOR_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A 150 }, 151}; 152 153static GLuint radeon_tfactor_color[] = 154{ 155 RADEON_COLOR_ARG_A_TFACTOR_COLOR, 156 RADEON_COLOR_ARG_A_TFACTOR_COLOR | RADEON_COMP_ARG_A, 157 RADEON_COLOR_ARG_A_TFACTOR_ALPHA, 158 RADEON_COLOR_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A 159}; 160 161static GLuint radeon_primary_color[] = 162{ 163 RADEON_COLOR_ARG_A_DIFFUSE_COLOR, 164 RADEON_COLOR_ARG_A_DIFFUSE_COLOR | RADEON_COMP_ARG_A, 165 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA, 166 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A 167}; 168 169static GLuint radeon_previous_color[] = 170{ 171 RADEON_COLOR_ARG_A_CURRENT_COLOR, 172 RADEON_COLOR_ARG_A_CURRENT_COLOR | RADEON_COMP_ARG_A, 173 RADEON_COLOR_ARG_A_CURRENT_ALPHA, 174 RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A 175}; 176 177/* GL_ZERO table - indices 0-3 178 * GL_ONE table - indices 1-4 179 */ 180static GLuint radeon_zero_color[] = 181{ 182 RADEON_COLOR_ARG_A_ZERO, 183 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A, 184 RADEON_COLOR_ARG_A_ZERO, 185 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A, 186 RADEON_COLOR_ARG_A_ZERO 187}; 188 189 190/* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA. 191 */ 192static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] = 193{ 194 { 195 RADEON_ALPHA_ARG_A_T0_ALPHA, 196 RADEON_ALPHA_ARG_A_T1_ALPHA, 197 RADEON_ALPHA_ARG_A_T2_ALPHA 198 }, 199 { 200 RADEON_ALPHA_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A, 201 RADEON_ALPHA_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A, 202 RADEON_ALPHA_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A 203 }, 204}; 205 206static GLuint radeon_tfactor_alpha[] = 207{ 208 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA, 209 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A 210}; 211 212static GLuint radeon_primary_alpha[] = 213{ 214 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA, 215 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A 216}; 217 218static GLuint radeon_previous_alpha[] = 219{ 220 RADEON_ALPHA_ARG_A_CURRENT_ALPHA, 221 RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A 222}; 223 224/* GL_ZERO table - indices 0-1 225 * GL_ONE table - indices 1-2 226 */ 227static GLuint radeon_zero_alpha[] = 228{ 229 RADEON_ALPHA_ARG_A_ZERO, 230 RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A, 231 RADEON_ALPHA_ARG_A_ZERO 232}; 233 234 235/* Extract the arg from slot A, shift it into the correct argument slot 236 * and set the corresponding complement bit. 237 */ 238#define RADEON_COLOR_ARG( n, arg ) \ 239do { \ 240 color_combine |= \ 241 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \ 242 << RADEON_COLOR_ARG_##arg##_SHIFT); \ 243 color_combine |= \ 244 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \ 245 << RADEON_COMP_ARG_##arg##_SHIFT); \ 246} while (0) 247 248#define RADEON_ALPHA_ARG( n, arg ) \ 249do { \ 250 alpha_combine |= \ 251 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \ 252 << RADEON_ALPHA_ARG_##arg##_SHIFT); \ 253 alpha_combine |= \ 254 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \ 255 << RADEON_COMP_ARG_##arg##_SHIFT); \ 256} while (0) 257 258 259/* ================================================================ 260 * Texture unit state management 261 */ 262 263static GLboolean radeonUpdateTextureEnv( struct gl_context *ctx, int unit ) 264{ 265 r100ContextPtr rmesa = R100_CONTEXT(ctx); 266 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; 267 GLuint color_combine, alpha_combine; 268 const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO 269 | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD 270 | RADEON_SCALE_1X | RADEON_CLAMP_TX; 271 const GLuint alpha_combine0 = RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO 272 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | RADEON_BLEND_CTL_ADD 273 | RADEON_SCALE_1X | RADEON_CLAMP_TX; 274 275 276 /* texUnit->_Current can be NULL if and only if the texture unit is 277 * not actually enabled. 278 */ 279 assert( (texUnit->_ReallyEnabled == 0) 280 || (texUnit->_Current != NULL) ); 281 282 if ( RADEON_DEBUG & RADEON_TEXTURE ) { 283 fprintf( stderr, "%s( %p, %d )\n", __FUNCTION__, (void *)ctx, unit ); 284 } 285 286 /* Set the texture environment state. Isn't this nice and clean? 287 * The chip will automagically set the texture alpha to 0xff when 288 * the texture format does not include an alpha component. This 289 * reduces the amount of special-casing we have to do, alpha-only 290 * textures being a notable exception. Doesn't work for luminance 291 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100). 292 */ 293 /* Don't cache these results. 294 */ 295 rmesa->state.texture.unit[unit].format = 0; 296 rmesa->state.texture.unit[unit].envMode = 0; 297 298 if ( !texUnit->_ReallyEnabled ) { 299 color_combine = color_combine0; 300 alpha_combine = alpha_combine0; 301 } 302 else { 303 GLuint color_arg[3], alpha_arg[3]; 304 GLuint i; 305 const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB; 306 const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA; 307 GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB; 308 GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA; 309 310 311 /* Step 1: 312 * Extract the color and alpha combine function arguments. 313 */ 314 for ( i = 0 ; i < numColorArgs ; i++ ) { 315 const GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR; 316 const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i]; 317 assert(op >= 0); 318 assert(op <= 3); 319 switch ( srcRGBi ) { 320 case GL_TEXTURE: 321 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_ALPHA) 322 color_arg[i] = radeon_zero_color[op]; 323 else 324 color_arg[i] = radeon_texture_color[op][unit]; 325 break; 326 case GL_CONSTANT: 327 color_arg[i] = radeon_tfactor_color[op]; 328 break; 329 case GL_PRIMARY_COLOR: 330 color_arg[i] = radeon_primary_color[op]; 331 break; 332 case GL_PREVIOUS: 333 color_arg[i] = radeon_previous_color[op]; 334 break; 335 case GL_ZERO: 336 color_arg[i] = radeon_zero_color[op]; 337 break; 338 case GL_ONE: 339 color_arg[i] = radeon_zero_color[op+1]; 340 break; 341 case GL_TEXTURE0: 342 case GL_TEXTURE1: 343 case GL_TEXTURE2: { 344 GLuint txunit = srcRGBi - GL_TEXTURE0; 345 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_ALPHA) 346 color_arg[i] = radeon_zero_color[op]; 347 else 348 /* implement ogl 1.4/1.5 core spec here, not specification of 349 * GL_ARB_texture_env_crossbar (which would require disabling blending 350 * instead of undefined results when referencing not enabled texunit) */ 351 color_arg[i] = radeon_texture_color[op][txunit]; 352 } 353 break; 354 default: 355 return GL_FALSE; 356 } 357 } 358 359 for ( i = 0 ; i < numAlphaArgs ; i++ ) { 360 const GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA; 361 const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i]; 362 assert(op >= 0); 363 assert(op <= 1); 364 switch ( srcAi ) { 365 case GL_TEXTURE: 366 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_LUMINANCE) 367 alpha_arg[i] = radeon_zero_alpha[op+1]; 368 else 369 alpha_arg[i] = radeon_texture_alpha[op][unit]; 370 break; 371 case GL_CONSTANT: 372 alpha_arg[i] = radeon_tfactor_alpha[op]; 373 break; 374 case GL_PRIMARY_COLOR: 375 alpha_arg[i] = radeon_primary_alpha[op]; 376 break; 377 case GL_PREVIOUS: 378 alpha_arg[i] = radeon_previous_alpha[op]; 379 break; 380 case GL_ZERO: 381 alpha_arg[i] = radeon_zero_alpha[op]; 382 break; 383 case GL_ONE: 384 alpha_arg[i] = radeon_zero_alpha[op+1]; 385 break; 386 case GL_TEXTURE0: 387 case GL_TEXTURE1: 388 case GL_TEXTURE2: { 389 GLuint txunit = srcAi - GL_TEXTURE0; 390 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_LUMINANCE) 391 alpha_arg[i] = radeon_zero_alpha[op+1]; 392 else 393 alpha_arg[i] = radeon_texture_alpha[op][txunit]; 394 } 395 break; 396 default: 397 return GL_FALSE; 398 } 399 } 400 401 /* Step 2: 402 * Build up the color and alpha combine functions. 403 */ 404 switch ( texUnit->_CurrentCombine->ModeRGB ) { 405 case GL_REPLACE: 406 color_combine = (RADEON_COLOR_ARG_A_ZERO | 407 RADEON_COLOR_ARG_B_ZERO | 408 RADEON_BLEND_CTL_ADD | 409 RADEON_CLAMP_TX); 410 RADEON_COLOR_ARG( 0, C ); 411 break; 412 case GL_MODULATE: 413 color_combine = (RADEON_COLOR_ARG_C_ZERO | 414 RADEON_BLEND_CTL_ADD | 415 RADEON_CLAMP_TX); 416 RADEON_COLOR_ARG( 0, A ); 417 RADEON_COLOR_ARG( 1, B ); 418 break; 419 case GL_ADD: 420 color_combine = (RADEON_COLOR_ARG_B_ZERO | 421 RADEON_COMP_ARG_B | 422 RADEON_BLEND_CTL_ADD | 423 RADEON_CLAMP_TX); 424 RADEON_COLOR_ARG( 0, A ); 425 RADEON_COLOR_ARG( 1, C ); 426 break; 427 case GL_ADD_SIGNED: 428 color_combine = (RADEON_COLOR_ARG_B_ZERO | 429 RADEON_COMP_ARG_B | 430 RADEON_BLEND_CTL_ADDSIGNED | 431 RADEON_CLAMP_TX); 432 RADEON_COLOR_ARG( 0, A ); 433 RADEON_COLOR_ARG( 1, C ); 434 break; 435 case GL_SUBTRACT: 436 color_combine = (RADEON_COLOR_ARG_B_ZERO | 437 RADEON_COMP_ARG_B | 438 RADEON_BLEND_CTL_SUBTRACT | 439 RADEON_CLAMP_TX); 440 RADEON_COLOR_ARG( 0, A ); 441 RADEON_COLOR_ARG( 1, C ); 442 break; 443 case GL_INTERPOLATE: 444 color_combine = (RADEON_BLEND_CTL_BLEND | 445 RADEON_CLAMP_TX); 446 RADEON_COLOR_ARG( 0, B ); 447 RADEON_COLOR_ARG( 1, A ); 448 RADEON_COLOR_ARG( 2, C ); 449 break; 450 451 case GL_DOT3_RGB_EXT: 452 case GL_DOT3_RGBA_EXT: 453 /* The EXT version of the DOT3 extension does not support the 454 * scale factor, but the ARB version (and the version in OpenGL 455 * 1.3) does. 456 */ 457 RGBshift = 0; 458 /* FALLTHROUGH */ 459 460 case GL_DOT3_RGB: 461 case GL_DOT3_RGBA: 462 /* The R100 / RV200 only support a 1X multiplier in hardware 463 * w/the ARB version. 464 */ 465 if ( RGBshift != (RADEON_SCALE_1X >> RADEON_SCALE_SHIFT) ) { 466 return GL_FALSE; 467 } 468 469 RGBshift += 2; 470 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT) 471 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) { 472 /* is it necessary to set this or will it be ignored anyway? */ 473 Ashift = RGBshift; 474 } 475 476 color_combine = (RADEON_COLOR_ARG_C_ZERO | 477 RADEON_BLEND_CTL_DOT3 | 478 RADEON_CLAMP_TX); 479 RADEON_COLOR_ARG( 0, A ); 480 RADEON_COLOR_ARG( 1, B ); 481 break; 482 483 case GL_MODULATE_ADD_ATI: 484 color_combine = (RADEON_BLEND_CTL_ADD | 485 RADEON_CLAMP_TX); 486 RADEON_COLOR_ARG( 0, A ); 487 RADEON_COLOR_ARG( 1, C ); 488 RADEON_COLOR_ARG( 2, B ); 489 break; 490 case GL_MODULATE_SIGNED_ADD_ATI: 491 color_combine = (RADEON_BLEND_CTL_ADDSIGNED | 492 RADEON_CLAMP_TX); 493 RADEON_COLOR_ARG( 0, A ); 494 RADEON_COLOR_ARG( 1, C ); 495 RADEON_COLOR_ARG( 2, B ); 496 break; 497 case GL_MODULATE_SUBTRACT_ATI: 498 color_combine = (RADEON_BLEND_CTL_SUBTRACT | 499 RADEON_CLAMP_TX); 500 RADEON_COLOR_ARG( 0, A ); 501 RADEON_COLOR_ARG( 1, C ); 502 RADEON_COLOR_ARG( 2, B ); 503 break; 504 default: 505 return GL_FALSE; 506 } 507 508 switch ( texUnit->_CurrentCombine->ModeA ) { 509 case GL_REPLACE: 510 alpha_combine = (RADEON_ALPHA_ARG_A_ZERO | 511 RADEON_ALPHA_ARG_B_ZERO | 512 RADEON_BLEND_CTL_ADD | 513 RADEON_CLAMP_TX); 514 RADEON_ALPHA_ARG( 0, C ); 515 break; 516 case GL_MODULATE: 517 alpha_combine = (RADEON_ALPHA_ARG_C_ZERO | 518 RADEON_BLEND_CTL_ADD | 519 RADEON_CLAMP_TX); 520 RADEON_ALPHA_ARG( 0, A ); 521 RADEON_ALPHA_ARG( 1, B ); 522 break; 523 case GL_ADD: 524 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO | 525 RADEON_COMP_ARG_B | 526 RADEON_BLEND_CTL_ADD | 527 RADEON_CLAMP_TX); 528 RADEON_ALPHA_ARG( 0, A ); 529 RADEON_ALPHA_ARG( 1, C ); 530 break; 531 case GL_ADD_SIGNED: 532 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO | 533 RADEON_COMP_ARG_B | 534 RADEON_BLEND_CTL_ADDSIGNED | 535 RADEON_CLAMP_TX); 536 RADEON_ALPHA_ARG( 0, A ); 537 RADEON_ALPHA_ARG( 1, C ); 538 break; 539 case GL_SUBTRACT: 540 alpha_combine = (RADEON_COLOR_ARG_B_ZERO | 541 RADEON_COMP_ARG_B | 542 RADEON_BLEND_CTL_SUBTRACT | 543 RADEON_CLAMP_TX); 544 RADEON_ALPHA_ARG( 0, A ); 545 RADEON_ALPHA_ARG( 1, C ); 546 break; 547 case GL_INTERPOLATE: 548 alpha_combine = (RADEON_BLEND_CTL_BLEND | 549 RADEON_CLAMP_TX); 550 RADEON_ALPHA_ARG( 0, B ); 551 RADEON_ALPHA_ARG( 1, A ); 552 RADEON_ALPHA_ARG( 2, C ); 553 break; 554 555 case GL_MODULATE_ADD_ATI: 556 alpha_combine = (RADEON_BLEND_CTL_ADD | 557 RADEON_CLAMP_TX); 558 RADEON_ALPHA_ARG( 0, A ); 559 RADEON_ALPHA_ARG( 1, C ); 560 RADEON_ALPHA_ARG( 2, B ); 561 break; 562 case GL_MODULATE_SIGNED_ADD_ATI: 563 alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED | 564 RADEON_CLAMP_TX); 565 RADEON_ALPHA_ARG( 0, A ); 566 RADEON_ALPHA_ARG( 1, C ); 567 RADEON_ALPHA_ARG( 2, B ); 568 break; 569 case GL_MODULATE_SUBTRACT_ATI: 570 alpha_combine = (RADEON_BLEND_CTL_SUBTRACT | 571 RADEON_CLAMP_TX); 572 RADEON_ALPHA_ARG( 0, A ); 573 RADEON_ALPHA_ARG( 1, C ); 574 RADEON_ALPHA_ARG( 2, B ); 575 break; 576 default: 577 return GL_FALSE; 578 } 579 580 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB_EXT) 581 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB) ) { 582 alpha_combine |= RADEON_DOT_ALPHA_DONT_REPLICATE; 583 } 584 585 /* Step 3: 586 * Apply the scale factor. 587 */ 588 color_combine |= (RGBshift << RADEON_SCALE_SHIFT); 589 alpha_combine |= (Ashift << RADEON_SCALE_SHIFT); 590 591 /* All done! 592 */ 593 } 594 595 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine || 596 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) { 597 RADEON_STATECHANGE( rmesa, tex[unit] ); 598 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine; 599 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine; 600 } 601 602 return GL_TRUE; 603} 604 605void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname, 606 unsigned long long offset, GLint depth, GLuint pitch) 607{ 608 r100ContextPtr rmesa = pDRICtx->driverPrivate; 609 struct gl_texture_object *tObj = 610 _mesa_lookup_texture(rmesa->radeon.glCtx, texname); 611 radeonTexObjPtr t = radeon_tex_obj(tObj); 612 613 if (tObj == NULL) 614 return; 615 616 t->image_override = GL_TRUE; 617 618 if (!offset) 619 return; 620 621 t->bo = NULL; 622 t->override_offset = offset; 623 t->pp_txpitch = pitch - 32; 624 625 switch (depth) { 626 case 32: 627 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; 628 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; 629 break; 630 case 24: 631 default: 632 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; 633 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; 634 break; 635 case 16: 636 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; 637 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; 638 break; 639 } 640} 641 642void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, 643 __DRIdrawable *dPriv) 644{ 645 struct gl_texture_unit *texUnit; 646 struct gl_texture_object *texObj; 647 struct gl_texture_image *texImage; 648 struct radeon_renderbuffer *rb; 649 radeon_texture_image *rImage; 650 radeonContextPtr radeon; 651 r100ContextPtr rmesa; 652 struct radeon_framebuffer *rfb; 653 radeonTexObjPtr t; 654 uint32_t pitch_val; 655 uint32_t internalFormat, type, format; 656 gl_format texFormat; 657 658 type = GL_BGRA; 659 format = GL_UNSIGNED_BYTE; 660 internalFormat = (texture_format == __DRI_TEXTURE_FORMAT_RGB ? 3 : 4); 661 662 radeon = pDRICtx->driverPrivate; 663 rmesa = pDRICtx->driverPrivate; 664 665 rfb = dPriv->driverPrivate; 666 texUnit = _mesa_get_current_tex_unit(radeon->glCtx); 667 texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); 668 texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); 669 670 rImage = get_radeon_texture_image(texImage); 671 t = radeon_tex_obj(texObj); 672 if (t == NULL) { 673 return; 674 } 675 676 radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); 677 rb = rfb->color_rb[0]; 678 if (rb->bo == NULL) { 679 /* Failed to BO for the buffer */ 680 return; 681 } 682 683 _mesa_lock_texture(radeon->glCtx, texObj); 684 if (t->bo) { 685 radeon_bo_unref(t->bo); 686 t->bo = NULL; 687 } 688 if (rImage->bo) { 689 radeon_bo_unref(rImage->bo); 690 rImage->bo = NULL; 691 } 692 693 radeon_miptree_unreference(&t->mt); 694 radeon_miptree_unreference(&rImage->mt); 695 696 rImage->bo = rb->bo; 697 radeon_bo_ref(rImage->bo); 698 t->bo = rb->bo; 699 radeon_bo_ref(t->bo); 700 t->tile_bits = 0; 701 t->image_override = GL_TRUE; 702 t->override_offset = 0; 703 switch (rb->cpp) { 704 case 4: 705 if (texture_format == __DRI_TEXTURE_FORMAT_RGB) { 706 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; 707 texFormat = MESA_FORMAT_RGB888; 708 } 709 else { 710 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format; 711 texFormat = MESA_FORMAT_ARGB8888; 712 } 713 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter; 714 break; 715 case 3: 716 default: 717 texFormat = MESA_FORMAT_RGB888; 718 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format; 719 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter; 720 break; 721 case 2: 722 texFormat = MESA_FORMAT_RGB565; 723 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format; 724 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; 725 break; 726 } 727 728 _mesa_init_teximage_fields(radeon->glCtx, target, texImage, 729 rb->base.Width, rb->base.Height, 1, 0, 730 rb->cpp, texFormat); 731 texImage->RowStride = rb->pitch / rb->cpp; 732 733 t->pp_txpitch &= (1 << 13) -1; 734 pitch_val = rb->pitch; 735 736 t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT) 737 | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT); 738 if (target == GL_TEXTURE_RECTANGLE_NV) { 739 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; 740 t->pp_txpitch = pitch_val; 741 t->pp_txpitch -= 32; 742 } 743 t->validated = GL_TRUE; 744 _mesa_unlock_texture(radeon->glCtx, texObj); 745 return; 746} 747 748 749void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) 750{ 751 radeonSetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv); 752} 753 754 755#define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \ 756 RADEON_MIN_FILTER_MASK | \ 757 RADEON_MAG_FILTER_MASK | \ 758 RADEON_MAX_ANISO_MASK | \ 759 RADEON_YUV_TO_RGB | \ 760 RADEON_YUV_TEMPERATURE_MASK | \ 761 RADEON_CLAMP_S_MASK | \ 762 RADEON_CLAMP_T_MASK | \ 763 RADEON_BORDER_MODE_D3D ) 764 765#define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \ 766 RADEON_TXFORMAT_HEIGHT_MASK | \ 767 RADEON_TXFORMAT_FORMAT_MASK | \ 768 RADEON_TXFORMAT_F5_WIDTH_MASK | \ 769 RADEON_TXFORMAT_F5_HEIGHT_MASK | \ 770 RADEON_TXFORMAT_ALPHA_IN_MAP | \ 771 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \ 772 RADEON_TXFORMAT_NON_POWER2) 773 774 775static void disable_tex_obj_state( r100ContextPtr rmesa, 776 int unit ) 777{ 778 RADEON_STATECHANGE( rmesa, tex[unit] ); 779 780 RADEON_STATECHANGE( rmesa, tcl ); 781 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | 782 RADEON_Q_BIT(unit)); 783 784 if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) { 785 TCL_FALLBACK( rmesa->radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE); 786 rmesa->recheck_texgen[unit] = GL_TRUE; 787 } 788 789 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) { 790 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the 791 cubic_map bit on unit 2 when the unit is disabled, otherwise every 792 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other 793 units, better be safe than sorry though).*/ 794 RADEON_STATECHANGE( rmesa, tex[unit] ); 795 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE; 796 } 797 798 { 799 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; 800 GLuint tmp = rmesa->TexGenEnabled; 801 802 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit); 803 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit); 804 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift); 805 rmesa->TexGenNeedNormals[unit] = 0; 806 rmesa->TexGenEnabled |= 807 (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift; 808 809 if (tmp != rmesa->TexGenEnabled) { 810 rmesa->recheck_texgen[unit] = GL_TRUE; 811 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; 812 } 813 } 814} 815 816static void import_tex_obj_state( r100ContextPtr rmesa, 817 int unit, 818 radeonTexObjPtr texobj ) 819{ 820/* do not use RADEON_DB_STATE to avoid stale texture caches */ 821 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; 822 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; 823 824 RADEON_STATECHANGE( rmesa, tex[unit] ); 825 826 cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK; 827 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; 828 cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; 829 cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; 830 cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; 831 832 if (texobj->pp_txformat & RADEON_TXFORMAT_NON_POWER2) { 833 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0]; 834 txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */ 835 txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */ 836 RADEON_STATECHANGE( rmesa, txr[unit] ); 837 } 838 839 if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) { 840 se_coord_fmt |= RADEON_VTX_ST0_NONPARAMETRIC << unit; 841 } 842 else { 843 se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit); 844 845 if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { 846 uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; 847 848 RADEON_STATECHANGE( rmesa, cube[unit] ); 849 cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; 850 /* state filled out in the cube_emit */ 851 } 852 } 853 854 if (se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT]) { 855 RADEON_STATECHANGE( rmesa, set ); 856 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt; 857 } 858 859 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; 860} 861 862 863static void set_texgen_matrix( r100ContextPtr rmesa, 864 GLuint unit, 865 const GLfloat *s_plane, 866 const GLfloat *t_plane, 867 const GLfloat *r_plane, 868 const GLfloat *q_plane ) 869{ 870 rmesa->TexGenMatrix[unit].m[0] = s_plane[0]; 871 rmesa->TexGenMatrix[unit].m[4] = s_plane[1]; 872 rmesa->TexGenMatrix[unit].m[8] = s_plane[2]; 873 rmesa->TexGenMatrix[unit].m[12] = s_plane[3]; 874 875 rmesa->TexGenMatrix[unit].m[1] = t_plane[0]; 876 rmesa->TexGenMatrix[unit].m[5] = t_plane[1]; 877 rmesa->TexGenMatrix[unit].m[9] = t_plane[2]; 878 rmesa->TexGenMatrix[unit].m[13] = t_plane[3]; 879 880 rmesa->TexGenMatrix[unit].m[2] = r_plane[0]; 881 rmesa->TexGenMatrix[unit].m[6] = r_plane[1]; 882 rmesa->TexGenMatrix[unit].m[10] = r_plane[2]; 883 rmesa->TexGenMatrix[unit].m[14] = r_plane[3]; 884 885 rmesa->TexGenMatrix[unit].m[3] = q_plane[0]; 886 rmesa->TexGenMatrix[unit].m[7] = q_plane[1]; 887 rmesa->TexGenMatrix[unit].m[11] = q_plane[2]; 888 rmesa->TexGenMatrix[unit].m[15] = q_plane[3]; 889 890 rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit; 891 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; 892} 893 894/* Returns GL_FALSE if fallback required. 895 */ 896static GLboolean radeon_validate_texgen( struct gl_context *ctx, GLuint unit ) 897{ 898 r100ContextPtr rmesa = R100_CONTEXT(ctx); 899 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; 900 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4; 901 GLuint tmp = rmesa->TexGenEnabled; 902 static const GLfloat reflect[16] = { 903 -1, 0, 0, 0, 904 0, -1, 0, 0, 905 0, 0, -1, 0, 906 0, 0, 0, 1 }; 907 908 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE << unit); 909 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE << unit); 910 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK << inputshift); 911 rmesa->TexGenNeedNormals[unit] = 0; 912 913 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) { 914 /* Disabled, no fallback: 915 */ 916 rmesa->TexGenEnabled |= 917 (RADEON_TEXGEN_INPUT_TEXCOORD_0 + unit) << inputshift; 918 return GL_TRUE; 919 } 920 /* the r100 cannot do texgen for some coords and not for others 921 * we do not detect such cases (certainly can't do it here) and just 922 * ASSUME that when S and T are texgen enabled we do not need other 923 * non-texgen enabled coords, no matter if the R and Q bits are texgen 924 * enabled. Still check for mixed mode texgen for all coords. 925 */ 926 else if ( (texUnit->TexGenEnabled & S_BIT) && 927 (texUnit->TexGenEnabled & T_BIT) && 928 (texUnit->GenS.Mode == texUnit->GenT.Mode) ) { 929 if ( ((texUnit->TexGenEnabled & R_BIT) && 930 (texUnit->GenS.Mode != texUnit->GenR.Mode)) || 931 ((texUnit->TexGenEnabled & Q_BIT) && 932 (texUnit->GenS.Mode != texUnit->GenQ.Mode)) ) { 933 /* Mixed modes, fallback: 934 */ 935 if (RADEON_DEBUG & RADEON_FALLBACKS) 936 fprintf(stderr, "fallback mixed texgen\n"); 937 return GL_FALSE; 938 } 939 rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit; 940 } 941 else { 942 /* some texgen mode not including both S and T bits */ 943 if (RADEON_DEBUG & RADEON_FALLBACKS) 944 fprintf(stderr, "fallback mixed texgen/nontexgen\n"); 945 return GL_FALSE; 946 } 947 948 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) { 949 /* need this here for vtxfmt presumably. Argh we need to set 950 this from way too many places, would be much easier if we could leave 951 tcl q coord always enabled as on r200) */ 952 RADEON_STATECHANGE( rmesa, tcl ); 953 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit); 954 } 955 956 switch (texUnit->GenS.Mode) { 957 case GL_OBJECT_LINEAR: 958 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift; 959 set_texgen_matrix( rmesa, unit, 960 texUnit->GenS.ObjectPlane, 961 texUnit->GenT.ObjectPlane, 962 texUnit->GenR.ObjectPlane, 963 texUnit->GenQ.ObjectPlane); 964 break; 965 966 case GL_EYE_LINEAR: 967 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift; 968 set_texgen_matrix( rmesa, unit, 969 texUnit->GenS.EyePlane, 970 texUnit->GenT.EyePlane, 971 texUnit->GenR.EyePlane, 972 texUnit->GenQ.EyePlane); 973 break; 974 975 case GL_REFLECTION_MAP_NV: 976 rmesa->TexGenNeedNormals[unit] = GL_TRUE; 977 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT << inputshift; 978 /* TODO: unknown if this is needed/correct */ 979 set_texgen_matrix( rmesa, unit, reflect, reflect + 4, 980 reflect + 8, reflect + 12 ); 981 break; 982 983 case GL_NORMAL_MAP_NV: 984 rmesa->TexGenNeedNormals[unit] = GL_TRUE; 985 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL << inputshift; 986 break; 987 988 case GL_SPHERE_MAP: 989 /* the mode which everyone uses :-( */ 990 default: 991 /* Unsupported mode, fallback: 992 */ 993 if (RADEON_DEBUG & RADEON_FALLBACKS) 994 fprintf(stderr, "fallback GL_SPHERE_MAP\n"); 995 return GL_FALSE; 996 } 997 998 if (tmp != rmesa->TexGenEnabled) { 999 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; 1000 } 1001 1002 return GL_TRUE; 1003} 1004 1005/** 1006 * Compute the cached hardware register values for the given texture object. 1007 * 1008 * \param rmesa Context pointer 1009 * \param t the r300 texture object 1010 */ 1011static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int unit) 1012{ 1013 const struct gl_texture_image *firstImage; 1014 GLint log2Width, log2Height, log2Depth, texelBytes; 1015 1016 if ( t->bo ) { 1017 return GL_TRUE; 1018 } 1019 1020 firstImage = t->base.Image[0][t->minLod]; 1021 1022 if (firstImage->Border > 0) { 1023 fprintf(stderr, "%s: border\n", __FUNCTION__); 1024 return GL_FALSE; 1025 } 1026 1027 log2Width = firstImage->WidthLog2; 1028 log2Height = firstImage->HeightLog2; 1029 log2Depth = firstImage->DepthLog2; 1030 texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); 1031 1032 if (!t->image_override) { 1033 if (VALID_FORMAT(firstImage->TexFormat)) { 1034 const struct tx_table *table = tx_table; 1035 1036 t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | 1037 RADEON_TXFORMAT_ALPHA_IN_MAP); 1038 t->pp_txfilter &= ~RADEON_YUV_TO_RGB; 1039 1040 t->pp_txformat |= table[ firstImage->TexFormat ].format; 1041 t->pp_txfilter |= table[ firstImage->TexFormat ].filter; 1042 } else { 1043 _mesa_problem(NULL, "unexpected texture format in %s", 1044 __FUNCTION__); 1045 return GL_FALSE; 1046 } 1047 } 1048 1049 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; 1050 t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT; 1051 1052 t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK | 1053 RADEON_TXFORMAT_HEIGHT_MASK | 1054 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | 1055 RADEON_TXFORMAT_F5_WIDTH_MASK | 1056 RADEON_TXFORMAT_F5_HEIGHT_MASK); 1057 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) | 1058 (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT)); 1059 1060 t->tile_bits = 0; 1061 1062 if (t->base.Target == GL_TEXTURE_CUBE_MAP) { 1063 ASSERT(log2Width == log2Height); 1064 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) | 1065 (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) | 1066 /* don't think we need this bit, if it exists at all - fglrx does not set it */ 1067 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE)); 1068 t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) | 1069 (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) | 1070 (log2Width << RADEON_FACE_WIDTH_2_SHIFT) | 1071 (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) | 1072 (log2Width << RADEON_FACE_WIDTH_3_SHIFT) | 1073 (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) | 1074 (log2Width << RADEON_FACE_WIDTH_4_SHIFT) | 1075 (log2Height << RADEON_FACE_HEIGHT_4_SHIFT)); 1076 } 1077 1078 t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT) 1079 | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT)); 1080 1081 if ( !t->image_override ) { 1082 if (_mesa_is_format_compressed(firstImage->TexFormat)) 1083 t->pp_txpitch = (firstImage->Width + 63) & ~(63); 1084 else 1085 t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63); 1086 t->pp_txpitch -= 32; 1087 } 1088 1089 if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { 1090 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; 1091 } 1092 1093 return GL_TRUE; 1094} 1095 1096static GLboolean radeon_validate_texture(struct gl_context *ctx, struct gl_texture_object *texObj, int unit) 1097{ 1098 r100ContextPtr rmesa = R100_CONTEXT(ctx); 1099 radeonTexObj *t = radeon_tex_obj(texObj); 1100 int ret; 1101 1102 if (!radeon_validate_texture_miptree(ctx, texObj)) 1103 return GL_FALSE; 1104 1105 ret = setup_hardware_state(rmesa, t, unit); 1106 if (ret == GL_FALSE) 1107 return GL_FALSE; 1108 1109 /* yuv conversion only works in first unit */ 1110 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) 1111 return GL_FALSE; 1112 1113 RADEON_STATECHANGE( rmesa, ctx ); 1114 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= 1115 (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; 1116 RADEON_STATECHANGE( rmesa, tcl ); 1117 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); 1118 1119 rmesa->recheck_texgen[unit] = GL_TRUE; 1120 1121 import_tex_obj_state( rmesa, unit, t ); 1122 1123 if (rmesa->recheck_texgen[unit]) { 1124 GLboolean fallback = !radeon_validate_texgen( ctx, unit ); 1125 TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback); 1126 rmesa->recheck_texgen[unit] = 0; 1127 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; 1128 } 1129 1130 if ( ! radeonUpdateTextureEnv( ctx, unit ) ) { 1131 return GL_FALSE; 1132 } 1133 FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); 1134 1135 t->validated = GL_TRUE; 1136 return !t->border_fallback; 1137} 1138 1139static GLboolean radeonUpdateTextureUnit( struct gl_context *ctx, int unit ) 1140{ 1141 r100ContextPtr rmesa = R100_CONTEXT(ctx); 1142 1143 if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) { 1144 rmesa->state.texture.unit[unit].texobj = NULL; 1145 return GL_FALSE; 1146 } 1147 1148 if (!ctx->Texture.Unit[unit]._ReallyEnabled) { 1149 /* disable the unit */ 1150 disable_tex_obj_state(rmesa, unit); 1151 rmesa->state.texture.unit[unit].texobj = NULL; 1152 return GL_TRUE; 1153 } 1154 1155 if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { 1156 _mesa_warning(ctx, 1157 "failed to validate texture for unit %d.\n", 1158 unit); 1159 rmesa->state.texture.unit[unit].texobj = NULL; 1160 return GL_FALSE; 1161 } 1162 rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); 1163 return GL_TRUE; 1164} 1165 1166void radeonUpdateTextureState( struct gl_context *ctx ) 1167{ 1168 r100ContextPtr rmesa = R100_CONTEXT(ctx); 1169 GLboolean ok; 1170 1171 /* set the ctx all textures off */ 1172 RADEON_STATECHANGE( rmesa, ctx ); 1173 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK)); 1174 1175 ok = (radeonUpdateTextureUnit( ctx, 0 ) && 1176 radeonUpdateTextureUnit( ctx, 1 ) && 1177 radeonUpdateTextureUnit( ctx, 2 )); 1178 1179 FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok ); 1180 1181 if (rmesa->radeon.TclFallback) 1182 radeonChooseVertexState( ctx ); 1183} 1184