17a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# Core Solo / Core Duo possible unit masks 27a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 37a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:zero type:mandatory default:0x0 47a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0 No unit mask 57a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:one type:mandatory default:0x1 67a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x1 No unit mask 77a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:two type:mandatory default:0x2 87a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x2 No unit mask 97a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:x0f type:mandatory default:0xf 107a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0xf No unit mask 117a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:x20 type:mandatory default:0x20 127a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 No unit mask 137a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:x40 type:mandatory default:0x40 147a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x40 No unit mask 157a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:xc0 type:mandatory default:0xc0 167a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0xc0 No unit mask 177a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:nonhlt type:exclusive default:0x0 187a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0 Unhalted core cycles 197a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x1 Unhalted bus cycles 207a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x2 Unhalted bus cycles of this core while the other core is halted 217a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mesi type:bitmask default:0x0f 227a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 (M)odified cache state 237a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 (E)xclusive cache state 247a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 (S)hared cache state 257a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 (I)nvalid cache state 267a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0f All cache states 277a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 HW prefetched line only 287a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 all prefetched line w/o regarding mask 0x10. 297a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:est_trans type:exclusive default:0x00 307a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 any transitions 317a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions 327a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 any transactions 337a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:kni_prefetch type:exclusive default:0x0 347a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 prefetch NTA 357a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 prefetch T1 367a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 prefetch T2 377a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 weakly-ordered stores 387a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# this bitmask can seems weirds but is correct, note there is no way to only 397a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# count scalar SIMD instructions 407a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:sse_sse2_inst_retired type:exclusive default:0x0 417a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 SSE Packed Single 427a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 SSE Scalar-Single 437a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 SSE2 Packed-Double 447a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 SSE2 Scalar-Double 457a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mmx_instr_type_exec type:bitmask default:0x3f 467a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 MMX packed multiplies 477a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 MMX packed shifts 487a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 MMX pack operations 497a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 MMX unpack operations 507a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 MMX packed logical 517a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 MMX packed arithmetic 527a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x3f all of the above 537a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mmx_trans type:exclusive default:0x0 547a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 MMX->float operations 557a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 float->MMX operations 567a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:fused type:exclusive default:0x0 577a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 All fused micro-ops 587a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 Only load+Op micro-ops 597a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 Only std+sta micro-ops 607a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:dc_pend_miss type:exclusive default:0x0 617a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 Weighted cycles 627a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 Duration of cycles 637a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:sse_miss type:exclusive default:0x0 647a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 PREFETCHNTA 657a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 PREFETCHT1 667a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 PREFETCHT2 677a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 SSE streaming store instructions 68