1741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli/* 2741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli * MIPS CPU interrupt support. 3741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli * 4741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli */ 5741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 62ec695af7284adbedcdbc08a22d818b6bdd8990cDavid 'Digit' Turner#include "hw/hw.h" 7741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 8741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli/* Stub functions for hardware that don't exist. */ 9741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapallivoid pic_info(void) 10741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 11741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 12741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 13741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapallivoid irq_info(void) 14741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 15741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 16741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 17741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapallistatic void mips_cpu_irq_handler(void *opaque, int irq, int level) 18741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 19e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turner CPUOldState *env = (CPUOldState *)opaque; 20741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int causebit; 21741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 22741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (irq < 0 || 7 < irq) 23741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli cpu_abort(env, "mips_pic_cpu_handler: Bad interrupt line %d\n", 24741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli irq); 25741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 26741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli causebit = 0x00000100 << irq; 27741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (level) { 28741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli env->CP0_Cause |= causebit; 29bf7a22f3a6c38d359d2e933dec4706d1c7375f0aDavid 'Digit' Turner cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_HARD); 30741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } else { 31741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli env->CP0_Cause &= ~causebit; 32bf7a22f3a6c38d359d2e933dec4706d1c7375f0aDavid 'Digit' Turner cpu_reset_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_HARD); 33741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } 34741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 35741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 36e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerqemu_irq *mips_cpu_irq_init(CPUOldState *env) 37741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 38741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli return qemu_allocate_irqs(mips_cpu_irq_handler, env, 8); 39741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 40