1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef CPU_COMMON_H 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define CPU_COMMON_H 1 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "qemu-common.h" 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* CPU interfaces that are target independent. */ 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef CONFIG_USER_ONLY 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "exec/hwaddr.h" 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#endif 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef NEED_CPU_H 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "exec/poison.h" 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#endif 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "qemu/bswap.h" 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "qemu/queue.h" 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/** 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * CPUListState: 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * @cpu_fprintf: Print function. 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * @file: File to print to using @cpu_fprint. 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * State commonly used for iterating over CPU models. 25 */ 26typedef struct CPUListState { 27 fprintf_function cpu_fprintf; 28 FILE *file; 29} CPUListState; 30 31#if !defined(CONFIG_USER_ONLY) 32 33enum device_endian { 34 DEVICE_NATIVE_ENDIAN, 35 DEVICE_BIG_ENDIAN, 36 DEVICE_LITTLE_ENDIAN, 37}; 38 39/* address in the RAM (different from a physical address) */ 40#if defined(CONFIG_XEN_BACKEND) 41typedef uint64_t ram_addr_t; 42# define RAM_ADDR_MAX UINT64_MAX 43# define RAM_ADDR_FMT "%" PRIx64 44#else 45typedef uintptr_t ram_addr_t; 46# define RAM_ADDR_MAX UINTPTR_MAX 47# define RAM_ADDR_FMT "%" PRIxPTR 48#endif 49 50/* memory API */ 51 52/* MMIO pages are identified by a combination of an IO device index and 53 3 flags. The ROMD code stores the page ram offset in iotlb entry, 54 so only a limited number of ids are avaiable. */ 55 56#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) 57 58typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); 59typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); 60 61void cpu_register_physical_memory_log(hwaddr start_addr, 62 ram_addr_t size, 63 ram_addr_t phys_offset, 64 ram_addr_t region_offset, 65 bool log_dirty); 66 67static inline void cpu_register_physical_memory_offset(hwaddr start_addr, 68 ram_addr_t size, 69 ram_addr_t phys_offset, 70 ram_addr_t region_offset) 71{ 72 cpu_register_physical_memory_log(start_addr, size, phys_offset, 73 region_offset, false); 74} 75 76static inline void cpu_register_physical_memory(hwaddr start_addr, 77 ram_addr_t size, 78 ram_addr_t phys_offset) 79{ 80 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); 81} 82 83ram_addr_t cpu_get_physical_page_desc(hwaddr addr); 84ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, 85 ram_addr_t size, void *host); 86ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size); 87void qemu_ram_free(ram_addr_t addr); 88void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 89/* This should only be used for ram local to a device. */ 90void *qemu_get_ram_ptr(ram_addr_t addr); 91/* Same but slower, to use for migration, where the order of 92 * RAMBlocks must not change. */ 93void *qemu_safe_ram_ptr(ram_addr_t addr); 94/* This should not be used by devices. */ 95int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); 96ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 97 98int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, 99 CPUWriteMemoryFunc * const *mem_write, 100 void *opaque); 101void cpu_unregister_io_memory(int table_address); 102 103void cpu_physical_memory_rw(hwaddr addr, void *buf, 104 int len, int is_write); 105static inline void cpu_physical_memory_read(hwaddr addr, 106 void *buf, int len) 107{ 108 cpu_physical_memory_rw(addr, buf, len, 0); 109} 110static inline void cpu_physical_memory_write(hwaddr addr, 111 const void *buf, int len) 112{ 113 cpu_physical_memory_rw(addr, (void*)buf, len, 1); 114} 115void *cpu_physical_memory_map(hwaddr addr, 116 hwaddr *plen, 117 int is_write); 118void cpu_physical_memory_unmap(void *buffer, hwaddr len, 119 int is_write, hwaddr access_len); 120void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); 121 122uint32_t ldub_phys(hwaddr addr); 123uint32_t lduw_le_phys(hwaddr addr); 124uint32_t lduw_be_phys(hwaddr addr); 125uint32_t ldl_le_phys(hwaddr addr); 126uint32_t ldl_be_phys(hwaddr addr); 127uint64_t ldq_le_phys(hwaddr addr); 128uint64_t ldq_be_phys(hwaddr addr); 129void stb_phys(hwaddr addr, uint32_t val); 130void stw_le_phys(hwaddr addr, uint32_t val); 131void stw_be_phys(hwaddr addr, uint32_t val); 132void stl_le_phys(hwaddr addr, uint32_t val); 133void stl_be_phys(hwaddr addr, uint32_t val); 134void stq_le_phys(hwaddr addr, uint64_t val); 135void stq_be_phys(hwaddr addr, uint64_t val); 136 137#ifdef NEED_CPU_H 138uint32_t lduw_phys(hwaddr addr); 139uint32_t ldl_phys(hwaddr addr); 140uint64_t ldq_phys(hwaddr addr); 141void stl_phys_notdirty(hwaddr addr, uint32_t val); 142void stq_phys_notdirty(hwaddr addr, uint64_t val); 143void stw_phys(hwaddr addr, uint32_t val); 144void stl_phys(hwaddr addr, uint32_t val); 145void stq_phys(hwaddr addr, uint64_t val); 146#endif 147 148void cpu_physical_memory_write_rom(hwaddr addr, 149 const void *buf, int len); 150 151#define IO_MEM_SHIFT 3 152 153#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ 154#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ 155#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) 156#define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) 157 158/* Acts like a ROM when read and like a device when written. */ 159#define IO_MEM_ROMD (1) 160#define IO_MEM_SUBPAGE (2) 161#define IO_MEM_SUBWIDTH (4) 162 163#endif 164 165#endif /* !CPU_COMMON_H */ 166