1663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 2663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*---------------------------------------------------------------*/ 3663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*--- begin host_mips_defs.h ---*/ 4663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*---------------------------------------------------------------*/ 5663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 6663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* 7663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng This file is part of Valgrind, a dynamic binary instrumentation 8663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng framework. 9663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 10436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Copyright (C) 2010-2013 RT-RK 11663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng mips-valgrind@rt-rk.com 12663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 13663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng This program is free software; you can redistribute it and/or 14663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng modify it under the terms of the GNU General Public License as 15663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng published by the Free Software Foundation; either version 2 of the 16663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng License, or (at your option) any later version. 17663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 18663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng This program is distributed in the hope that it will be useful, but 19663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng WITHOUT ANY WARRANTY; without even the implied warranty of 20663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng General Public License for more details. 22663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 23663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng You should have received a copy of the GNU General Public License 24663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng along with this program; if not, write to the Free Software 25663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 26663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 02111-1307, USA. 27663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 28663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng The GNU General Public License is contained in the file COPYING. 29663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng*/ 30663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 31663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#ifndef __VEX_HOST_MIPS_DEFS_H 32663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define __VEX_HOST_MIPS_DEFS_H 33663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 34436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "libvex_basictypes.h" 35436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "libvex.h" /* VexArch */ 36436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#include "host_generic_regs.h" /* HReg */ 37436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 38663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Num registers used for function calls */ 39436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#if defined(VGP_mips32_linux) 40436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov/* a0, a1, a2, a3 */ 41663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define MIPS_N_REGPARMS 4 42436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#else 43436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov/* a0, a1, a2, a3, a4, a5, a6, a7 */ 44436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#define MIPS_N_REGPARMS 8 45436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#endif 46663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- Registers. --------- */ 47663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 48663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* The usual HReg abstraction. 49663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng There are 32 general purpose regs. 50663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng*/ 51663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 52663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void ppHRegMIPS(HReg, Bool); 53663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 54436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern HReg hregMIPS_GPR0(Bool mode64); /* scratch reg / zero reg */ 55436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern HReg hregMIPS_GPR1(Bool mode64); 56436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern HReg hregMIPS_GPR2(Bool mode64); 57663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR3(Bool mode64); 58663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR4(Bool mode64); 59663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR5(Bool mode64); 60663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR6(Bool mode64); 61663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR7(Bool mode64); 62663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR8(Bool mode64); 63663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR9(Bool mode64); 64663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR10(Bool mode64); 65663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR11(Bool mode64); 66663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR12(Bool mode64); 67663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR13(Bool mode64); 68663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR14(Bool mode64); 69663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR15(Bool mode64); 70663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR16(Bool mode64); 71663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR17(Bool mode64); 72663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR18(Bool mode64); 73663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR19(Bool mode64); 74663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR20(Bool mode64); 75663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR21(Bool mode64); 76663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR22(Bool mode64); 77436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern HReg hregMIPS_GPR23(Bool mode64); /* GuestStatePtr */ 78436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern HReg hregMIPS_GPR24(Bool mode64); 79663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR25(Bool mode64); 80663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR26(Bool mode64); 81663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR27(Bool mode64); 82663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR28(Bool mode64); 83663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR29(Bool mode64); 84663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR30(Bool mode64); 85663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_GPR31(Bool mode64); 86663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_PC(Bool mode64); 87663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 88663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_HI(Bool mode64); 89663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_LO(Bool mode64); 90663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 91663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F0(Bool mode64); 92663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F1(Bool mode64); 93663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F2(Bool mode64); 94663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F3(Bool mode64); 95663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F4(Bool mode64); 96663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F5(Bool mode64); 97663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F6(Bool mode64); 98663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F7(Bool mode64); 99663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F8(Bool mode64); 100663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F9(Bool mode64); 101663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F10(Bool mode64); 102663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F11(Bool mode64); 103663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F12(Bool mode64); 104663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F13(Bool mode64); 105663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F14(Bool mode64); 106663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F15(Bool mode64); 107663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F16(Bool mode64); 108663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F17(Bool mode64); 109663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F18(Bool mode64); 110663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F19(Bool mode64); 111663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F20(Bool mode64); 112663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F21(Bool mode64); 113663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F22(Bool mode64); 114663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F23(Bool mode64); 115663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F24(Bool mode64); 116663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F25(Bool mode64); 117663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F26(Bool mode64); 118663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F27(Bool mode64); 119663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F28(Bool mode64); 120663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F29(Bool mode64); 121663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F30(Bool mode64); 122663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_F31(Bool mode64); 123663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_FIR(void); 124663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_FCCR(void); 125663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_FEXR(void); 126663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_FENR(void); 127663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_FCSR(void); 128663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_COND(void); 129663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 130663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D0(void); 131663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D1(void); 132663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D2(void); 133663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D3(void); 134663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D4(void); 135663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D5(void); 136663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D6(void); 137663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D7(void); 138663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D8(void); 139663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D9(void); 140663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D10(void); 141663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D11(void); 142663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D12(void); 143663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D13(void); 144663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D14(void); 145663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HReg hregMIPS_D15(void); 146663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 147436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#define GuestStatePointer(_mode64) hregMIPS_GPR23(_mode64) 148663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 149663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define StackFramePointer(_mode64) hregMIPS_GPR30(_mode64) 150663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define LinkRegister(_mode64) hregMIPS_GPR31(_mode64) 151663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define StackPointer(_mode64) hregMIPS_GPR29(_mode64) 152663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define FCSR() hregMIPS_FCSR() 153663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define COND() hregMIPS_COND() 154663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 155663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define HIRegister(_mode64) hregMIPS_HI(_mode64) 156663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define LORegister(_mode64) hregMIPS_LO(_mode64) 157663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 158436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#if defined(VGP_mips64_linux) 159436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov/* a0, a1, a2, a3, a4, a5, a6, a7 */ 160436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#define MIPS_N_ARGREGS 8 161436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#elif defined(VGP_mips32_linux) 162663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* a0, a1, a2, a3 */ 163663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#define MIPS_N_ARGREGS 4 164436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov#endif 165663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 166663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- Condition codes, Intel encoding. --------- */ 167663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 168436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_EQ = 0, /* equal */ 169436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_NE = 1, /* not equal */ 170663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 171436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_HS = 2, /* >=u (higher or same) */ 172436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_LO = 3, /* <u (lower) */ 173663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 174436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_MI = 4, /* minus (negative) */ 175436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_PL = 5, /* plus (zero or +ve) */ 176663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 177436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_VS = 6, /* overflow */ 178436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_VC = 7, /* no overflow */ 179663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 180436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_HI = 8, /* >u (higher) */ 181436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_LS = 9, /* <=u (lower or same) */ 182663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 183436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_GE = 10, /* >=s (signed greater or equal) */ 184436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_LT = 11, /* <s (signed less than) */ 185663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 186436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_GT = 12, /* >s (signed greater) */ 187436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_LE = 13, /* <=s (signed less or equal) */ 188663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 189436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_AL = 14, /* always (unconditional) */ 190436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPScc_NV = 15 /* never (unconditional): */ 191663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSCondCode; 192663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 193436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSCondCode(MIPSCondCode); 194663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 195663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- Memory address expressions (amodes). --------- */ 196663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 197663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mam_IR, /* Immediate (signed 16-bit) + Reg */ 198663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mam_RR /* Reg1 + Reg2 */ 199663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSAModeTag; 200663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 201663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef struct { 202663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAModeTag tag; 203663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng union { 204663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 205663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg base; 206663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int index; 207663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } IR; 208663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 209663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg base; 210663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg index; 211663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } RR; 212663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Mam; 213663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSAMode; 214663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 215663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSAMode *MIPSAMode_IR(Int, HReg); 216663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSAMode *MIPSAMode_RR(HReg, HReg); 217663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 218663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSAMode *dopyMIPSAMode(MIPSAMode *); 219663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSAMode *nextMIPSAModeFloat(MIPSAMode *); 220663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSAMode *nextMIPSAModeInt(MIPSAMode *); 221663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 222663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void ppMIPSAMode(MIPSAMode *, Bool); 223663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 224663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- Operand, which can be a reg or a u16/s16. --------- */ 225663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* ("RH" == "Register or Halfword immediate") */ 226663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 227663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mrh_Imm, 228663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mrh_Reg 229663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSRHTag; 230663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 231663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef struct { 232663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSRHTag tag; 233663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng union { 234663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 235663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool syned; 236663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UShort imm16; 237663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Imm; 238663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 239663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg reg; 240663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Reg; 241663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Mrh; 242663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSRH; 243663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 244663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void ppMIPSRH(MIPSRH *, Bool); 245663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 246663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSRH *MIPSRH_Imm(Bool, UShort); 247663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSRH *MIPSRH_Reg(HReg); 248663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 249663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- Instructions. --------- */ 250663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 251663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*Tags for operations*/ 252663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 253663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 254663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 255663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mun_CLO, 256663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mun_CLZ, 257436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mun_DCLO, 258436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mun_DCLZ, 259663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mun_NOP, 260663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSUnaryOp; 261663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 262436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSUnaryOp(MIPSUnaryOp); 263663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 264663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 265663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 266663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 267663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 268663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Malu_INVALID, 269663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Malu_ADD, Malu_SUB, 270663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Malu_AND, Malu_OR, Malu_NOR, Malu_XOR, 271436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Malu_DADD, Malu_DSUB, 272436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Malu_SLT 273663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSAluOp; 274663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 275436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSAluOp(MIPSAluOp, 276663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool /* is the 2nd operand an immediate? */ ); 277663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 278663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 279663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 280663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mshft_INVALID, 281663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mshft_SLL, Mshft_SRL, 282663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mshft_SRA 283663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSShftOp; 284663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 285436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSShftOp(MIPSShftOp, 286663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool /* is the 2nd operand an immediate? */ , 287663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool /* is this a 32bit or 64bit op? */ ); 288663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 289663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 290663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 291663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Macc_ADD, 292663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Macc_SUB 293663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSMaccOp; 294663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 295436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSMaccOp(MIPSMaccOp, Bool); 296663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 297663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 298663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* ----- Instruction tags ----- */ 299663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 300436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_LI, /* load word (32/64-bit) immediate (fake insn) */ 301436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Alu, /* word add/sub/and/or/xor/nor/others? */ 302436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Shft, /* word sll/srl/sra */ 303436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Unary, /* clo, clz, nop, neg */ 304663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 305436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Cmp, /* word compare (fake insn) */ 306663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 307436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Mul, /* widening/non-widening multiply */ 308436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Div, /* div */ 309663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 310436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Call, /* call to address in register */ 311663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 312663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* The following 5 insns are mandated by translation chaining */ 313436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_XDirect, /* direct transfer to GA */ 314436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_XIndir, /* indirect transfer to GA */ 315436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_XAssisted, /* assisted transfer to GA */ 316436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_EvCheck, /* Event check */ 317436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_ProfInc, /* 64-bit profile counter increment */ 318436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 319436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_RdWrLR, /* Read/Write Link Register */ 320436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Mthi, /* Move to HI from GP register */ 321436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Mtlo, /* Move to LO from GP register */ 322436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Mfhi, /* Move from HI to GP register */ 323436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Mflo, /* Move from LO to GP register */ 324436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Macc, /* Multiply and accumulate */ 325436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 326436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Load, /* zero-extending load a 8|16|32 bit value from mem */ 327436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_Store, /* store a 8|16|32 bit value to mem */ 328436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_LoadL, /* mips Load Linked Word - LL */ 329436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_StoreC, /* mips Store Conditional Word - SC */ 330436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 331436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpUnary, /* FP unary op */ 332436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpBinary, /* FP binary op */ 333436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpTernary, /* FP ternary op */ 334436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpConvert, /* FP conversion op */ 335436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpMulAcc, /* FP multipy-accumulate style op */ 336436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpLdSt, /* FP load/store */ 337436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpSTFIW, /* stfiwx */ 338436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpRSP, /* FP round IEEE754 double to IEEE754 single */ 339436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpCftI, /* fcfid/fctid/fctiw */ 340436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpCMov, /* FP floating point conditional move */ 341436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_MtFCSR, /* set FCSR register */ 342436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_MfFCSR, /* get FCSR register */ 343436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpCompare, /* FP compare, generating value into int reg */ 344436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 345436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_FpGpMove, /* Move from/to fpr to/from gpr */ 346436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Min_MoveCond /* Move Conditional */ 347663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSInstrTag; 348663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 349663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* --------- */ 350663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef enum { 351663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mfp_INVALID, 352663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 353663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Ternary */ 354663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mfp_MADDD, Mfp_MSUBD, 355663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mfp_MADDS, Mfp_MSUBS, 356663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 357663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Binary */ 358663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mfp_ADDD, Mfp_SUBD, Mfp_MULD, Mfp_DIVD, 359436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_ADDS, Mfp_SUBS, Mfp_MULS, Mfp_DIVS, 360663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 361663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Unary */ 362436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_SQRTS, Mfp_SQRTD, 363663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Mfp_ABSS, Mfp_ABSD, Mfp_NEGS, Mfp_NEGD, Mfp_MOVS, Mfp_MOVD, 364436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 365436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov /* FP convert */ 366436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD, 367436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD, 368436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, 369436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_CVTDW, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, Mfp_CVTDS, 370436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_ROUNDLD, Mfp_FLOORLD, 371436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 372436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov /* FP compare */ 373436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Mfp_CMP_UN, Mfp_CMP_EQ, Mfp_CMP_LT, Mfp_CMP_NGT 374436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 375663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSFpOp; 376663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 377436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSFpOp(MIPSFpOp); 378436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 379436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov/* Move from/to fpr to/from gpr */ 380436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovtypedef enum { 381436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpGpMove_mfc1, /* Move Word From Floating Point - MIPS32 */ 382436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpGpMove_dmfc1, /* Doubleword Move from Floating Point - MIPS64 */ 383436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpGpMove_mtc1, /* Move Word to Floating Point - MIPS32 */ 384436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpGpMove_dmtc1 /* Doubleword Move to Floating Point - MIPS64 */ 385436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov} MIPSFpGpMoveOp; 386436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 387436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSFpGpMoveOp ( MIPSFpGpMoveOp ); 388436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 389436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov/* Move Conditional */ 390436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovtypedef enum { 391436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpMoveCond_movns, /* FP Move Conditional on Not Zero - MIPS32 */ 392436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MFpMoveCond_movnd, 393436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MMoveCond_movn /* Move Conditional on Not Zero */ 394436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov} MIPSMoveCondOp; 395436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 396436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern const HChar *showMIPSMoveCondOp ( MIPSMoveCondOp ); 397663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 398663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*--------- Structure for instructions ----------*/ 399663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Destinations are on the LEFT (first operand) */ 400663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 401663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengtypedef struct { 402663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSInstrTag tag; 403663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng union { 404663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Get a 32/64-bit literal into a register. 405663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng May turn into a number of real insns. */ 406663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 407663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 408663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng ULong imm; 409663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } LI; 410663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Integer add/sub/and/or/xor. Limitations: 411663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng - For add, the immediate, if it exists, is a signed 16. 412663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng - For sub, the immediate, if it exists, is a signed 16 413663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng which may not be -32768, since no such instruction 414663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng exists, and so we have to emit addi with +32768, but 415663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng that is not possible. 416663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng - For and/or/xor, the immediate, if it exists, 417663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng is an unsigned 16. 418663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng */ 419663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 420663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAluOp op; 421663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 422663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 423663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSRH *srcR; 424663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Alu; 425663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Integer shl/shr/sar. 426663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Limitations: the immediate, if it exists, 427663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng is a signed 5-bit value between 1 and 31 inclusive. 428663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng */ 429663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 430663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSShftOp op; 431663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool sz32; /* mode64 has both 32 and 64bit shft */ 432663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 433663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 434663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSRH *srcR; 435663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Shft; 436663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Clz, Clo, nop */ 437663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 438663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSUnaryOp op; 439663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 440663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 441663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Unary; 442663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Word compare. Fake instruction, used for basic block ending */ 443663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 444663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool syned; 445663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool sz32; 446663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 447663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 448663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 449663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 450663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond; 451663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Cmp; 452663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 453436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Bool widening; /* True => widening, False => non-widening */ 454436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Bool syned; /* signed/unsigned - meaningless if widenind = False */ 455663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool sz32; 456663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 457663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 458663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 459663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Mul; 460663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 461436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Bool syned; /* signed/unsigned - meaningless if widenind = False */ 462663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool sz32; 463663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 464663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 465663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Div; 466663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Pseudo-insn. Call target (an absolute address), on given 467663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng condition (which could be Mcc_ALWAYS). argiregs indicates 468436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov which of $4 .. $7 (mips32) or $4 .. $11 (mips64) 469663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng carries argument values for this call, 470436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov using a bit mask (1<<N is set if $N holds an arg, for N in 471436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov $4 .. $7 or $4 .. $11 inclusive). 472663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng If cond is != Mcc_ALWAYS, src is checked. 473663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Otherwise, unconditional call */ 474663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 475663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond; 476436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Addr64 target; 477663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UInt argiregs; 478663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 479436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov RetLoc rloc; /* where the return value will be */ 480663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Call; 481663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Update the guest EIP value, then exit requesting to chain 482663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng to it. May be conditional. Urr, use of Addr32 implicitly 483663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng assumes that wordsize(guest) == wordsize(host). */ 484663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 485436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Addr64 dstGA; /* next guest address */ 486436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSAMode* amPC; /* amode in guest state for PC */ 487436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSCondCode cond; /* can be MIPScc_AL */ 488436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov Bool toFastEP; /* chain to the slow or fast point? */ 489663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XDirect; 490663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Boring transfer to a guest address not known at JIT time. 491663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 492663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 493663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 494663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode* amPC; 495663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond; /* can be MIPScc_AL */ 496663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XIndir; 497663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Assisted transfer to a guest address, most general case. 498663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 499663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 500663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 501663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode* amPC; 502663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond; /* can be MIPScc_AL */ 503663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng IRJumpKind jk; 504663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XAssisted; 505663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Zero extending loads. Dst size is host word size */ 506663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 507663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar sz; /* 1|2|4|8 */ 508663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 509663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode *src; 510663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Load; 511663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* 64/32/16/8 bit stores */ 512663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 513663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar sz; /* 1|2|4|8 */ 514663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode *dst; 515663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 516663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Store; 517663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 518663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar sz; /* 4|8 */ 519663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 520663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode *src; 521663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } LoadL; 522663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 523663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar sz; /* 4|8 */ 524663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode *dst; 525663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 526663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } StoreC; 527663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Move from HI/LO register to GP register. */ 528663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 529663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 530663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } MfHL; 531663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 532663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Move to HI/LO register from GP register. */ 533663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 534663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 535663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } MtHL; 536663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 537663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Read/Write Link Register */ 538663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 539663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool wrLR; 540663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg gpr; 541663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } RdWrLR; 542663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 543663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* MIPS Multiply and accumulate instructions. */ 544663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 545663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSMaccOp op; 546663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool syned; 547663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 548663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 549663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 550663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Macc; 551663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 552663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* MIPS Floating point */ 553663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 554663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSFpOp op; 555663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 556663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 557663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpUnary; 558663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 559663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSFpOp op; 560663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 561663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 562663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 563663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpBinary; 564663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 565663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSFpOp op; 566663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 567436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src1; 568436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src2; 569436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src3; 570436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov } FpTernary; 571436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov struct { 572436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSFpOp op; 573436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg dst; 574663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcML; 575663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcMR; 576663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcAcc; 577663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpMulAcc; 578663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 579663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool isLoad; 580663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ 581663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg reg; 582663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode *addr; 583663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpLdSt; 584663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 585663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 586663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSFpOp op; 587663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 588663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 589663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpConvert; 590663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 591663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSFpOp op; 592663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 593663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcL; 594663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR; 595663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar cond1; 596663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } FpCompare; 597663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Move from GP register to FCSR register. */ 598663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 599663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg src; 600663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } MtFCSR; 601663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Move from FCSR register to GP register. */ 602663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 603663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dst; 604663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } MfFCSR; 605663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 606663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode* amCounter; 607663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode* amFailAddr; 608663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } EvCheck; 609663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 610663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* No fields. The address of the counter to inc is 611663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng installed later, post-translation, by patching it in, 612663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng as it is not known at translation time. */ 613663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } ProfInc; 614663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 615436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov /* Move from/to fpr to/from gpr */ 616436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov struct { 617436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSFpGpMoveOp op; 618436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg dst; 619436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src; 620436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov } FpGpMove; 621436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov struct { 622436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSMoveCondOp op; 623436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg dst; 624436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src; 625436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg cond; 626436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov } MoveCond; 627436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 628663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } Min; 629663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng} MIPSInstr; 630663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 631663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_LI(HReg, ULong); 632663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Alu(MIPSAluOp, HReg, HReg, MIPSRH *); 633663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *); 634663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src); 635663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode); 636663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 637663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Mul(Bool syned, Bool hi32, Bool sz32, HReg, 638663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg, HReg); 639663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg); 640663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg); 641663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg); 642663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 643663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src, 644663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64); 645663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src, 646663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64); 647663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 648663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src, 649663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64); 650663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, 651663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64); 652663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 653436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_Call ( MIPSCondCode, Addr64, UInt, HReg, RetLoc ); 654436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_CallAlways ( MIPSCondCode, Addr64, UInt, RetLoc ); 655663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 656436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_XDirect ( Addr64 dstGA, MIPSAMode* amPC, 657436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov MIPSCondCode cond, Bool toFastEP ); 658663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_XIndir(HReg dstGA, MIPSAMode* amPC, 659663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond); 660663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_XAssisted(HReg dstGA, MIPSAMode* amPC, 661663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSCondCode cond, IRJumpKind jk); 662663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 663663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src); 664663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL, 665663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcR); 666436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1, 667436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src2, HReg src3 ); 668663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src); 669663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, 670436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg srcR); 671663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML, 672663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg srcMR, HReg srcAcc); 673663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *); 674663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpSTFIW(HReg addr, HReg data); 675663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpRSP(HReg dst, HReg src); 676663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src); 677663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpCMov(MIPSCondCode, HReg dst, HReg src); 678663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_MtFCSR(HReg src); 679663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_MfFCSR(HReg dst); 680663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_FpCmp(HReg dst, HReg srcL, HReg srcR); 681663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 682663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Mfhi(HReg dst); 683663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Mflo(HReg dst); 684663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Mthi(HReg src); 685663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_Mtlo(HReg src); 686663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 687663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr); 688663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 689436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_MoveCond ( MIPSMoveCondOp op, HReg dst, 690436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov HReg src, HReg cond ); 691436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanov 692436e89c602e787e7a27dd6624b09beed41a0da8aDmitriy Ivanovextern MIPSInstr *MIPSInstr_FpGpMove ( MIPSFpGpMoveOp op, HReg dst, HReg src ); 693663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 694663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_EvCheck(MIPSAMode* amCounter, 695663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng MIPSAMode* amFailAddr ); 696663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern MIPSInstr *MIPSInstr_ProfInc( void ); 697663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 698663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void ppMIPSInstr(MIPSInstr *, Bool mode64); 699663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 700663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Some functions that insulate the register allocator from details 701663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng of the underlying instruction set. */ 702663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void getRegUsage_MIPSInstr (HRegUsage *, MIPSInstr *, Bool); 703663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64); 704663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Bool isMove_MIPSInstr (MIPSInstr *, HReg *, HReg *); 705663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, 706663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar* buf, Int nbuf, MIPSInstr* i, 707663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64, 708663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_slowEP, 709663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_fastEP, 710663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xindir, 711663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xassisted ); 712663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 713663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 714663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg rreg, Int offset, Bool); 715663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 716663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg rreg, Int offset, Bool); 717663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 718663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern void getAllocableRegs_MIPS (Int *, HReg **, Bool mode64); 719663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HInstrArray *iselSB_MIPS ( IRSB*, 720663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArch, 721663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArchInfo*, 722663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexAbiInfo*, 723663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_Counter, 724663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_FailAddr, 725663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool chainingAllowed, 726663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool addProfInc, 727663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Addr64 max_ga ); 728663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 729663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* How big is an event check? This is kind of a kludge because it 730663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, 731663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng and so assumes that they are both <= 128, and so can use the short 732663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng offset encoding. This is all checked with assertions, so in the 733663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng worst case we will merely assert at startup. */ 734663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int evCheckSzB_MIPS ( void ); 735663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 736663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Perform a chaining and unchaining of an XDirect jump. */ 737663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange chainXDirect_MIPS ( void* place_to_chain, 738663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_EXPECTED, 739663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to, 740663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64 ); 741663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 742663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain, 743663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to_EXPECTED, 744663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me, 745663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64 ); 746663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 747663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Patch the counter location into an existing ProfInc point. */ 748663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange patchProfInc_MIPS ( void* place_to_patch, 749663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng ULong* location_of_counter, 750663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64 ); 751663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 752663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng#endif /* ndef __LIBVEX_HOST_MIPS_HDEFS_H */ 753663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 754663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*---------------------------------------------------------------*/ 755663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*--- end host-mips_defs.h ---*/ 756663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/*---------------------------------------------------------------*/ 757