libvex_guest_offsets.h revision 663860b1408516d02ebfcb3a9999a134e6cfb223 
1#define OFFSET_x86_EAX 8
2#define OFFSET_x86_EBX 20
3#define OFFSET_x86_ECX 12
4#define OFFSET_x86_EDX 16
5#define OFFSET_x86_ESI 32
6#define OFFSET_x86_EDI 36
7#define OFFSET_x86_EBP 28
8#define OFFSET_x86_ESP 24
9#define OFFSET_x86_EIP 68
10#define OFFSET_x86_CS 288
11#define OFFSET_x86_DS 290
12#define OFFSET_x86_ES 292
13#define OFFSET_x86_FS 294
14#define OFFSET_x86_GS 296
15#define OFFSET_x86_SS 298
16#define OFFSET_amd64_RAX 16
17#define OFFSET_amd64_RBX 40
18#define OFFSET_amd64_RCX 24
19#define OFFSET_amd64_RDX 32
20#define OFFSET_amd64_RSI 64
21#define OFFSET_amd64_RDI 72
22#define OFFSET_amd64_RSP 48
23#define OFFSET_amd64_RBP 56
24#define OFFSET_amd64_R8 80
25#define OFFSET_amd64_R9 88
26#define OFFSET_amd64_R10 96
27#define OFFSET_amd64_R11 104
28#define OFFSET_amd64_R12 112
29#define OFFSET_amd64_R13 120
30#define OFFSET_amd64_R14 128
31#define OFFSET_amd64_R15 136
32#define OFFSET_amd64_RIP 184
33#define OFFSET_ppc32_GPR0 16
34#define OFFSET_ppc32_GPR1 20
35#define OFFSET_ppc32_GPR2 24
36#define OFFSET_ppc32_GPR3 28
37#define OFFSET_ppc32_GPR4 32
38#define OFFSET_ppc32_GPR5 36
39#define OFFSET_ppc32_GPR6 40
40#define OFFSET_ppc32_GPR7 44
41#define OFFSET_ppc32_GPR8 48
42#define OFFSET_ppc32_GPR9 52
43#define OFFSET_ppc32_GPR10 56
44#define OFFSET_ppc32_CIA 1168
45#define OFFSET_ppc32_CR0_0 1185
46#define OFFSET_ppc64_GPR0 16
47#define OFFSET_ppc64_GPR1 24
48#define OFFSET_ppc64_GPR2 32
49#define OFFSET_ppc64_GPR3 40
50#define OFFSET_ppc64_GPR4 48
51#define OFFSET_ppc64_GPR5 56
52#define OFFSET_ppc64_GPR6 64
53#define OFFSET_ppc64_GPR7 72
54#define OFFSET_ppc64_GPR8 80
55#define OFFSET_ppc64_GPR9 88
56#define OFFSET_ppc64_GPR10 96
57#define OFFSET_ppc64_CIA 1296
58#define OFFSET_ppc64_CR0_0 1325
59#define OFFSET_arm_R0 8
60#define OFFSET_arm_R1 12
61#define OFFSET_arm_R2 16
62#define OFFSET_arm_R3 20
63#define OFFSET_arm_R4 24
64#define OFFSET_arm_R5 28
65#define OFFSET_arm_R7 36
66#define OFFSET_arm_R13 60
67#define OFFSET_arm_R14 64
68#define OFFSET_arm_R15T 68
69#define OFFSET_s390x_r2 208
70#define OFFSET_s390x_r3 216
71#define OFFSET_s390x_r4 224
72#define OFFSET_s390x_r5 232
73#define OFFSET_s390x_r6 240
74#define OFFSET_s390x_r7 248
75#define OFFSET_s390x_r15 312
76#define OFFSET_s390x_IA 336
77#define OFFSET_s390x_SYSNO 344
78#define OFFSET_s390x_IP_AT_SYSCALL 408
79#define OFFSET_s390x_fpc 328
80#define OFFSET_s390x_CC_OP 352
81#define OFFSET_s390x_CC_DEP1 360
82#define OFFSET_s390x_CC_DEP2 368
83#define OFFSET_s390x_CC_NDEP 376
84#define OFFSET_mips32_r0 0
85#define OFFSET_mips32_r1 4
86#define OFFSET_mips32_r2 8
87#define OFFSET_mips32_r3 12
88#define OFFSET_mips32_r4 16
89#define OFFSET_mips32_r5 20
90#define OFFSET_mips32_r6 24
91#define OFFSET_mips32_r7 28
92#define OFFSET_mips32_r8 32
93#define OFFSET_mips32_r9 36
94#define OFFSET_mips32_r10 40
95#define OFFSET_mips32_r11 44
96#define OFFSET_mips32_r12 48
97#define OFFSET_mips32_r13 52
98#define OFFSET_mips32_r14 56
99#define OFFSET_mips32_r15 60
100#define OFFSET_mips32_r15 60
101#define OFFSET_mips32_r17 68
102#define OFFSET_mips32_r18 72
103#define OFFSET_mips32_r19 76
104#define OFFSET_mips32_r20 80
105#define OFFSET_mips32_r21 84
106#define OFFSET_mips32_r22 88
107#define OFFSET_mips32_r23 92
108#define OFFSET_mips32_r24 96
109#define OFFSET_mips32_r25 100
110#define OFFSET_mips32_r26 104
111#define OFFSET_mips32_r27 108
112#define OFFSET_mips32_r28 112
113#define OFFSET_mips32_r29 116
114#define OFFSET_mips32_r30 120
115#define OFFSET_mips32_r31 124
116#define OFFSET_mips32_PC 128
117#define OFFSET_mips32_HI 132
118#define OFFSET_mips32_LO 136
119