macro_int.h revision 436e89c602e787e7a27dd6624b09beed41a0da8a
1ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton#define TEST1(instruction, RSval, RTval, RD, RS, RT) \ 2ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton{ \ 3ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long out; \ 4ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton __asm__ __volatile__( \ 5ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RS", %1" "\n\t" \ 6ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RT", %2" "\n\t" \ 7ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RD", $zero" "\n\t" \ 8ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction "\n\t" \ 9ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move %0, $"#RD "\n\t" \ 10ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "=r" (out) \ 11ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "r" (RSval), "r" (RTval) \ 12ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : #RD, #RS, #RT \ 13ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton ); \ 14ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne printf("%s :: rd 0x%llx, rs 0x%llx, rt 0x%llx\n", \ 15ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction, out, (long long) RSval, \ 16ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton (long long) RTval); \ 17ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton} 18ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton 19ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton#define TEST2(instruction, RSval, imm, RT, RS) \ 20ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton{ \ 21ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long out; \ 22ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton __asm__ __volatile__( \ 23ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RS", %1" "\n\t" \ 24ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RT", $zero" "\n\t" \ 25ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction "\n\t" \ 26d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton "move %0, $"#RT "\n\t" \ 27ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "=r" (out) \ 28ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "r" (RSval) \ 29ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : #RT, #RS \ 30ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton ); \ 31d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton printf("%s :: rt 0x%llx, rs 0x%llx, imm 0x%04x\n", \ 32d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton instruction, out, (long long) RSval, imm); \ 33d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton} 34d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton 35d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton#define TEST3(instruction, RSval, RD, RS) \ 36d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton{ \ 37d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton unsigned long long out; \ 38d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton __asm__ __volatile__( \ 39d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton "move $"#RS", %1" "\n\t" \ 40d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton "move $"#RD", $zero" "\n\t" \ 41d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton instruction "\n\t" \ 42d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton "move %0, $"#RD "\n\t" \ 43d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton : "=r" (out) \ 44d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton : "r" (RSval) \ 45d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton : #RD, #RS \ 46d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton ); \ 47d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton printf("%s :: rd 0x%llx, rs 0x%llx\n", \ 48d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton instruction, out, (long long) RSval); \ 49d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton} 50d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton 51d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton#define TEST4(instruction, RSval, RTval, RS, RT) \ 52d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton{ \ 53d5b3e3c662c967feb455a01f307c3f4bc318eec9Greg Clayton unsigned long long HI; \ 54ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long LO; \ 55ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton __asm__ __volatile__( \ 56ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RS", %2" "\n\t" \ 57ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RT", %3" "\n\t" \ 58ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mthi $zero" "\n\t" \ 59ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mtlo $zero" "\n\t" \ 60ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction "\n\t" \ 61ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mfhi %0" "\n\t" \ 62ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mflo %1" "\n\t" \ 63ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "=r" (HI), "=r" (LO) \ 64ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : "r" (RSval), "r"(RTval) \ 65ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton : #RS, #RT \ 66ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton ); \ 67ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton printf("%s :: rs 0x%llx, rt 0x%llx, HI 0x%llx, LO 0x%llx\n", \ 68ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction, (long long) RSval, (long long) RTval, HI, LO); \ 69ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton} 70ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton 71ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton#define TEST5(instruction, RSval, RTval, RS, RT) \ 72ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton{ \ 73ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long HI; \ 74ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long LO; \ 75ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton __asm__ __volatile__( \ 76ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RS", %2" "\n\t" \ 77ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "move $"#RT", %3" "\n\t" \ 78ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mthi $"#RS "\n\t" \ 79ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton "mtlo $"#RT "\n\t" \ 80ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction "\n\t" \ 81ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne "mfhi %0" "\n\t" \ 82ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne "mflo %1" "\n\t" \ 83ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne : "=r" (HI), "=r" (LO) \ 84ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne : "r" (RSval), "r"(RTval) \ 85ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne : #RS, #RT \ 86ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne ); \ 87ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne printf("%s :: rs 0x%llx, rt 0x%llx, HI 0x%llx, LO 0x%llx\n", \ 88ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne instruction, (long long) RSval, (long long) RTval, HI, LO); \ 89ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne} 90ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne 91ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne#define TEST6(instruction, imm, RT) \ 92ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton{ \ 93ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton unsigned long long out; \ 94ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton __asm__ __volatile__( \ 95ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne "move $"#RT", $zero" "\n\t" \ 96ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction "\n\t" \ 97ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne "move %0, $"#RT "\n\t" \ 98ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne : "=r" (out) : \ 99ea6d783624f0b7dcbf3773cb31d6e4fcd4f93b6cPeter Collingbourne : #RT \ 100ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton ); \ 101ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton printf("%s :: rt 0x%llx, imm 0x%04x\n", \ 102ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton instruction, out, imm); \ 103ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton} 104ac304e4cbd1005210661720d5f2232f85b08c195Greg Clayton