condloadstore.c revision b32f58018498ea2225959b0ba11c18f0c433deef 
1#include <stdio.h>
2#include <stdlib.h>
3#include "opcodes.h"
4
5#define LOAD_REG_MEM(insn, s, ccset, initial, mask)	\
6({							\
7	register unsigned long target asm("1") = initial;	\
8	unsigned long source = s;			\
9	register unsigned long *addr asm("5") = &source;	\
10	unsigned int a,b;				\
11	switch(ccset) {					\
12	case 0: a = 0; b = 0; break;			\
13	case 1: a = 1; b = 0; break;			\
14	case 2: a = 0xffffffff; b = 1; break;		\
15	case 3: a = 0xffffffff; b = 2; break;		\
16	default: abort();				\
17	}						\
18	asm volatile(	"alr %1, %3\n"  /* set cc */	\
19			insn(1,mask,5,000,00)		\
20			: "+d" (target), "+d" (a)	\
21			: "Q" (source), "d" (b), "d"(addr)		\
22			: "cc");			\
23	printf(#insn " %16.16lX into %16.16lX if mask"	\
24		"%d for cc %d: %16.16lX\n",s, initial,	\
25		 0x##mask, ccset, target);		\
26})
27
28
29#define LOAD_REG_REG(insn, s, ccset, initial, mask)	\
30({							\
31	register unsigned long target asm("1") = initial;	\
32	register unsigned long source asm("2")= s;		\
33	unsigned int a,b;				\
34	switch(ccset) {					\
35	case 0: a = 0; b = 0; break;			\
36	case 1: a = 1; b = 0; break;			\
37	case 2: a = 0xffffffff; b = 1; break;		\
38	case 3: a = 0xffffffff; b = 2; break;		\
39	default: abort();				\
40	}						\
41	asm volatile(	"alr %1, %3\n"  /* set cc */	\
42			insn(mask,1,2)			\
43			: "+d" (target), "+d" (a)	\
44			: "d" (source), "d" (b)		\
45			: "cc");			\
46	printf(#insn " %16.16lX into %16.16lX if mask"	\
47		"%d for cc %d: %16.16lX\n",s, initial,	\
48		 0x##mask, ccset, target);		\
49})
50
51#define STORE_REG_REG(insn, s, ccset, initial, mask)	\
52({							\
53	unsigned long target = initial;			\
54	register unsigned long source asm("1") = s;	\
55	register unsigned long *addr asm("5") = &target;	\
56	unsigned int a,b;				\
57	switch(ccset) {					\
58	case 0: a = 0; b = 0; break;			\
59	case 1: a = 1; b = 0; break;			\
60	case 2: a = 0xffffffff; b = 1; break;		\
61	case 3: a = 0xffffffff; b = 2; break;		\
62	default: abort();				\
63	}						\
64	asm volatile(	"alr %1, %3\n"  /* set cc */	\
65			insn(1,mask,5,000,00)		\
66			: "+Q" (target), "+d" (a)	\
67			: "d" (source), "d" (b), "d"(addr)		\
68			: "cc");			\
69	printf(#insn " %16.16lX into %16.16lX if mask"	\
70		"%d for cc %d: %16.16lX\n",s, initial,	\
71		 0x##mask, ccset, target);		\
72})
73
74
75#define INSNVALCCINIT(insn, value, ccset, INIT, FUNC)	\
76({							\
77	FUNC(insn, value, ccset, INIT, 0);		\
78	FUNC(insn, value, ccset, INIT, 1);		\
79	FUNC(insn, value, ccset, INIT, 2);		\
80	FUNC(insn, value, ccset, INIT, 3);		\
81	FUNC(insn, value, ccset, INIT, 4);		\
82	FUNC(insn, value, ccset, INIT, 5);		\
83	FUNC(insn, value, ccset, INIT, 6);		\
84	FUNC(insn, value, ccset, INIT, 7);		\
85	FUNC(insn, value, ccset, INIT, 8);		\
86	FUNC(insn, value, ccset, INIT, 9);		\
87	FUNC(insn, value, ccset, INIT, A);		\
88	FUNC(insn, value, ccset, INIT, B);		\
89	FUNC(insn, value, ccset, INIT, C);		\
90	FUNC(insn, value, ccset, INIT, D);		\
91	FUNC(insn, value, ccset, INIT, E);		\
92	FUNC(insn, value, ccset, INIT, F);		\
93})
94
95
96
97
98#define INSNVALCC(insn, value, ccset, FUNC)		\
99({							\
100	INSNVALCCINIT(insn, value, ccset, 0UL, FUNC);	\
101	INSNVALCCINIT(insn, value, ccset, 0xffffffffffffffffUL, FUNC);	\
102})
103
104#define INSNVAL(insn, value, FUNC)			\
105({							\
106	INSNVALCC(insn, value, 0, FUNC);		\
107	INSNVALCC(insn, value, 1, FUNC);		\
108	INSNVALCC(insn, value, 2, FUNC);		\
109	INSNVALCC(insn, value, 3, FUNC);		\
110})
111
112#define DO_INSN(insn, FUNC)				\
113({							\
114	INSNVAL(insn, 0UL, FUNC);			\
115	INSNVAL(insn, 0xffffffffUL, FUNC);		\
116	INSNVAL(insn, 0xffffffffffffffffUL, FUNC);	\
117	INSNVAL(insn, 0xffffffff00000000UL, FUNC);	\
118})
119
120int main()
121{
122  	DO_INSN(LOC, LOAD_REG_MEM);
123  	DO_INSN(LOCG, LOAD_REG_MEM);
124	DO_INSN(LOCR, LOAD_REG_REG);
125	DO_INSN(LOCGR, LOAD_REG_REG);
126	DO_INSN(STOC, STORE_REG_REG);
127	DO_INSN(STOCG, STORE_REG_REG);
128	return 0;
129}
130