1// Copyright 2013, ARM Limited
2// All rights reserved.
3//
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5// modification, are permitted provided that the following conditions are met:
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15//
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26
27#ifndef VIXL_CPU_A64_H
28#define VIXL_CPU_A64_H
29
30#include "globals-vixl.h"
31
32namespace vixl {
33
34class CPU {
35 public:
36  // Initialise CPU support.
37  static void SetUp();
38
39  // Ensures the data at a given address and with a given size is the same for
40  // the I and D caches. I and D caches are not automatically coherent on ARM
41  // so this operation is required before any dynamically generated code can
42  // safely run.
43  static void EnsureIAndDCacheCoherency(void *address, size_t length);
44
45 private:
46  // Return the content of the cache type register.
47  static uint32_t GetCacheType();
48
49  // I and D cache line size in bytes.
50  static unsigned icache_line_size_;
51  static unsigned dcache_line_size_;
52};
53
54}  // namespace vixl
55
56#endif  // VIXL_CPU_A64_H
57