1ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Copyright 2013, ARM Limited 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#ifndef VIXL_CPU_A64_H 28ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#define VIXL_CPU_A64_H 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30bc4afbd2754e20d14114e4ba83f9035b26ab701dSerban Constantinescu#include "globals-vixl.h" 31ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 32ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 33ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 34ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlclass CPU { 35ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl public: 36ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Initialise CPU support. 37ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static void SetUp(); 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 39ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensures the data at a given address and with a given size is the same for 40ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the I and D caches. I and D caches are not automatically coherent on ARM 41ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // so this operation is required before any dynamically generated code can 42ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // safely run. 43ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static void EnsureIAndDCacheCoherency(void *address, size_t length); 44ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 45ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl private: 46ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Return the content of the cache type register. 47ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static uint32_t GetCacheType(); 48ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 49ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // I and D cache line size in bytes. 50ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static unsigned icache_line_size_; 51ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static unsigned dcache_line_size_; 52ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 53ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 54ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 55ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 56ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl#endif // VIXL_CPU_A64_H 57