1f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/* 2f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Copyright © 2008 Intel Corporation 3f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 4f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Permission is hereby granted, free of charge, to any person obtaining a 5f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * copy of this software and associated documentation files (the "Software"), 6f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * to deal in the Software without restriction, including without limitation 7f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * and/or sell copies of the Software, and to permit persons to whom the 9f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Software is furnished to do so, subject to the following conditions: 10f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 11f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * The above copyright notice and this permission notice (including the next 12f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * paragraph) shall be included in all copies or substantial portions of the 13f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Software. 14f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 15f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * IN THE SOFTWARE. 22f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 23f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Authors: 24f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Eric Anholt <eric@anholt.net> 25f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 26f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 27f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 28f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/** 29f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * @file intel_bufmgr.h 30f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 31f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Public definitions of Intel-specific bufmgr functions. 32f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 33f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 34f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#ifndef INTEL_BUFMGR_H 35f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define INTEL_BUFMGR_H 36f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 37f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#include <stdint.h> 38f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 39f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryutypedef struct _drm_intel_bufmgr drm_intel_bufmgr; 40f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryutypedef struct _drm_intel_bo drm_intel_bo; 41f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 42f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryustruct _drm_intel_bo { 43f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** 44f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Size in bytes of the buffer object. 45f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 46f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * The size may be larger than the size originally requested for the 47f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * allocation, such as being aligned to page size. 48f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 49f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size; 50f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** 51f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Alignment requirement for object 52f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * 53f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Used for GTT mapping & pinning the object. 54f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 55f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long align; 56f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 57f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** 58f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Card virtual address (offset from the beginning of the aperture) for the 59f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * object. Only valid while validated. 60f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 61f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long offset; 62f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** 63f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * Virtual address for accessing the buffer data. Only valid while mapped. 64f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 65f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *virtual; 66f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 67f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** Buffer manager context associated with this buffer object */ 68f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu drm_intel_bufmgr *bufmgr; 69f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 70f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu /** 71f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * MM-specific handle for accessing object 72f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 73f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu int handle; 74f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu}; 75f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 76f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, 77f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size, unsigned int alignment); 78f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 79f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu const char *name, 80f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size, 81f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned int alignment); 82f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bo_reference(drm_intel_bo *bo); 83f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bo_unreference(drm_intel_bo *bo); 84f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_map(drm_intel_bo *bo, int write_enable); 85f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_unmap(drm_intel_bo *bo); 86f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 87f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, 88f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size, const void *data); 89f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, 90f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size, void *data); 91f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bo_wait_rendering(drm_intel_bo *bo); 92f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 93f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); 94f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); 95f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_exec(drm_intel_bo *bo, int used, 96f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu drm_clip_rect_t *cliprects, int num_cliprects, 97f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu int DR4); 98f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bufmgr_check_aperture_space(drm_intel_bo **bo_array, int count); 99f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 100f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 101f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu drm_intel_bo *target_bo, uint32_t target_offset, 102f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu uint32_t read_domains, uint32_t write_domain); 103f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); 104f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_unpin(drm_intel_bo *bo); 105f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, 106f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu uint32_t stride); 107f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, 108f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu uint32_t *swizzle_mode); 109f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name); 110f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_busy(drm_intel_bo *bo); 111f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 112f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_bo_disable_reuse(drm_intel_bo *bo); 113f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 114f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/* drm_intel_bufmgr_gem.c */ 115f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); 116f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 117f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu const char *name, 118f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned int handle); 119f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); 120f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 121f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 122f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); 123f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 124f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuint drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); 125f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 126f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/* drm_intel_bufmgr_fake.c */ 127f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, 128f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long low_offset, 129f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *low_virtual, 130f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long size, 131f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu volatile unsigned int *last_dispatch); 132f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, 133f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu volatile unsigned int *last_dispatch); 134f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, 135f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu int (*exec)(drm_intel_bo *bo, 136f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned int used, 137f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *priv), 138f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *priv); 139f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, 140f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned int (*emit)(void *priv), 141f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void (*wait)(unsigned int fence, 142f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *priv), 143f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *priv); 144f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryudrm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, 145f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu const char *name, 146f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu unsigned long offset, unsigned long size, 147f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *virtual); 148f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, 149f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void (*invalidate_cb)(drm_intel_bo *bo, 150f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *ptr), 151f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu void *ptr); 152f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 153f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); 154f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryuvoid drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); 155f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 156f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/** @{ Compatibility defines to keep old code building despite the symbol rename 157f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu * from dri_* to drm_intel_* 158f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu */ 159f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo drm_intel_bo 160f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bufmgr drm_intel_bufmgr 161f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_alloc drm_intel_bo_alloc 162f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_reference drm_intel_bo_reference 163f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_unreference drm_intel_bo_unreference 164f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_map drm_intel_bo_map 165f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_unmap drm_intel_bo_unmap 166f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_subdata drm_intel_bo_subdata 167f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_get_subdata drm_intel_bo_get_subdata 168f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_wait_rendering drm_intel_bo_wait_rendering 169f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug 170f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bufmgr_destroy drm_intel_bufmgr_destroy 171f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_exec drm_intel_bo_exec 172f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space 173f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ 174f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu reloc_offset, target_bo) \ 175f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ 176f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu target_bo, target_offset, \ 177f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu read, write); 178f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_pin drm_intel_bo_pin 179f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_unpin drm_intel_bo_unpin 180f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_get_tiling drm_intel_bo_get_tiling 181f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0) 182f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define dri_bo_flink drm_intel_bo_flink 183f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init 184f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name 185f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse 186f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init 187f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch 188f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback 189f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback 190f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static 191f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store 192f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take 193f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all 194f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 195f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu/** @{ */ 196f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 197f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu#endif /* INTEL_BUFMGR_H */ 198f0352d4fde4ec179ffe04c3f834199d3bad36087Ho-Eun Ryu 199