hwc.cpp revision 45709e7bcbc0f8e73ca4251eb2d3c74341b8f72e
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 59const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 60 sizeof(AVAILABLE_GSC_UNITS[0]); 61 62struct exynos5_hwc_composer_device_1_t; 63 64struct exynos5_gsc_map_t { 65 enum { 66 GSC_NONE = 0, 67 GSC_M2M, 68 // TODO: GSC_LOCAL_PATH 69 } mode; 70 int idx; 71}; 72 73struct exynos5_hwc_post_data_t { 74 int overlay_map[NUM_HW_WINDOWS]; 75 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 76 size_t fb_window; 77}; 78 79const size_t NUM_GSC_DST_BUFS = 3; 80struct exynos5_gsc_data_t { 81 void *gsc; 82 exynos_gsc_img src_cfg; 83 exynos_gsc_img dst_cfg; 84 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 85 size_t current_buf; 86}; 87 88struct exynos5_hwc_composer_device_1_t { 89 hwc_composer_device_1_t base; 90 91 int fd; 92 int vsync_fd; 93 exynos5_hwc_post_data_t bufs; 94 95 const private_module_t *gralloc_module; 96 alloc_device_t *alloc_device; 97 const hwc_procs_t *procs; 98 pthread_t vsync_thread; 99 int force_gpu; 100 101 int32_t xres; 102 int32_t yres; 103 int32_t xdpi; 104 int32_t ydpi; 105 int32_t vsync_period; 106 107 int hdmi_mixer0; 108 int hdmi_layer0; 109 int hdmi_layer1; 110 bool hdmi_hpd; 111 bool hdmi_enabled; 112 bool hdmi_blanked; 113 void *hdmi_gsc; 114 int hdmi_w; 115 int hdmi_h; 116 exynos_gsc_img hdmi_src; 117 exynos_gsc_img hdmi_dst; 118 119 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 120 121 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 122 size_t last_fb_window; 123 const void *last_handles[NUM_HW_WINDOWS]; 124 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 125}; 126 127static void dump_handle(private_handle_t *h) 128{ 129 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 130 h->format, h->width, h->height, h->stride, h->vstride); 131} 132 133static void dump_layer(hwc_layer_1_t const *l) 134{ 135 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 136 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 137 l->compositionType, l->flags, l->handle, l->transform, 138 l->blending, 139 l->sourceCrop.left, 140 l->sourceCrop.top, 141 l->sourceCrop.right, 142 l->sourceCrop.bottom, 143 l->displayFrame.left, 144 l->displayFrame.top, 145 l->displayFrame.right, 146 l->displayFrame.bottom); 147 148 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 149 dump_handle(private_handle_t::dynamicCast(l->handle)); 150} 151 152static void dump_config(s3c_fb_win_config &c) 153{ 154 ALOGV("\tstate = %u", c.state); 155 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 156 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 157 "x = %d, y = %d, w = %u, h = %u, " 158 "format = %u, blending = %u", 159 c.fd, c.offset, c.stride, 160 c.x, c.y, c.w, c.h, 161 c.format, c.blending); 162 } 163 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 164 ALOGV("\t\tcolor = %u", c.color); 165 } 166} 167 168static void dump_gsc_img(exynos_gsc_img &c) 169{ 170 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 171 c.x, c.y, c.w, c.h, c.fw, c.fh); 172 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 173 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 174} 175 176inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 177inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 178template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 179template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 180 181static bool is_transformed(const hwc_layer_1_t &layer) 182{ 183 return layer.transform != 0; 184} 185 186static bool is_rotated(const hwc_layer_1_t &layer) 187{ 188 return (layer.transform & HAL_TRANSFORM_ROT_90) || 189 (layer.transform & HAL_TRANSFORM_ROT_180); 190} 191 192static bool is_scaled(const hwc_layer_1_t &layer) 193{ 194 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 195 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 196} 197 198static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 199{ 200 return c1.x != c2.x || 201 c1.y != c2.y || 202 c1.w != c2.w || 203 c1.h != c2.h || 204 c1.format != c2.format || 205 c1.rot != c2.rot || 206 c1.cacheable != c2.cacheable || 207 c1.drmMode != c2.drmMode; 208} 209 210static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 211{ 212 return gsc_dst_cfg_changed(c1, c2) || 213 c1.fw != c2.fw || 214 c1.fh != c2.fh; 215} 216 217static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 218{ 219 switch (format) { 220 case HAL_PIXEL_FORMAT_RGBA_8888: 221 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 222 case HAL_PIXEL_FORMAT_RGBX_8888: 223 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 224 case HAL_PIXEL_FORMAT_RGBA_5551: 225 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 226 case HAL_PIXEL_FORMAT_RGB_565: 227 return S3C_FB_PIXEL_FORMAT_RGB_565; 228 case HAL_PIXEL_FORMAT_BGRA_8888: 229 return S3C_FB_PIXEL_FORMAT_BGRA_8888; 230 default: 231 return S3C_FB_PIXEL_FORMAT_MAX; 232 } 233} 234 235static bool exynos5_format_is_supported(int format) 236{ 237 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 238} 239 240static bool exynos5_format_is_rgb(int format) 241{ 242 switch (format) { 243 case HAL_PIXEL_FORMAT_RGBA_8888: 244 case HAL_PIXEL_FORMAT_RGBX_8888: 245 case HAL_PIXEL_FORMAT_RGB_888: 246 case HAL_PIXEL_FORMAT_RGB_565: 247 case HAL_PIXEL_FORMAT_BGRA_8888: 248 case HAL_PIXEL_FORMAT_RGBA_5551: 249 case HAL_PIXEL_FORMAT_RGBA_4444: 250 return true; 251 252 default: 253 return false; 254 } 255} 256 257static bool exynos5_format_is_supported_by_gscaler(int format) 258{ 259 switch (format) { 260 case HAL_PIXEL_FORMAT_RGBX_8888: 261 case HAL_PIXEL_FORMAT_RGB_565: 262 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 263 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 264 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 265 return true; 266 267 default: 268 return false; 269 } 270} 271 272static bool exynos5_format_is_ycrcb(int format) 273{ 274 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 275} 276 277static bool exynos5_format_requires_gscaler(int format) 278{ 279 return (exynos5_format_is_supported_by_gscaler(format) && 280 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565)); 281} 282 283static uint8_t exynos5_format_to_bpp(int format) 284{ 285 switch (format) { 286 case HAL_PIXEL_FORMAT_RGBA_8888: 287 case HAL_PIXEL_FORMAT_RGBX_8888: 288 case HAL_PIXEL_FORMAT_BGRA_8888: 289 return 32; 290 291 case HAL_PIXEL_FORMAT_RGBA_5551: 292 case HAL_PIXEL_FORMAT_RGBA_4444: 293 case HAL_PIXEL_FORMAT_RGB_565: 294 return 16; 295 296 default: 297 ALOGW("unrecognized pixel format %u", format); 298 return 0; 299 } 300} 301 302static bool is_x_aligned(const hwc_layer_1_t &layer, int format) 303{ 304 if (!exynos5_format_is_supported(format)) 305 return true; 306 307 uint8_t bpp = exynos5_format_to_bpp(format); 308 uint8_t pixel_alignment = 32 / bpp; 309 310 return (layer.displayFrame.left % pixel_alignment) == 0 && 311 (layer.displayFrame.right % pixel_alignment) == 0; 312} 313 314static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 315 bool local_path) 316{ 317 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 318 319 int max_w = is_rotated(layer) ? 2048 : 4800; 320 int max_h = is_rotated(layer) ? 2048 : 3344; 321 322 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 323 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 324 // HAL_TRANSFORM_ROT_180 325 326 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 327 int dest_w, dest_h; 328 if (rot90or270) { 329 dest_w = HEIGHT(layer.displayFrame); 330 dest_h = WIDTH(layer.displayFrame); 331 } else { 332 dest_w = WIDTH(layer.displayFrame); 333 dest_h = HEIGHT(layer.displayFrame); 334 } 335 int max_downscale = local_path ? 4 : 16; 336 const int max_upscale = 8; 337 338 return exynos5_format_is_supported_by_gscaler(format) && 339 handle->stride <= max_w && 340 handle->stride % GSC_W_ALIGNMENT == 0 && 341 src_w <= dest_w * max_downscale && 342 dest_w <= src_w * max_upscale && 343 handle->vstride <= max_h && 344 handle->vstride % GSC_H_ALIGNMENT == 0 && 345 src_h <= dest_h * max_downscale && 346 dest_h <= src_h * max_upscale && 347 // per 46.2 348 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 349 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 350 // per 46.3.1.6 351} 352 353static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 354{ 355 return exynos5_format_requires_gscaler(format) || is_scaled(layer) 356 || is_transformed(layer) || !is_x_aligned(layer, format); 357} 358 359int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 360{ 361 struct v4l2_dv_preset preset; 362 struct v4l2_dv_enum_preset enum_preset; 363 int index = 0; 364 bool found = false; 365 int ret; 366 367 if (ioctl(dev->hdmi_layer0, VIDIOC_G_DV_PRESET, &preset) < 0) { 368 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 369 return -1; 370 } 371 372 while (true) { 373 enum_preset.index = index++; 374 ret = ioctl(dev->hdmi_layer0, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 375 376 if (ret < 0) { 377 if (errno == EINVAL) 378 break; 379 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 380 return -1; 381 } 382 383 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 384 __func__, enum_preset.index, enum_preset.preset, 385 enum_preset.width, enum_preset.height, enum_preset.name); 386 387 if (preset.preset == enum_preset.preset) { 388 dev->hdmi_w = enum_preset.width; 389 dev->hdmi_h = enum_preset.height; 390 found = true; 391 } 392 } 393 394 return found ? 0 : -1; 395} 396 397static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 398{ 399 switch (blending) { 400 case HWC_BLENDING_NONE: 401 return S3C_FB_BLENDING_NONE; 402 case HWC_BLENDING_PREMULT: 403 return S3C_FB_BLENDING_PREMULT; 404 case HWC_BLENDING_COVERAGE: 405 return S3C_FB_BLENDING_COVERAGE; 406 407 default: 408 return S3C_FB_BLENDING_MAX; 409 } 410} 411 412static bool exynos5_blending_is_supported(int32_t blending) 413{ 414 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 415} 416 417static int hdmi_start_background(struct exynos5_hwc_composer_device_1_t *dev) 418{ 419 struct v4l2_requestbuffers reqbuf; 420 struct v4l2_subdev_format sd_fmt; 421 struct v4l2_subdev_crop sd_crop; 422 struct v4l2_format fmt; 423 struct v4l2_buffer buffer; 424 struct v4l2_plane planes[1]; 425 426 memset(&reqbuf, 0, sizeof(reqbuf)); 427 memset(&sd_fmt, 0, sizeof(sd_fmt)); 428 memset(&sd_crop, 0, sizeof(sd_crop)); 429 memset(&fmt, 0, sizeof(fmt)); 430 memset(&buffer, 0, sizeof(buffer)); 431 memset(planes, 0, sizeof(planes)); 432 433 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SINK; 434 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 435 sd_fmt.format.width = 1; 436 sd_fmt.format.height = 1; 437 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 438 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 439 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 440 return -1; 441 } 442 443 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SINK; 444 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 445 sd_crop.rect.left = 0; 446 sd_crop.rect.top = 0; 447 sd_crop.rect.width = 1; 448 sd_crop.rect.height = 1; 449 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 450 ALOGE("%s: set_crop failed pad=%d", __func__, sd_crop.pad); 451 return -1; 452 } 453 454 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 455 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 456 sd_fmt.format.width = dev->hdmi_w; 457 sd_fmt.format.height = dev->hdmi_h; 458 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 459 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 460 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 461 return -1; 462 } 463 464 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 465 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 466 sd_crop.rect.left = 0; 467 sd_crop.rect.top = 0; 468 sd_crop.rect.width = 1; 469 sd_crop.rect.height = 1; 470 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 471 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 472 return -1; 473 } 474 475 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 476 fmt.fmt.pix_mp.width = 1; 477 fmt.fmt.pix_mp.height = 1; 478 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 479 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 480 fmt.fmt.pix_mp.num_planes = 1; 481 if (exynos_v4l2_s_fmt(dev->hdmi_layer1, &fmt) < 0) { 482 ALOGE("%s::videodev set format failed", __func__); 483 return -1; 484 } 485 486 reqbuf.count = 1; 487 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 488 reqbuf.memory = V4L2_MEMORY_MMAP; 489 490 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 491 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 492 return -1; 493 } 494 495 if (reqbuf.count != 1) { 496 ALOGE("%s: didn't get buffer", __func__); 497 return -1; 498 } 499 500 memset(&buffer, 0, sizeof(buffer)); 501 buffer.type = reqbuf.type; 502 buffer.memory = V4L2_MEMORY_MMAP; 503 buffer.length = 1; 504 buffer.m.planes = planes; 505 if (exynos_v4l2_querybuf(dev->hdmi_layer1, &buffer) < 0) { 506 ALOGE("%s: exynos_v4l2_querybuf failed %d", __func__, errno); 507 return -1; 508 } 509 510 void *start = mmap(NULL, planes[0].length, PROT_READ | PROT_WRITE, 511 MAP_SHARED, dev->hdmi_layer1, planes[0].m.mem_offset); 512 if (start == MAP_FAILED) { 513 ALOGE("%s: mmap failed %d", __func__, errno); 514 return -1; 515 } 516 517 memset(start, 0, planes[0].length); 518 519 munmap(start, planes[0].length); 520 521 if (exynos_v4l2_qbuf(dev->hdmi_layer1, &buffer) < 0) { 522 ALOGE("%s: exynos_v4l2_qbuf failed %d", __func__, errno); 523 return -1; 524 } 525 526 if (exynos_v4l2_streamon(dev->hdmi_layer1, buffer.type) < 0) { 527 ALOGE("%s:stream on failed", __func__); 528 return -1; 529 } 530 531 if (exynos_v4l2_s_ctrl(dev->hdmi_layer1, V4L2_CID_TV_LAYER_PRIO, 0) < 0) { 532 ALOGE("%s: s_ctrl LAYER_PRIO failed", __func__); 533 return -1; 534 } 535 536 return 0; 537} 538 539static int hdmi_stop_background(struct exynos5_hwc_composer_device_1_t *dev) 540{ 541 struct v4l2_requestbuffers reqbuf; 542 543 if (exynos_v4l2_streamoff(dev->hdmi_layer1, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) { 544 ALOGE("%s:stream off failed", __func__); 545 return -1; 546 } 547 548 memset(&reqbuf, 0, sizeof(reqbuf)); 549 reqbuf.count = 0; 550 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 551 reqbuf.memory = V4L2_MEMORY_MMAP; 552 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 553 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 554 return -1; 555 } 556 557 return 0; 558} 559 560static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 561{ 562 if (dev->hdmi_enabled) 563 return 0; 564 565 if (dev->hdmi_blanked) 566 return 0; 567 568 dev->hdmi_gsc = exynos_gsc_create_exclusive(3, GSC_OUTPUT_MODE, GSC_OUT_TV); 569 if (!dev->hdmi_gsc) { 570 ALOGE("%s: exynos_gsc_create_exclusive failed", __func__); 571 return -ENODEV; 572 } 573 574 memset(&dev->hdmi_src, 0, sizeof(dev->hdmi_src)); 575 576 if (hdmi_start_background(dev) < 0) { 577 ALOGE("%s: hdmi_start_background failed", __func__); 578 return -1; 579 } 580 581 dev->hdmi_enabled = true; 582 return 0; 583} 584 585static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 586{ 587 if (!dev->hdmi_enabled) 588 return; 589 exynos_gsc_destroy(dev->hdmi_gsc); 590 hdmi_stop_background(dev); 591 dev->hdmi_gsc = NULL; 592 dev->hdmi_enabled = false; 593} 594 595static int hdmi_configure_fblayer(struct exynos5_hwc_composer_device_1_t *dev, 596 hwc_layer_1_t &layer) 597{ 598 int ret = 0; 599 exynos_gsc_img src_cfg, dst_cfg; 600 memset(&src_cfg, 0, sizeof(src_cfg)); 601 memset(&dst_cfg, 0, sizeof(dst_cfg)); 602 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 603 604 src_cfg.x = layer.sourceCrop.left; 605 src_cfg.y = layer.sourceCrop.top; 606 src_cfg.w = WIDTH(layer.sourceCrop); 607 src_cfg.fw = h->stride; 608 src_cfg.h = HEIGHT(layer.sourceCrop); 609 src_cfg.fh = h->vstride; 610 src_cfg.format = HAL_PIXEL_FORMAT_RGBX_8888; 611 src_cfg.yaddr = h->fd; 612 src_cfg.acquireFenceFd = layer.acquireFenceFd; 613 614 dst_cfg.w = dev->hdmi_w; 615 dst_cfg.fw = dev->hdmi_w; 616 dst_cfg.h = dev->hdmi_h; 617 dst_cfg.fh = dev->hdmi_h; 618 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 619 dst_cfg.rot = layer.transform; 620 621 if (gsc_src_cfg_changed(src_cfg, dev->hdmi_src) 622 || gsc_dst_cfg_changed(dst_cfg, dev->hdmi_dst)) { 623 624 ALOGV("HDMI source config:"); 625 dump_gsc_img(src_cfg); 626 ALOGV("HDMI dest config:"); 627 dump_gsc_img(dst_cfg); 628 629 exynos_gsc_stop_exclusive(dev->hdmi_gsc); 630 631 ret = exynos_gsc_config_exclusive(dev->hdmi_gsc, &src_cfg, &dst_cfg); 632 if (ret < 0) { 633 ALOGE("%s: exynos_gsc_config_exclusive failed %d", __func__, ret); 634 goto err; 635 } 636 637 dev->hdmi_src = src_cfg; 638 dev->hdmi_dst = dst_cfg; 639 } 640 641 ret = exynos_gsc_run_exclusive(dev->hdmi_gsc, &src_cfg, NULL); 642 if (ret < 0) { 643 ALOGE("%s: exynos_gsc_run_exclusive failed %d", __func__, ret); 644 goto err; 645 } 646 647 layer.releaseFenceFd = src_cfg.releaseFenceFd; 648 649err: 650 if (layer.acquireFenceFd >= 0) 651 close(layer.acquireFenceFd); 652 return ret; 653} 654 655bool exynos5_is_offscreen(hwc_layer_1_t &layer, 656 struct exynos5_hwc_composer_device_1_t *pdev) 657{ 658 return layer.sourceCrop.left > pdev->xres || 659 layer.sourceCrop.right < 0 || 660 layer.sourceCrop.top > pdev->yres || 661 layer.sourceCrop.bottom < 0; 662} 663 664bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 665 struct exynos5_hwc_composer_device_1_t *pdev) 666{ 667 if (layer.flags & HWC_SKIP_LAYER) { 668 ALOGV("\tlayer %u: skipping", i); 669 return false; 670 } 671 672 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 673 674 if (!handle) { 675 ALOGV("\tlayer %u: handle is NULL", i); 676 return false; 677 } 678 if (!exynos5_format_is_rgb(handle->format) && 679 !exynos5_format_is_supported_by_gscaler(handle->format)) { 680 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 681 return false; 682 } 683 684 if (exynos5_requires_gscaler(layer, handle->format)) { 685 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 686 ALOGV("\tlayer %u: gscaler required but not supported", i); 687 return false; 688 } 689 } else { 690 if (!exynos5_format_is_supported(handle->format)) { 691 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 692 return false; 693 } 694 } 695 if (!exynos5_blending_is_supported(layer.blending)) { 696 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 697 return false; 698 } 699 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 700 ALOGW("\tlayer %u: off-screen", i); 701 return false; 702 } 703 704 return true; 705} 706 707inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 708{ 709 return !(r1.left > r2.right || 710 r1.right < r2.left || 711 r1.top > r2.bottom || 712 r1.bottom < r2.top); 713} 714 715inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 716{ 717 hwc_rect i; 718 i.top = max(r1.top, r2.top); 719 i.bottom = min(r1.bottom, r2.bottom); 720 i.left = max(r1.left, r2.left); 721 i.right = min(r1.right, r2.right); 722 return i; 723} 724 725static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 726 hwc_display_contents_1_t* contents) 727{ 728 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 729 730 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 731 732 bool force_fb = pdev->force_gpu; 733 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 734 pdev->bufs.overlay_map[i] = -1; 735 736 bool fb_needed = false; 737 size_t first_fb = 0, last_fb = 0; 738 739 // find unsupported overlays 740 for (size_t i = 0; i < contents->numHwLayers; i++) { 741 hwc_layer_1_t &layer = contents->hwLayers[i]; 742 743 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 744 ALOGV("\tlayer %u: framebuffer target", i); 745 continue; 746 } 747 748 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 749 ALOGV("\tlayer %u: background supported", i); 750 dump_layer(&contents->hwLayers[i]); 751 continue; 752 } 753 754 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 755 !force_fb) { 756 ALOGV("\tlayer %u: overlay supported", i); 757 layer.compositionType = HWC_OVERLAY; 758 dump_layer(&contents->hwLayers[i]); 759 continue; 760 } 761 762 if (!fb_needed) { 763 first_fb = i; 764 fb_needed = true; 765 } 766 last_fb = i; 767 layer.compositionType = HWC_FRAMEBUFFER; 768 769 dump_layer(&contents->hwLayers[i]); 770 } 771 772 // can't composite overlays sandwiched between framebuffers 773 if (fb_needed) 774 for (size_t i = first_fb; i < last_fb; i++) 775 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 776 777 // Incrementally try to add our supported layers to hardware windows. 778 // If adding a layer would violate a hardware constraint, force it 779 // into the framebuffer and try again. (Revisiting the entire list is 780 // necessary because adding a layer to the framebuffer can cause other 781 // windows to retroactively violate constraints.) 782 bool changed; 783 do { 784 android::Vector<hwc_rect> rects; 785 android::Vector<hwc_rect> overlaps; 786 size_t pixels_left, windows_left, gsc_left = NUM_GSC_UNITS; 787 788 if (fb_needed) { 789 hwc_rect_t fb_rect; 790 fb_rect.top = fb_rect.left = 0; 791 fb_rect.right = pdev->xres - 1; 792 fb_rect.bottom = pdev->yres - 1; 793 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 794 windows_left = NUM_HW_WINDOWS - 1; 795 rects.push_back(fb_rect); 796 } 797 else { 798 pixels_left = MAX_PIXELS; 799 windows_left = NUM_HW_WINDOWS; 800 } 801 if (pdev->hdmi_enabled) 802 gsc_left--; 803 804 changed = false; 805 806 for (size_t i = 0; i < contents->numHwLayers; i++) { 807 hwc_layer_1_t &layer = contents->hwLayers[i]; 808 if ((layer.flags & HWC_SKIP_LAYER) || 809 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 810 continue; 811 812 private_handle_t *handle = private_handle_t::dynamicCast( 813 layer.handle); 814 815 // we've already accounted for the framebuffer above 816 if (layer.compositionType == HWC_FRAMEBUFFER) 817 continue; 818 819 // only layer 0 can be HWC_BACKGROUND, so we can 820 // unconditionally allow it without extra checks 821 if (layer.compositionType == HWC_BACKGROUND) { 822 windows_left--; 823 continue; 824 } 825 826 size_t pixels_needed = WIDTH(layer.displayFrame) * 827 HEIGHT(layer.displayFrame); 828 bool can_compose = windows_left && pixels_needed <= pixels_left; 829 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 830 if (gsc_required) 831 can_compose = can_compose && gsc_left; 832 833 // hwc_rect_t right and bottom values are normally exclusive; 834 // the intersection logic is simpler if we make them inclusive 835 hwc_rect_t visible_rect = layer.displayFrame; 836 visible_rect.right--; visible_rect.bottom--; 837 838 // no more than 2 layers can overlap on a given pixel 839 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 840 if (intersect(visible_rect, overlaps.itemAt(j))) 841 can_compose = false; 842 } 843 844 if (!can_compose) { 845 layer.compositionType = HWC_FRAMEBUFFER; 846 if (!fb_needed) { 847 first_fb = last_fb = i; 848 fb_needed = true; 849 } 850 else { 851 first_fb = min(i, first_fb); 852 last_fb = max(i, last_fb); 853 } 854 changed = true; 855 break; 856 } 857 858 for (size_t j = 0; j < rects.size(); j++) { 859 const hwc_rect_t &other_rect = rects.itemAt(j); 860 if (intersect(visible_rect, other_rect)) 861 overlaps.push_back(intersection(visible_rect, other_rect)); 862 } 863 rects.push_back(visible_rect); 864 pixels_left -= pixels_needed; 865 windows_left--; 866 if (gsc_required) 867 gsc_left--; 868 } 869 870 if (changed) 871 for (size_t i = first_fb; i < last_fb; i++) 872 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 873 } while(changed); 874 875 unsigned int nextWindow = 0; 876 int nextGsc = 0; 877 878 for (size_t i = 0; i < contents->numHwLayers; i++) { 879 hwc_layer_1_t &layer = contents->hwLayers[i]; 880 881 if (fb_needed && i == first_fb) { 882 ALOGV("assigning framebuffer to window %u\n", 883 nextWindow); 884 nextWindow++; 885 continue; 886 } 887 888 if (layer.compositionType != HWC_FRAMEBUFFER && 889 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 890 ALOGV("assigning layer %u to window %u", i, nextWindow); 891 pdev->bufs.overlay_map[nextWindow] = i; 892 if (layer.compositionType == HWC_OVERLAY) { 893 private_handle_t *handle = 894 private_handle_t::dynamicCast(layer.handle); 895 if (exynos5_requires_gscaler(layer, handle->format)) { 896 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[nextGsc]); 897 pdev->bufs.gsc_map[nextWindow].mode = 898 exynos5_gsc_map_t::GSC_M2M; 899 pdev->bufs.gsc_map[nextWindow].idx = nextGsc++; 900 } 901 } 902 nextWindow++; 903 } 904 } 905 906 for (size_t i = nextGsc; i < NUM_GSC_UNITS; i++) { 907 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 908 if (pdev->gsc[i].dst_buf[j]) 909 pdev->alloc_device->free(pdev->alloc_device, 910 pdev->gsc[i].dst_buf[j]); 911 memset(&pdev->gsc[i], 0, sizeof(pdev->gsc[i])); 912 } 913 914 if (fb_needed) 915 pdev->bufs.fb_window = first_fb; 916 else 917 pdev->bufs.fb_window = NO_FB_NEEDED; 918 919 return 0; 920} 921 922static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 923 hwc_display_contents_1_t* contents) 924{ 925 ALOGV("preparing %u layers for HDMI", contents->numHwLayers); 926 927 for (size_t i = 0; i < contents->numHwLayers; i++) { 928 hwc_layer_1_t &layer = contents->hwLayers[i]; 929 930 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 931 ALOGV("\tlayer %u: framebuffer target", i); 932 dump_layer(&layer); 933 continue; 934 } 935 936 if (layer.compositionType == HWC_BACKGROUND) { 937 ALOGV("\tlayer %u: background layer", i); 938 dump_layer(&layer); 939 continue; 940 } 941 942 layer.compositionType = HWC_FRAMEBUFFER; 943 dump_layer(&layer); 944 } 945 946 return 0; 947} 948 949static int exynos5_prepare(hwc_composer_device_1_t *dev, 950 size_t numDisplays, hwc_display_contents_1_t** displays) 951{ 952 if (!numDisplays || !displays) 953 return 0; 954 955 exynos5_hwc_composer_device_1_t *pdev = 956 (exynos5_hwc_composer_device_1_t *)dev; 957 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 958 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 959 960 if (pdev->hdmi_hpd) { 961 hdmi_enable(pdev); 962 } else { 963 hdmi_disable(pdev); 964 } 965 966 if (fimd_contents) { 967 int err = exynos5_prepare_fimd(pdev, fimd_contents); 968 if (err) 969 return err; 970 } 971 972 if (hdmi_contents) { 973 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 974 if (err) 975 return err; 976 } 977 978 return 0; 979} 980 981static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 982 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 983 int gsc_idx) 984{ 985 ALOGV("configuring gscaler %u for memory-to-memory", gsc_idx); 986 987 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 988 buffer_handle_t dst_buf; 989 private_handle_t *dst_handle; 990 int ret = 0; 991 992 exynos_gsc_img src_cfg, dst_cfg; 993 memset(&src_cfg, 0, sizeof(src_cfg)); 994 memset(&dst_cfg, 0, sizeof(dst_cfg)); 995 996 src_cfg.x = layer.sourceCrop.left; 997 src_cfg.y = layer.sourceCrop.top; 998 src_cfg.w = WIDTH(layer.sourceCrop); 999 src_cfg.fw = src_handle->stride; 1000 src_cfg.h = HEIGHT(layer.sourceCrop); 1001 src_cfg.fh = src_handle->vstride; 1002 src_cfg.yaddr = src_handle->fd; 1003 if (exynos5_format_is_ycrcb(src_handle->format)) { 1004 src_cfg.uaddr = src_handle->fd2; 1005 src_cfg.vaddr = src_handle->fd1; 1006 } else { 1007 src_cfg.uaddr = src_handle->fd1; 1008 src_cfg.vaddr = src_handle->fd2; 1009 } 1010 src_cfg.format = src_handle->format; 1011 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1012 1013 dst_cfg.x = 0; 1014 dst_cfg.y = 0; 1015 dst_cfg.w = WIDTH(layer.displayFrame); 1016 dst_cfg.h = HEIGHT(layer.displayFrame); 1017 dst_cfg.rot = layer.transform; 1018 dst_cfg.drmMode = src_cfg.drmMode; 1019 if (exynos5_format_is_rgb(src_handle->format)) 1020 dst_cfg.format = HAL_PIXEL_FORMAT_RGBX_8888; 1021 else 1022 dst_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 1023 // RGB surfaces are already in the right color order from the GPU, 1024 // YUV surfaces need the Gscaler to swap R & B 1025 1026 ALOGV("source configuration:"); 1027 dump_gsc_img(src_cfg); 1028 1029 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1030 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 1031 int dst_stride; 1032 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1033 GRALLOC_USAGE_SW_WRITE_NEVER | 1034 GRALLOC_USAGE_HW_COMPOSER; 1035 1036 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1037 usage |= GRALLOC_USAGE_PROTECTED; 1038 1039 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1040 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1041 1042 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1043 if (gsc_data->dst_buf[i]) { 1044 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1045 gsc_data->dst_buf[i] = NULL; 1046 } 1047 1048 int ret = alloc_device->alloc(alloc_device, w, h, 1049 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1050 &dst_stride); 1051 if (ret < 0) { 1052 ALOGE("failed to allocate destination buffer: %s", 1053 strerror(-ret)); 1054 goto err_alloc; 1055 } 1056 } 1057 1058 gsc_data->current_buf = 0; 1059 } 1060 1061 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1062 dst_handle = private_handle_t::dynamicCast(dst_buf); 1063 1064 dst_cfg.fw = dst_handle->stride; 1065 dst_cfg.fh = dst_handle->vstride; 1066 dst_cfg.yaddr = dst_handle->fd; 1067 1068 ALOGV("destination configuration:"); 1069 dump_gsc_img(dst_cfg); 1070 1071 gsc_data->gsc = exynos_gsc_create_exclusive(AVAILABLE_GSC_UNITS[gsc_idx], 1072 GSC_M2M_MODE, GSC_DUMMY); 1073 if (!gsc_data->gsc) { 1074 ALOGE("failed to create gscaler handle"); 1075 ret = -1; 1076 goto err_alloc; 1077 } 1078 1079 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1080 if (ret < 0) { 1081 ALOGE("failed to configure gscaler %u", gsc_idx); 1082 goto err_gsc_config; 1083 } 1084 1085 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1086 if (ret < 0) { 1087 ALOGE("failed to run gscaler %u", gsc_idx); 1088 goto err_gsc_config; 1089 } 1090 1091 gsc_data->src_cfg = src_cfg; 1092 gsc_data->dst_cfg = dst_cfg; 1093 1094 return 0; 1095 1096err_gsc_config: 1097 exynos_gsc_destroy(gsc_data->gsc); 1098 gsc_data->gsc = NULL; 1099err_alloc: 1100 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1101 if (gsc_data->dst_buf[i]) { 1102 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1103 gsc_data->dst_buf[i] = NULL; 1104 } 1105 } 1106 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1107 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1108 return ret; 1109} 1110 1111static void exynos5_config_handle(private_handle_t *handle, 1112 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1113 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1114 exynos5_hwc_composer_device_1_t *pdev) 1115{ 1116 uint32_t x, y; 1117 uint32_t w = WIDTH(displayFrame); 1118 uint32_t h = HEIGHT(displayFrame); 1119 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1120 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1121 1122 if (displayFrame.left < 0) { 1123 unsigned int crop = -displayFrame.left; 1124 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1125 crop); 1126 x = 0; 1127 w -= crop; 1128 offset += crop * bpp / 8; 1129 } else { 1130 x = displayFrame.left; 1131 } 1132 1133 if (displayFrame.right > pdev->xres) { 1134 unsigned int crop = displayFrame.right - pdev->xres; 1135 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1136 crop); 1137 w -= crop; 1138 } 1139 1140 if (displayFrame.top < 0) { 1141 unsigned int crop = -displayFrame.top; 1142 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1143 crop); 1144 y = 0; 1145 h -= crop; 1146 offset += handle->stride * crop * bpp / 8; 1147 } else { 1148 y = displayFrame.top; 1149 } 1150 1151 if (displayFrame.bottom > pdev->yres) { 1152 int crop = displayFrame.bottom - pdev->yres; 1153 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1154 crop); 1155 h -= crop; 1156 } 1157 1158 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1159 cfg.fd = handle->fd; 1160 cfg.x = x; 1161 cfg.y = y; 1162 cfg.w = w; 1163 cfg.h = h; 1164 cfg.format = exynos5_format_to_s3c_format(handle->format); 1165 cfg.offset = offset; 1166 cfg.stride = handle->stride * bpp / 8; 1167 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1168 cfg.fence_fd = fence_fd; 1169} 1170 1171static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1172 exynos5_hwc_composer_device_1_t *pdev) 1173{ 1174 if (layer->compositionType == HWC_BACKGROUND) { 1175 hwc_color_t color = layer->backgroundColor; 1176 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1177 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1178 cfg.x = 0; 1179 cfg.y = 0; 1180 cfg.w = pdev->xres; 1181 cfg.h = pdev->yres; 1182 return; 1183 } 1184 1185 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1186 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1187 layer->blending, layer->acquireFenceFd, cfg, pdev); 1188} 1189 1190static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1191 hwc_display_contents_1_t* contents) 1192{ 1193 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1194 struct s3c_fb_win_config_data win_data; 1195 struct s3c_fb_win_config *config = win_data.config; 1196 1197 memset(config, 0, sizeof(win_data.config)); 1198 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1199 config[i].fence_fd = -1; 1200 1201 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1202 int layer_idx = pdata->overlay_map[i]; 1203 if (layer_idx != -1) { 1204 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1205 private_handle_t *handle = 1206 private_handle_t::dynamicCast(layer.handle); 1207 1208 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1209 int gsc_idx = pdata->gsc_map[i].idx; 1210 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1211 1212 if (layer.acquireFenceFd != -1) { 1213 int err = sync_wait(layer.acquireFenceFd, 100); 1214 if (err != 0) 1215 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1216 i, strerror(errno)); 1217 close(layer.acquireFenceFd); 1218 } 1219 1220 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1221 gsc_idx); 1222 if (err < 0) { 1223 ALOGE("failed to queue gscaler %u input for layer %u", 1224 gsc_idx, i); 1225 continue; 1226 } 1227 1228 err = exynos_gsc_stop_exclusive(gsc.gsc); 1229 exynos_gsc_destroy(gsc.gsc); 1230 gsc.gsc = NULL; 1231 if (err < 0) { 1232 ALOGE("failed to dequeue gscaler output for layer %u", i); 1233 continue; 1234 } 1235 1236 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1237 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1238 private_handle_t *dst_handle = 1239 private_handle_t::dynamicCast(dst_buf); 1240 hwc_rect_t sourceCrop = { 0, 0, 1241 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1242 exynos5_config_handle(dst_handle, sourceCrop, 1243 layer.displayFrame, layer.blending, -1, config[i], 1244 pdev); 1245 } else { 1246 exynos5_config_overlay(&layer, config[i], pdev); 1247 } 1248 } 1249 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1250 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1251 config[i].blending = S3C_FB_BLENDING_NONE; 1252 } 1253 1254 ALOGV("window %u configuration:", i); 1255 dump_config(config[i]); 1256 } 1257 1258 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1259 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1260 if (config[i].fence_fd != -1) 1261 close(config[i].fence_fd); 1262 if (ret < 0) { 1263 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1264 return ret; 1265 } 1266 1267 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1268 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1269 pdev->last_fb_window = pdata->fb_window; 1270 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1271 int layer_idx = pdata->overlay_map[i]; 1272 if (layer_idx != -1) { 1273 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1274 pdev->last_handles[i] = layer.handle; 1275 } 1276 } 1277 1278 return win_data.fence; 1279} 1280 1281static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1282 hwc_display_contents_1_t* contents) 1283{ 1284 if (!contents->dpy || !contents->sur) 1285 return 0; 1286 1287 hwc_layer_1_t *fb_layer = NULL; 1288 1289 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1290 for (size_t i = 0; i < contents->numHwLayers; i++) { 1291 if (contents->hwLayers[i].compositionType == 1292 HWC_FRAMEBUFFER_TARGET) { 1293 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1294 fb_layer = &contents->hwLayers[i]; 1295 break; 1296 } 1297 } 1298 1299 if (CC_UNLIKELY(!fb_layer)) { 1300 ALOGE("framebuffer target expected, but not provided"); 1301 return -EINVAL; 1302 } 1303 1304 ALOGV("framebuffer target buffer:"); 1305 dump_layer(fb_layer); 1306 } 1307 1308 int fence = exynos5_post_fimd(pdev, contents); 1309 if (fence < 0) 1310 return fence; 1311 1312 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1313 if (pdev->bufs.overlay_map[i] != -1) { 1314 hwc_layer_1_t &layer = 1315 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1316 int dup_fd = dup(fence); 1317 if (dup_fd < 0) 1318 ALOGW("release fence dup failed: %s", strerror(errno)); 1319 layer.releaseFenceFd = dup_fd; 1320 } 1321 } 1322 close(fence); 1323 1324 return 0; 1325} 1326 1327static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1328 hwc_display_contents_1_t* contents) 1329{ 1330 if (!pdev->hdmi_enabled) { 1331 for (size_t i = 0; i < contents->numHwLayers; i++) { 1332 hwc_layer_1_t &layer = contents->hwLayers[i]; 1333 if (layer.acquireFenceFd != -1) 1334 close(layer.acquireFenceFd); 1335 } 1336 return 0; 1337 } 1338 1339 for (size_t i = 0; i < contents->numHwLayers; i++) { 1340 hwc_layer_1_t &layer = contents->hwLayers[i]; 1341 1342 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1343 if (!layer.handle) 1344 continue; 1345 1346 ALOGV("HDMI FB layer:"); 1347 dump_layer(&layer); 1348 1349 hdmi_configure_fblayer(pdev, layer); 1350 } 1351 } 1352 1353 return 0; 1354} 1355 1356static int exynos5_set(struct hwc_composer_device_1 *dev, 1357 size_t numDisplays, hwc_display_contents_1_t** displays) 1358{ 1359 if (!numDisplays || !displays) 1360 return 0; 1361 1362 exynos5_hwc_composer_device_1_t *pdev = 1363 (exynos5_hwc_composer_device_1_t *)dev; 1364 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1365 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1366 1367 if (fimd_contents) { 1368 int err = exynos5_set_fimd(pdev, fimd_contents); 1369 if (err) 1370 return err; 1371 } 1372 1373 if (hdmi_contents) { 1374 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1375 if (err) 1376 return err; 1377 } 1378 1379 return 0; 1380} 1381 1382static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1383 hwc_procs_t const* procs) 1384{ 1385 struct exynos5_hwc_composer_device_1_t* pdev = 1386 (struct exynos5_hwc_composer_device_1_t*)dev; 1387 pdev->procs = procs; 1388} 1389 1390static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1391{ 1392 struct exynos5_hwc_composer_device_1_t *pdev = 1393 (struct exynos5_hwc_composer_device_1_t *)dev; 1394 1395 switch (what) { 1396 case HWC_BACKGROUND_LAYER_SUPPORTED: 1397 // we support the background layer 1398 value[0] = 1; 1399 break; 1400 case HWC_VSYNC_PERIOD: 1401 // vsync period in nanosecond 1402 value[0] = pdev->vsync_period; 1403 break; 1404 default: 1405 // unsupported query 1406 return -EINVAL; 1407 } 1408 return 0; 1409} 1410 1411static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1412 int event, int enabled) 1413{ 1414 struct exynos5_hwc_composer_device_1_t *pdev = 1415 (struct exynos5_hwc_composer_device_1_t *)dev; 1416 1417 switch (event) { 1418 case HWC_EVENT_VSYNC: 1419 __u32 val = !!enabled; 1420 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1421 if (err < 0) { 1422 ALOGE("vsync ioctl failed"); 1423 return -errno; 1424 } 1425 1426 return 0; 1427 } 1428 1429 return -EINVAL; 1430} 1431 1432static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1433 const char *buff, int len) 1434{ 1435 const char *s = buff; 1436 s += strlen(s) + 1; 1437 1438 while (*s) { 1439 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1440 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1441 1442 s += strlen(s) + 1; 1443 if (s - buff >= len) 1444 break; 1445 } 1446 1447 if (pdev->hdmi_hpd) { 1448 if (hdmi_get_config(pdev)) { 1449 ALOGE("Error reading HDMI configuration"); 1450 pdev->hdmi_hpd = false; 1451 return; 1452 } 1453 } 1454 1455 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1456 if (pdev->hdmi_hpd) 1457 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1458 1459 /* hwc_dev->procs is set right after the device is opened, but there is 1460 * still a race condition where a hotplug event might occur after the open 1461 * but before the procs are registered. */ 1462 if (pdev->procs) 1463 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd); 1464} 1465 1466static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1467{ 1468 if (!pdev->procs) 1469 return; 1470 1471 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1472 if (err < 0) { 1473 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1474 return; 1475 } 1476 1477 char buf[4096]; 1478 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1479 if (err < 0) { 1480 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1481 return; 1482 } 1483 buf[sizeof(buf) - 1] = '\0'; 1484 1485 errno = 0; 1486 uint64_t timestamp = strtoull(buf, NULL, 0); 1487 if (!errno) 1488 pdev->procs->vsync(pdev->procs, 0, timestamp); 1489} 1490 1491static void *hwc_vsync_thread(void *data) 1492{ 1493 struct exynos5_hwc_composer_device_1_t *pdev = 1494 (struct exynos5_hwc_composer_device_1_t *)data; 1495 char uevent_desc[4096]; 1496 memset(uevent_desc, 0, sizeof(uevent_desc)); 1497 1498 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1499 1500 uevent_init(); 1501 1502 char temp[4096]; 1503 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1504 if (err < 0) { 1505 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1506 return NULL; 1507 } 1508 1509 struct pollfd fds[2]; 1510 fds[0].fd = pdev->vsync_fd; 1511 fds[0].events = POLLPRI; 1512 fds[1].fd = uevent_get_fd(); 1513 fds[1].events = POLLIN; 1514 1515 while (true) { 1516 int err = poll(fds, 2, -1); 1517 1518 if (err > 0) { 1519 if (fds[0].revents & POLLPRI) { 1520 handle_vsync_event(pdev); 1521 } 1522 else if (fds[1].revents & POLLIN) { 1523 int len = uevent_next_event(uevent_desc, 1524 sizeof(uevent_desc) - 2); 1525 1526 bool hdmi = !strcmp(uevent_desc, 1527 "change@/devices/virtual/switch/hdmi"); 1528 if (hdmi) 1529 handle_hdmi_uevent(pdev, uevent_desc, len); 1530 } 1531 } 1532 else if (err == -1) { 1533 if (errno == EINTR) 1534 break; 1535 ALOGE("error in vsync thread: %s", strerror(errno)); 1536 } 1537 } 1538 1539 return NULL; 1540} 1541 1542static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1543{ 1544 struct exynos5_hwc_composer_device_1_t *pdev = 1545 (struct exynos5_hwc_composer_device_1_t *)dev; 1546 1547 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1548 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1549 if (err < 0) { 1550 if (errno == EBUSY) 1551 ALOGI("%sblank ioctl failed (display already %sblanked)", 1552 blank ? "" : "un", blank ? "" : "un"); 1553 else 1554 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un", 1555 strerror(errno)); 1556 return -errno; 1557 } 1558 1559 if (pdev->hdmi_hpd) { 1560 if (blank && !pdev->hdmi_blanked) 1561 hdmi_disable(pdev); 1562 pdev->hdmi_blanked = !!blank; 1563 } 1564 1565 return 0; 1566} 1567 1568static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1569{ 1570 if (buff_len <= 0) 1571 return; 1572 1573 struct exynos5_hwc_composer_device_1_t *pdev = 1574 (struct exynos5_hwc_composer_device_1_t *)dev; 1575 1576 android::String8 result; 1577 1578 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1579 if (pdev->hdmi_enabled) 1580 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1581 result.append( 1582 " type | handle | color | blend | format | position | size | gsc \n" 1583 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1584 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1585 1586 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1587 struct s3c_fb_win_config &config = pdev->last_config[i]; 1588 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1589 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1590 "DISABLED", "-", "-", "-", "-", "-", "-"); 1591 } 1592 else { 1593 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1594 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1595 "-", config.color, "-", "-"); 1596 else 1597 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1598 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1599 intptr_t(pdev->last_handles[i]), 1600 "-", config.blending, config.format); 1601 1602 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1603 config.w, config.h); 1604 } 1605 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1606 result.appendFormat(" | %3s", "-"); 1607 else 1608 result.appendFormat(" | %3d", 1609 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1610 result.append("\n"); 1611 } 1612 1613 strlcpy(buff, result.string(), buff_len); 1614} 1615 1616static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1617 int disp, uint32_t *configs, size_t *numConfigs) 1618{ 1619 struct exynos5_hwc_composer_device_1_t *pdev = 1620 (struct exynos5_hwc_composer_device_1_t *)dev; 1621 1622 if (*numConfigs == 0) 1623 return 0; 1624 1625 if (disp == HWC_DISPLAY_PRIMARY) { 1626 configs[0] = 0; 1627 *numConfigs = 1; 1628 return 0; 1629 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1630 if (!pdev->hdmi_hpd) { 1631 return -EINVAL; 1632 } 1633 1634 int err = hdmi_get_config(pdev); 1635 if (err) { 1636 return -EINVAL; 1637 } 1638 1639 configs[0] = 0; 1640 *numConfigs = 1; 1641 return 0; 1642 } 1643 1644 return -EINVAL; 1645} 1646 1647static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1648 const uint32_t attribute) 1649{ 1650 switch(attribute) { 1651 case HWC_DISPLAY_VSYNC_PERIOD: 1652 return pdev->vsync_period; 1653 1654 case HWC_DISPLAY_WIDTH: 1655 return pdev->xres; 1656 1657 case HWC_DISPLAY_HEIGHT: 1658 return pdev->yres; 1659 1660 case HWC_DISPLAY_DPI_X: 1661 return pdev->xdpi; 1662 1663 case HWC_DISPLAY_DPI_Y: 1664 return pdev->ydpi; 1665 1666 default: 1667 ALOGE("unknown display attribute %u", attribute); 1668 return -EINVAL; 1669 } 1670} 1671 1672static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1673 const uint32_t attribute) 1674{ 1675 switch(attribute) { 1676 case HWC_DISPLAY_VSYNC_PERIOD: 1677 return pdev->vsync_period; 1678 1679 case HWC_DISPLAY_WIDTH: 1680 return pdev->hdmi_w; 1681 1682 case HWC_DISPLAY_HEIGHT: 1683 return pdev->hdmi_h; 1684 1685 case HWC_DISPLAY_DPI_X: 1686 case HWC_DISPLAY_DPI_Y: 1687 return 0; // unknown 1688 1689 default: 1690 ALOGE("unknown display attribute %u", attribute); 1691 return -EINVAL; 1692 } 1693} 1694 1695static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1696 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1697{ 1698 struct exynos5_hwc_composer_device_1_t *pdev = 1699 (struct exynos5_hwc_composer_device_1_t *)dev; 1700 1701 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1702 if (disp == HWC_DISPLAY_PRIMARY) 1703 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1704 else if (disp == HWC_DISPLAY_EXTERNAL) 1705 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1706 else { 1707 ALOGE("unknown display type %u", disp); 1708 return -EINVAL; 1709 } 1710 } 1711 1712 return 0; 1713} 1714 1715static int exynos5_close(hw_device_t* device); 1716 1717static int exynos5_open(const struct hw_module_t *module, const char *name, 1718 struct hw_device_t **device) 1719{ 1720 int ret; 1721 int refreshRate; 1722 int sw_fd; 1723 1724 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1725 return -EINVAL; 1726 } 1727 1728 struct exynos5_hwc_composer_device_1_t *dev; 1729 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1730 memset(dev, 0, sizeof(*dev)); 1731 1732 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1733 (const struct hw_module_t **)&dev->gralloc_module)) { 1734 ALOGE("failed to get gralloc hw module"); 1735 ret = -EINVAL; 1736 goto err_get_module; 1737 } 1738 1739 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1740 &dev->alloc_device)) { 1741 ALOGE("failed to open gralloc"); 1742 ret = -EINVAL; 1743 goto err_get_module; 1744 } 1745 1746 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1747 if (dev->fd < 0) { 1748 ALOGE("failed to open framebuffer"); 1749 ret = dev->fd; 1750 goto err_open_fb; 1751 } 1752 1753 struct fb_var_screeninfo info; 1754 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1755 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1756 ret = -errno; 1757 goto err_ioctl; 1758 } 1759 1760 refreshRate = 1000000000000LLU / 1761 ( 1762 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1763 * ( info.left_margin + info.right_margin + info.xres ) 1764 * info.pixclock 1765 ); 1766 1767 if (refreshRate == 0) { 1768 ALOGW("invalid refresh rate, assuming 60 Hz"); 1769 refreshRate = 60; 1770 } 1771 1772 dev->xres = 2560; 1773 dev->yres = 1600; 1774 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1775 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1776 dev->vsync_period = 1000000000 / refreshRate; 1777 1778 ALOGV("using\n" 1779 "xres = %d px\n" 1780 "yres = %d px\n" 1781 "width = %d mm (%f dpi)\n" 1782 "height = %d mm (%f dpi)\n" 1783 "refresh rate = %d Hz\n", 1784 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1785 info.height, dev->ydpi / 1000.0, refreshRate); 1786 1787 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1788 if (dev->hdmi_layer0 < 0) { 1789 ALOGE("failed to open hdmi mixer0 subdev"); 1790 ret = dev->hdmi_layer0; 1791 goto err_ioctl; 1792 } 1793 1794 dev->hdmi_layer0 = open("/dev/video16", O_RDWR); 1795 if (dev->hdmi_layer0 < 0) { 1796 ALOGE("failed to open hdmi layer0 device"); 1797 ret = dev->hdmi_layer0; 1798 goto err_mixer0; 1799 } 1800 1801 dev->hdmi_layer1 = open("/dev/video17", O_RDWR); 1802 if (dev->hdmi_layer1 < 0) { 1803 ALOGE("failed to open hdmi layer1 device"); 1804 ret = dev->hdmi_layer1; 1805 goto err_hdmi0; 1806 } 1807 1808 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1809 if (dev->vsync_fd < 0) { 1810 ALOGE("failed to open vsync attribute"); 1811 ret = dev->vsync_fd; 1812 goto err_hdmi1; 1813 } 1814 1815 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1816 if (sw_fd) { 1817 char val; 1818 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1819 dev->hdmi_hpd = true; 1820 if (hdmi_get_config(dev)) { 1821 ALOGE("Error reading HDMI configuration"); 1822 dev->hdmi_hpd = false; 1823 } 1824 } 1825 } 1826 1827 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1828 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1829 dev->base.common.module = const_cast<hw_module_t *>(module); 1830 dev->base.common.close = exynos5_close; 1831 1832 dev->base.prepare = exynos5_prepare; 1833 dev->base.set = exynos5_set; 1834 dev->base.eventControl = exynos5_eventControl; 1835 dev->base.blank = exynos5_blank; 1836 dev->base.query = exynos5_query; 1837 dev->base.registerProcs = exynos5_registerProcs; 1838 dev->base.dump = exynos5_dump; 1839 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1840 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1841 1842 *device = &dev->base.common; 1843 1844 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1845 if (ret) { 1846 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1847 ret = -ret; 1848 goto err_vsync; 1849 } 1850 1851 char value[PROPERTY_VALUE_MAX]; 1852 property_get("debug.hwc.force_gpu", value, "0"); 1853 dev->force_gpu = atoi(value); 1854 1855 return 0; 1856 1857err_vsync: 1858 close(dev->vsync_fd); 1859err_mixer0: 1860 close(dev->hdmi_mixer0); 1861err_hdmi1: 1862 close(dev->hdmi_layer0); 1863err_hdmi0: 1864 close(dev->hdmi_layer1); 1865err_ioctl: 1866 close(dev->fd); 1867err_open_fb: 1868 gralloc_close(dev->alloc_device); 1869err_get_module: 1870 free(dev); 1871 return ret; 1872} 1873 1874static int exynos5_close(hw_device_t *device) 1875{ 1876 struct exynos5_hwc_composer_device_1_t *dev = 1877 (struct exynos5_hwc_composer_device_1_t *)device; 1878 pthread_kill(dev->vsync_thread, SIGTERM); 1879 pthread_join(dev->vsync_thread, NULL); 1880 for (size_t i = 0; i < NUM_GSC_UNITS; i++) { 1881 if (dev->gsc[i].gsc) 1882 exynos_gsc_destroy(dev->gsc[i].gsc); 1883 for (size_t j = 0; i < NUM_GSC_DST_BUFS; j++) 1884 if (dev->gsc[i].dst_buf[j]) 1885 dev->alloc_device->free(dev->alloc_device, dev->gsc[i].dst_buf[j]); 1886 } 1887 gralloc_close(dev->alloc_device); 1888 close(dev->vsync_fd); 1889 close(dev->hdmi_mixer0); 1890 close(dev->hdmi_layer0); 1891 close(dev->hdmi_layer1); 1892 close(dev->fd); 1893 return 0; 1894} 1895 1896static struct hw_module_methods_t exynos5_hwc_module_methods = { 1897 open: exynos5_open, 1898}; 1899 1900hwc_module_t HAL_MODULE_INFO_SYM = { 1901 common: { 1902 tag: HARDWARE_MODULE_TAG, 1903 module_api_version: HWC_MODULE_API_VERSION_0_1, 1904 hal_api_version: HARDWARE_HAL_API_VERSION, 1905 id: HWC_HARDWARE_MODULE_ID, 1906 name: "Samsung exynos5 hwcomposer module", 1907 author: "Google", 1908 methods: &exynos5_hwc_module_methods, 1909 } 1910}; 1911