hwc.cpp revision d6743822496f732019c4c16db81e443598763500
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const size_t FIMD_GSC_IDX = 0; 59const size_t HDMI_GSC_IDX = 1; 60const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 61const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 62 sizeof(AVAILABLE_GSC_UNITS[0]); 63const size_t BURSTLEN_BYTES = 16 * 8; 64const size_t NUM_HDMI_BUFFERS = 3; 65 66struct exynos5_hwc_composer_device_1_t; 67 68struct exynos5_gsc_map_t { 69 enum { 70 GSC_NONE = 0, 71 GSC_M2M, 72 // TODO: GSC_LOCAL_PATH 73 } mode; 74 int idx; 75}; 76 77struct exynos5_hwc_post_data_t { 78 int overlay_map[NUM_HW_WINDOWS]; 79 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 80 size_t fb_window; 81}; 82 83const size_t NUM_GSC_DST_BUFS = 3; 84struct exynos5_gsc_data_t { 85 void *gsc; 86 exynos_gsc_img src_cfg; 87 exynos_gsc_img dst_cfg; 88 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 89 size_t current_buf; 90}; 91 92struct hdmi_layer_t { 93 int id; 94 int fd; 95 bool enabled; 96 exynos_gsc_img cfg; 97 98 bool streaming; 99 size_t current_buf; 100 size_t queued_buf; 101}; 102 103struct exynos5_hwc_composer_device_1_t { 104 hwc_composer_device_1_t base; 105 106 int fd; 107 int vsync_fd; 108 exynos5_hwc_post_data_t bufs; 109 110 const private_module_t *gralloc_module; 111 alloc_device_t *alloc_device; 112 const hwc_procs_t *procs; 113 pthread_t vsync_thread; 114 int force_gpu; 115 116 int32_t xres; 117 int32_t yres; 118 int32_t xdpi; 119 int32_t ydpi; 120 int32_t vsync_period; 121 122 int hdmi_mixer0; 123 bool hdmi_hpd; 124 bool hdmi_enabled; 125 bool hdmi_blanked; 126 int hdmi_w; 127 int hdmi_h; 128 129 hdmi_layer_t hdmi_layers[2]; 130 131 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 132 133 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 134 size_t last_fb_window; 135 const void *last_handles[NUM_HW_WINDOWS]; 136 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 137}; 138 139static void dump_handle(private_handle_t *h) 140{ 141 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 142 h->format, h->width, h->height, h->stride, h->vstride); 143} 144 145static void dump_layer(hwc_layer_1_t const *l) 146{ 147 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 148 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 149 l->compositionType, l->flags, l->handle, l->transform, 150 l->blending, 151 l->sourceCrop.left, 152 l->sourceCrop.top, 153 l->sourceCrop.right, 154 l->sourceCrop.bottom, 155 l->displayFrame.left, 156 l->displayFrame.top, 157 l->displayFrame.right, 158 l->displayFrame.bottom); 159 160 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 161 dump_handle(private_handle_t::dynamicCast(l->handle)); 162} 163 164static void dump_config(s3c_fb_win_config &c) 165{ 166 ALOGV("\tstate = %u", c.state); 167 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 168 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 169 "x = %d, y = %d, w = %u, h = %u, " 170 "format = %u, blending = %u", 171 c.fd, c.offset, c.stride, 172 c.x, c.y, c.w, c.h, 173 c.format, c.blending); 174 } 175 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 176 ALOGV("\t\tcolor = %u", c.color); 177 } 178} 179 180static void dump_gsc_img(exynos_gsc_img &c) 181{ 182 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 183 c.x, c.y, c.w, c.h, c.fw, c.fh); 184 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 185 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 186} 187 188inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 189inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 190template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 191template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 192 193static bool is_transformed(const hwc_layer_1_t &layer) 194{ 195 return layer.transform != 0; 196} 197 198static bool is_rotated(const hwc_layer_1_t &layer) 199{ 200 return (layer.transform & HAL_TRANSFORM_ROT_90) || 201 (layer.transform & HAL_TRANSFORM_ROT_180); 202} 203 204static bool is_scaled(const hwc_layer_1_t &layer) 205{ 206 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 207 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 208} 209 210static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 211{ 212 return c1.x != c2.x || 213 c1.y != c2.y || 214 c1.w != c2.w || 215 c1.h != c2.h || 216 c1.format != c2.format || 217 c1.rot != c2.rot || 218 c1.cacheable != c2.cacheable || 219 c1.drmMode != c2.drmMode; 220} 221 222static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 223{ 224 return gsc_dst_cfg_changed(c1, c2) || 225 c1.fw != c2.fw || 226 c1.fh != c2.fh; 227} 228 229static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 230{ 231 switch (format) { 232 case HAL_PIXEL_FORMAT_RGBA_8888: 233 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 234 case HAL_PIXEL_FORMAT_RGBX_8888: 235 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 236 case HAL_PIXEL_FORMAT_RGBA_5551: 237 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 238 case HAL_PIXEL_FORMAT_RGB_565: 239 return S3C_FB_PIXEL_FORMAT_RGB_565; 240 case HAL_PIXEL_FORMAT_BGRA_8888: 241 return S3C_FB_PIXEL_FORMAT_BGRA_8888; 242 default: 243 return S3C_FB_PIXEL_FORMAT_MAX; 244 } 245} 246 247static bool exynos5_format_is_supported(int format) 248{ 249 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 250} 251 252static bool exynos5_format_is_rgb(int format) 253{ 254 switch (format) { 255 case HAL_PIXEL_FORMAT_RGBA_8888: 256 case HAL_PIXEL_FORMAT_RGBX_8888: 257 case HAL_PIXEL_FORMAT_RGB_888: 258 case HAL_PIXEL_FORMAT_RGB_565: 259 case HAL_PIXEL_FORMAT_BGRA_8888: 260 case HAL_PIXEL_FORMAT_RGBA_5551: 261 case HAL_PIXEL_FORMAT_RGBA_4444: 262 return true; 263 264 default: 265 return false; 266 } 267} 268 269static bool exynos5_format_is_supported_by_gscaler(int format) 270{ 271 switch (format) { 272 case HAL_PIXEL_FORMAT_RGBX_8888: 273 case HAL_PIXEL_FORMAT_RGB_565: 274 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 275 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 276 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 277 return true; 278 279 default: 280 return false; 281 } 282} 283 284static bool exynos5_format_is_ycrcb(int format) 285{ 286 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 287} 288 289static bool exynos5_format_requires_gscaler(int format) 290{ 291 return (exynos5_format_is_supported_by_gscaler(format) && 292 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565)); 293} 294 295static uint8_t exynos5_format_to_bpp(int format) 296{ 297 switch (format) { 298 case HAL_PIXEL_FORMAT_RGBA_8888: 299 case HAL_PIXEL_FORMAT_RGBX_8888: 300 case HAL_PIXEL_FORMAT_BGRA_8888: 301 return 32; 302 303 case HAL_PIXEL_FORMAT_RGBA_5551: 304 case HAL_PIXEL_FORMAT_RGBA_4444: 305 case HAL_PIXEL_FORMAT_RGB_565: 306 return 16; 307 308 default: 309 ALOGW("unrecognized pixel format %u", format); 310 return 0; 311 } 312} 313 314static bool is_x_aligned(const hwc_layer_1_t &layer, int format) 315{ 316 if (!exynos5_format_is_supported(format)) 317 return true; 318 319 uint8_t bpp = exynos5_format_to_bpp(format); 320 uint8_t pixel_alignment = 32 / bpp; 321 322 return (layer.displayFrame.left % pixel_alignment) == 0 && 323 (layer.displayFrame.right % pixel_alignment) == 0; 324} 325 326static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 327 bool local_path) 328{ 329 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 330 331 int max_w = is_rotated(layer) ? 2048 : 4800; 332 int max_h = is_rotated(layer) ? 2048 : 3344; 333 334 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 335 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 336 // HAL_TRANSFORM_ROT_180 337 338 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 339 int dest_w, dest_h; 340 if (rot90or270) { 341 dest_w = HEIGHT(layer.displayFrame); 342 dest_h = WIDTH(layer.displayFrame); 343 } else { 344 dest_w = WIDTH(layer.displayFrame); 345 dest_h = HEIGHT(layer.displayFrame); 346 } 347 int max_downscale = local_path ? 4 : 16; 348 const int max_upscale = 8; 349 350 return exynos5_format_is_supported_by_gscaler(format) && 351 handle->stride <= max_w && 352 handle->stride % GSC_W_ALIGNMENT == 0 && 353 src_w <= dest_w * max_downscale && 354 dest_w <= src_w * max_upscale && 355 handle->vstride <= max_h && 356 handle->vstride % GSC_H_ALIGNMENT == 0 && 357 src_h <= dest_h * max_downscale && 358 dest_h <= src_h * max_upscale && 359 // per 46.2 360 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 361 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 362 // per 46.3.1.6 363} 364 365static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 366{ 367 return exynos5_format_requires_gscaler(format) || is_scaled(layer) 368 || is_transformed(layer) || !is_x_aligned(layer, format); 369} 370 371int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 372{ 373 struct v4l2_dv_preset preset; 374 struct v4l2_dv_enum_preset enum_preset; 375 int index = 0; 376 bool found = false; 377 int ret; 378 379 if (ioctl(dev->hdmi_layers[0].fd, VIDIOC_G_DV_PRESET, &preset) < 0) { 380 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 381 return -1; 382 } 383 384 while (true) { 385 enum_preset.index = index++; 386 ret = ioctl(dev->hdmi_layers[0].fd, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 387 388 if (ret < 0) { 389 if (errno == EINVAL) 390 break; 391 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 392 return -1; 393 } 394 395 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 396 __func__, enum_preset.index, enum_preset.preset, 397 enum_preset.width, enum_preset.height, enum_preset.name); 398 399 if (preset.preset == enum_preset.preset) { 400 dev->hdmi_w = enum_preset.width; 401 dev->hdmi_h = enum_preset.height; 402 found = true; 403 } 404 } 405 406 return found ? 0 : -1; 407} 408 409static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 410{ 411 switch (blending) { 412 case HWC_BLENDING_NONE: 413 return S3C_FB_BLENDING_NONE; 414 case HWC_BLENDING_PREMULT: 415 return S3C_FB_BLENDING_PREMULT; 416 case HWC_BLENDING_COVERAGE: 417 return S3C_FB_BLENDING_COVERAGE; 418 419 default: 420 return S3C_FB_BLENDING_MAX; 421 } 422} 423 424static bool exynos5_blending_is_supported(int32_t blending) 425{ 426 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 427} 428 429 430static int hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t *dev, 431 hdmi_layer_t &hl) 432{ 433 if (hl.enabled) 434 return 0; 435 436 struct v4l2_requestbuffers reqbuf; 437 memset(&reqbuf, 0, sizeof(reqbuf)); 438 reqbuf.count = NUM_HDMI_BUFFERS; 439 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 440 reqbuf.memory = V4L2_MEMORY_DMABUF; 441 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) { 442 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 443 return -1; 444 } 445 446 if (reqbuf.count != NUM_HDMI_BUFFERS) { 447 ALOGE("%s: layer%d: didn't get buffer", __func__, hl.id); 448 return -1; 449 } 450 451 if (hl.id == 1) { 452 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_PIXEL_BLEND_ENABLE, 1) < 0) { 453 ALOGE("%s: layer%d: PIXEL_BLEND_ENABLE failed %d", __func__, 454 hl.id, errno); 455 return -1; 456 } 457 } 458 459 ALOGV("%s: layer%d enabled", __func__, hl.id); 460 hl.enabled = true; 461 return 0; 462} 463 464static void hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t *dev, 465 hdmi_layer_t &hl) 466{ 467 if (!hl.enabled) 468 return; 469 470 if (hl.streaming) { 471 if (exynos_v4l2_streamoff(hl.fd, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) 472 ALOGE("%s: layer%d: streamoff failed %d", __func__, hl.id, errno); 473 hl.streaming = false; 474 } 475 476 struct v4l2_requestbuffers reqbuf; 477 memset(&reqbuf, 0, sizeof(reqbuf)); 478 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 479 reqbuf.memory = V4L2_MEMORY_DMABUF; 480 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) 481 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 482 483 memset(&hl.cfg, 0, sizeof(hl.cfg)); 484 hl.current_buf = 0; 485 hl.queued_buf = 0; 486 hl.enabled = false; 487 488 ALOGV("%s: layer%d disabled", __func__, hl.id); 489} 490 491static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 492{ 493 if (dev->hdmi_enabled) 494 return 0; 495 496 if (dev->hdmi_blanked) 497 return 0; 498 499 struct v4l2_subdev_format sd_fmt; 500 memset(&sd_fmt, 0, sizeof(sd_fmt)); 501 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SINK; 502 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 503 sd_fmt.format.width = dev->hdmi_w; 504 sd_fmt.format.height = dev->hdmi_h; 505 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 506 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 507 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 508 return -1; 509 } 510 511 struct v4l2_subdev_crop sd_crop; 512 memset(&sd_crop, 0, sizeof(sd_crop)); 513 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SINK; 514 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 515 sd_crop.rect.width = dev->hdmi_w; 516 sd_crop.rect.height = dev->hdmi_h; 517 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 518 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 519 return -1; 520 } 521 522 memset(&sd_fmt, 0, sizeof(sd_fmt)); 523 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 524 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 525 sd_fmt.format.width = dev->hdmi_w; 526 sd_fmt.format.height = dev->hdmi_h; 527 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 528 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 529 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 530 return -1; 531 } 532 533 memset(&sd_crop, 0, sizeof(sd_crop)); 534 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 535 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 536 sd_crop.rect.width = dev->hdmi_w; 537 sd_crop.rect.height = dev->hdmi_h; 538 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 539 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 540 return -1; 541 } 542 543 hdmi_enable_layer(dev, dev->hdmi_layers[1]); 544 545 dev->hdmi_enabled = true; 546 return 0; 547} 548 549static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 550{ 551 if (!dev->hdmi_enabled) 552 return; 553 554 hdmi_disable_layer(dev, dev->hdmi_layers[0]); 555 hdmi_disable_layer(dev, dev->hdmi_layers[1]); 556 557 exynos5_gsc_data_t *gsc_data = &dev->gsc[HDMI_GSC_IDX]; 558 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 559 if (gsc_data->dst_buf[i]) 560 dev->alloc_device->free(dev->alloc_device, gsc_data->dst_buf[i]); 561 } 562 563 memset(gsc_data, 0, sizeof(*gsc_data)); 564 565 dev->hdmi_enabled = false; 566} 567 568static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, 569 hdmi_layer_t &hl, 570 hwc_layer_1_t &layer, 571 private_handle_t *h) 572{ 573 int ret = 0; 574 575 exynos_gsc_img cfg; 576 memset(&cfg, 0, sizeof(cfg)); 577 cfg.x = layer.displayFrame.left; 578 cfg.y = layer.displayFrame.top; 579 cfg.w = WIDTH(layer.displayFrame); 580 cfg.h = HEIGHT(layer.displayFrame); 581 582 if (gsc_src_cfg_changed(hl.cfg, cfg)) { 583 hdmi_disable_layer(dev, hl); 584 585 struct v4l2_format fmt; 586 memset(&fmt, 0, sizeof(fmt)); 587 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 588 fmt.fmt.pix_mp.width = cfg.w; 589 fmt.fmt.pix_mp.height = cfg.h; 590 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 591 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 592 fmt.fmt.pix_mp.num_planes = 1; 593 ret = exynos_v4l2_s_fmt(hl.fd, &fmt); 594 if (ret < 0) { 595 ALOGE("%s: layer%d: s_fmt failed %d", __func__, hl.id, errno); 596 goto err; 597 } 598 599 struct v4l2_subdev_crop sd_crop; 600 memset(&sd_crop, 0, sizeof(sd_crop)); 601 if (hl.id == 0) 602 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 603 else 604 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 605 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 606 sd_crop.rect.left = cfg.x; 607 sd_crop.rect.top = cfg.y; 608 sd_crop.rect.width = cfg.w; 609 sd_crop.rect.height = cfg.h; 610 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 611 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 612 goto err; 613 } 614 615 hdmi_enable_layer(dev, hl); 616 617 ALOGV("HDMI layer%d configuration:", hl.id); 618 dump_gsc_img(cfg); 619 hl.cfg = cfg; 620 } 621 622 struct v4l2_buffer buffer; 623 struct v4l2_plane planes[1]; 624 625 if (hl.queued_buf == NUM_HDMI_BUFFERS) { 626 memset(&buffer, 0, sizeof(buffer)); 627 memset(planes, 0, sizeof(planes)); 628 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 629 buffer.memory = V4L2_MEMORY_DMABUF; 630 buffer.length = 1; 631 buffer.m.planes = planes; 632 ret = exynos_v4l2_dqbuf(hl.fd, &buffer); 633 if (ret < 0) { 634 ALOGE("%s: layer%d: dqbuf failed %d", __func__, hl.id, errno); 635 goto err; 636 } 637 hl.queued_buf--; 638 } 639 640 memset(&buffer, 0, sizeof(buffer)); 641 memset(planes, 0, sizeof(planes)); 642 buffer.index = hl.current_buf; 643 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 644 buffer.memory = V4L2_MEMORY_DMABUF; 645 buffer.flags = V4L2_BUF_FLAG_USE_SYNC; 646 buffer.reserved = layer.acquireFenceFd; 647 buffer.length = 1; 648 buffer.m.planes = planes; 649 buffer.m.planes[0].m.fd = h->fd; 650 if (exynos_v4l2_qbuf(hl.fd, &buffer) < 0) { 651 ALOGE("%s: layer%d: qbuf failed %d", __func__, hl.id, errno); 652 ret = -1; 653 goto err; 654 } 655 656 layer.releaseFenceFd = buffer.reserved; 657 658 hl.queued_buf++; 659 hl.current_buf = (hl.current_buf + 1) % NUM_HDMI_BUFFERS; 660 661 if (!hl.streaming) { 662 if (exynos_v4l2_streamon(hl.fd, buffer.type) < 0) { 663 ALOGE("%s: layer%d: streamon failed %d", __func__, hl.id, errno); 664 ret = -1; 665 goto err; 666 } 667 hl.streaming = true; 668 } 669 670err: 671 if (layer.acquireFenceFd >= 0) 672 close(layer.acquireFenceFd); 673 674 return ret; 675} 676 677bool exynos5_is_offscreen(hwc_layer_1_t &layer, 678 struct exynos5_hwc_composer_device_1_t *pdev) 679{ 680 return layer.sourceCrop.left > pdev->xres || 681 layer.sourceCrop.right < 0 || 682 layer.sourceCrop.top > pdev->yres || 683 layer.sourceCrop.bottom < 0; 684} 685 686size_t exynos5_visible_width(hwc_layer_1_t &layer, int format, 687 struct exynos5_hwc_composer_device_1_t *pdev) 688{ 689 int bpp; 690 if (exynos5_requires_gscaler(layer, format)) 691 bpp = 32; 692 else 693 bpp = exynos5_format_to_bpp(format); 694 int left = max(layer.displayFrame.left, 0); 695 int right = min(layer.displayFrame.right, pdev->xres); 696 697 return (right - left) * bpp / 8; 698} 699 700bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 701 struct exynos5_hwc_composer_device_1_t *pdev) 702{ 703 if (layer.flags & HWC_SKIP_LAYER) { 704 ALOGV("\tlayer %u: skipping", i); 705 return false; 706 } 707 708 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 709 710 if (!handle) { 711 ALOGV("\tlayer %u: handle is NULL", i); 712 return false; 713 } 714 if (!exynos5_format_is_rgb(handle->format) && 715 !exynos5_format_is_supported_by_gscaler(handle->format)) { 716 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 717 return false; 718 } 719 720 if (exynos5_requires_gscaler(layer, handle->format)) { 721 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 722 ALOGV("\tlayer %u: gscaler required but not supported", i); 723 return false; 724 } 725 } else { 726 if (!exynos5_format_is_supported(handle->format)) { 727 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 728 return false; 729 } 730 } 731 if (!exynos5_blending_is_supported(layer.blending)) { 732 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 733 return false; 734 } 735 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 736 ALOGW("\tlayer %u: off-screen", i); 737 return false; 738 } 739 if (exynos5_visible_width(layer, handle->format, pdev) < BURSTLEN_BYTES) { 740 ALOGV("\tlayer %u: visible area is too narrow", i); 741 return false; 742 } 743 744 return true; 745} 746 747inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 748{ 749 return !(r1.left > r2.right || 750 r1.right < r2.left || 751 r1.top > r2.bottom || 752 r1.bottom < r2.top); 753} 754 755inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 756{ 757 hwc_rect i; 758 i.top = max(r1.top, r2.top); 759 i.bottom = min(r1.bottom, r2.bottom); 760 i.left = max(r1.left, r2.left); 761 i.right = min(r1.right, r2.right); 762 return i; 763} 764 765static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 766 hwc_display_contents_1_t* contents) 767{ 768 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 769 770 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 771 772 bool force_fb = pdev->force_gpu; 773 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 774 pdev->bufs.overlay_map[i] = -1; 775 776 bool fb_needed = false; 777 size_t first_fb = 0, last_fb = 0; 778 779 // find unsupported overlays 780 for (size_t i = 0; i < contents->numHwLayers; i++) { 781 hwc_layer_1_t &layer = contents->hwLayers[i]; 782 783 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 784 ALOGV("\tlayer %u: framebuffer target", i); 785 continue; 786 } 787 788 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 789 ALOGV("\tlayer %u: background supported", i); 790 dump_layer(&contents->hwLayers[i]); 791 continue; 792 } 793 794 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 795 !force_fb) { 796 ALOGV("\tlayer %u: overlay supported", i); 797 layer.compositionType = HWC_OVERLAY; 798 dump_layer(&contents->hwLayers[i]); 799 continue; 800 } 801 802 if (!fb_needed) { 803 first_fb = i; 804 fb_needed = true; 805 } 806 last_fb = i; 807 layer.compositionType = HWC_FRAMEBUFFER; 808 809 dump_layer(&contents->hwLayers[i]); 810 } 811 812 // can't composite overlays sandwiched between framebuffers 813 if (fb_needed) 814 for (size_t i = first_fb; i < last_fb; i++) 815 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 816 817 // Incrementally try to add our supported layers to hardware windows. 818 // If adding a layer would violate a hardware constraint, force it 819 // into the framebuffer and try again. (Revisiting the entire list is 820 // necessary because adding a layer to the framebuffer can cause other 821 // windows to retroactively violate constraints.) 822 bool changed; 823 bool gsc_used; 824 do { 825 android::Vector<hwc_rect> rects; 826 android::Vector<hwc_rect> overlaps; 827 size_t pixels_left, windows_left; 828 829 gsc_used = false; 830 831 if (fb_needed) { 832 hwc_rect_t fb_rect; 833 fb_rect.top = fb_rect.left = 0; 834 fb_rect.right = pdev->xres - 1; 835 fb_rect.bottom = pdev->yres - 1; 836 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 837 windows_left = NUM_HW_WINDOWS - 1; 838 rects.push_back(fb_rect); 839 } 840 else { 841 pixels_left = MAX_PIXELS; 842 windows_left = NUM_HW_WINDOWS; 843 } 844 845 changed = false; 846 847 for (size_t i = 0; i < contents->numHwLayers; i++) { 848 hwc_layer_1_t &layer = contents->hwLayers[i]; 849 if ((layer.flags & HWC_SKIP_LAYER) || 850 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 851 continue; 852 853 private_handle_t *handle = private_handle_t::dynamicCast( 854 layer.handle); 855 856 // we've already accounted for the framebuffer above 857 if (layer.compositionType == HWC_FRAMEBUFFER) 858 continue; 859 860 // only layer 0 can be HWC_BACKGROUND, so we can 861 // unconditionally allow it without extra checks 862 if (layer.compositionType == HWC_BACKGROUND) { 863 windows_left--; 864 continue; 865 } 866 867 size_t pixels_needed = WIDTH(layer.displayFrame) * 868 HEIGHT(layer.displayFrame); 869 bool can_compose = windows_left && pixels_needed <= pixels_left; 870 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 871 if (gsc_required) 872 can_compose = can_compose && !gsc_used; 873 874 // hwc_rect_t right and bottom values are normally exclusive; 875 // the intersection logic is simpler if we make them inclusive 876 hwc_rect_t visible_rect = layer.displayFrame; 877 visible_rect.right--; visible_rect.bottom--; 878 879 // no more than 2 layers can overlap on a given pixel 880 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 881 if (intersect(visible_rect, overlaps.itemAt(j))) 882 can_compose = false; 883 } 884 885 if (!can_compose) { 886 layer.compositionType = HWC_FRAMEBUFFER; 887 if (!fb_needed) { 888 first_fb = last_fb = i; 889 fb_needed = true; 890 } 891 else { 892 first_fb = min(i, first_fb); 893 last_fb = max(i, last_fb); 894 } 895 changed = true; 896 break; 897 } 898 899 for (size_t j = 0; j < rects.size(); j++) { 900 const hwc_rect_t &other_rect = rects.itemAt(j); 901 if (intersect(visible_rect, other_rect)) 902 overlaps.push_back(intersection(visible_rect, other_rect)); 903 } 904 rects.push_back(visible_rect); 905 pixels_left -= pixels_needed; 906 windows_left--; 907 if (gsc_required) 908 gsc_used = true; 909 } 910 911 if (changed) 912 for (size_t i = first_fb; i < last_fb; i++) 913 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 914 } while(changed); 915 916 unsigned int nextWindow = 0; 917 918 for (size_t i = 0; i < contents->numHwLayers; i++) { 919 hwc_layer_1_t &layer = contents->hwLayers[i]; 920 921 if (fb_needed && i == first_fb) { 922 ALOGV("assigning framebuffer to window %u\n", 923 nextWindow); 924 nextWindow++; 925 continue; 926 } 927 928 if (layer.compositionType != HWC_FRAMEBUFFER && 929 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 930 ALOGV("assigning layer %u to window %u", i, nextWindow); 931 pdev->bufs.overlay_map[nextWindow] = i; 932 if (layer.compositionType == HWC_OVERLAY) { 933 private_handle_t *handle = 934 private_handle_t::dynamicCast(layer.handle); 935 if (exynos5_requires_gscaler(layer, handle->format)) { 936 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[FIMD_GSC_IDX]); 937 pdev->bufs.gsc_map[nextWindow].mode = 938 exynos5_gsc_map_t::GSC_M2M; 939 pdev->bufs.gsc_map[nextWindow].idx = FIMD_GSC_IDX; 940 } 941 } 942 nextWindow++; 943 } 944 } 945 946 if (!gsc_used) { 947 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 948 if (pdev->gsc[FIMD_GSC_IDX].dst_buf[j]) 949 pdev->alloc_device->free(pdev->alloc_device, 950 pdev->gsc[FIMD_GSC_IDX].dst_buf[j]); 951 memset(&pdev->gsc[FIMD_GSC_IDX], 0, sizeof(pdev->gsc[FIMD_GSC_IDX])); 952 } 953 954 if (fb_needed) 955 pdev->bufs.fb_window = first_fb; 956 else 957 pdev->bufs.fb_window = NO_FB_NEEDED; 958 959 return 0; 960} 961 962static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 963 hwc_display_contents_1_t* contents) 964{ 965 ALOGV("preparing %u layers for HDMI", contents->numHwLayers); 966 hwc_layer_1_t *video_layer = NULL; 967 968 for (size_t i = 0; i < contents->numHwLayers; i++) { 969 hwc_layer_1_t &layer = contents->hwLayers[i]; 970 971 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 972 ALOGV("\tlayer %u: framebuffer target", i); 973 continue; 974 } 975 976 if (layer.compositionType == HWC_BACKGROUND) { 977 ALOGV("\tlayer %u: background layer", i); 978 dump_layer(&layer); 979 continue; 980 } 981 982 if (layer.handle) { 983 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 984 if (h->flags & GRALLOC_USAGE_PROTECTED) { 985 if (!video_layer) { 986 video_layer = &layer; 987 layer.compositionType = HWC_OVERLAY; 988 ALOGV("\tlayer %u: video layer", i); 989 dump_layer(&layer); 990 continue; 991 } 992 } 993 } 994 995 layer.compositionType = HWC_FRAMEBUFFER; 996 dump_layer(&layer); 997 } 998 999 return 0; 1000} 1001 1002static int exynos5_prepare(hwc_composer_device_1_t *dev, 1003 size_t numDisplays, hwc_display_contents_1_t** displays) 1004{ 1005 if (!numDisplays || !displays) 1006 return 0; 1007 1008 exynos5_hwc_composer_device_1_t *pdev = 1009 (exynos5_hwc_composer_device_1_t *)dev; 1010 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1011 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1012 1013 if (pdev->hdmi_hpd) { 1014 hdmi_enable(pdev); 1015 } else { 1016 hdmi_disable(pdev); 1017 } 1018 1019 if (fimd_contents) { 1020 int err = exynos5_prepare_fimd(pdev, fimd_contents); 1021 if (err) 1022 return err; 1023 } 1024 1025 if (hdmi_contents) { 1026 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 1027 if (err) 1028 return err; 1029 } 1030 1031 return 0; 1032} 1033 1034static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 1035 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 1036 int gsc_idx, int dst_format) 1037{ 1038 ALOGV("configuring gscaler %u for memory-to-memory", AVAILABLE_GSC_UNITS[gsc_idx]); 1039 1040 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1041 buffer_handle_t dst_buf; 1042 private_handle_t *dst_handle; 1043 int ret = 0; 1044 1045 exynos_gsc_img src_cfg, dst_cfg; 1046 memset(&src_cfg, 0, sizeof(src_cfg)); 1047 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1048 1049 src_cfg.x = layer.sourceCrop.left; 1050 src_cfg.y = layer.sourceCrop.top; 1051 src_cfg.w = WIDTH(layer.sourceCrop); 1052 src_cfg.fw = src_handle->stride; 1053 src_cfg.h = HEIGHT(layer.sourceCrop); 1054 src_cfg.fh = src_handle->vstride; 1055 src_cfg.yaddr = src_handle->fd; 1056 if (exynos5_format_is_ycrcb(src_handle->format)) { 1057 src_cfg.uaddr = src_handle->fd2; 1058 src_cfg.vaddr = src_handle->fd1; 1059 } else { 1060 src_cfg.uaddr = src_handle->fd1; 1061 src_cfg.vaddr = src_handle->fd2; 1062 } 1063 src_cfg.format = src_handle->format; 1064 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1065 1066 dst_cfg.x = 0; 1067 dst_cfg.y = 0; 1068 dst_cfg.w = WIDTH(layer.displayFrame); 1069 dst_cfg.h = HEIGHT(layer.displayFrame); 1070 dst_cfg.rot = layer.transform; 1071 dst_cfg.drmMode = src_cfg.drmMode; 1072 dst_cfg.format = dst_format; 1073 1074 ALOGV("source configuration:"); 1075 dump_gsc_img(src_cfg); 1076 1077 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1078 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 1079 int dst_stride; 1080 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1081 GRALLOC_USAGE_SW_WRITE_NEVER | 1082 GRALLOC_USAGE_HW_COMPOSER; 1083 1084 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1085 usage |= GRALLOC_USAGE_PROTECTED; 1086 1087 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1088 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1089 1090 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1091 if (gsc_data->dst_buf[i]) { 1092 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1093 gsc_data->dst_buf[i] = NULL; 1094 } 1095 1096 int ret = alloc_device->alloc(alloc_device, w, h, 1097 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1098 &dst_stride); 1099 if (ret < 0) { 1100 ALOGE("failed to allocate destination buffer: %s", 1101 strerror(-ret)); 1102 goto err_alloc; 1103 } 1104 } 1105 1106 gsc_data->current_buf = 0; 1107 } 1108 1109 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1110 dst_handle = private_handle_t::dynamicCast(dst_buf); 1111 1112 dst_cfg.fw = dst_handle->stride; 1113 dst_cfg.fh = dst_handle->vstride; 1114 dst_cfg.yaddr = dst_handle->fd; 1115 1116 ALOGV("destination configuration:"); 1117 dump_gsc_img(dst_cfg); 1118 1119 gsc_data->gsc = exynos_gsc_create_exclusive(AVAILABLE_GSC_UNITS[gsc_idx], 1120 GSC_M2M_MODE, GSC_DUMMY); 1121 if (!gsc_data->gsc) { 1122 ALOGE("failed to create gscaler handle"); 1123 ret = -1; 1124 goto err_alloc; 1125 } 1126 1127 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1128 if (ret < 0) { 1129 ALOGE("failed to configure gscaler %u", gsc_idx); 1130 goto err_gsc_config; 1131 } 1132 1133 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1134 if (ret < 0) { 1135 ALOGE("failed to run gscaler %u", gsc_idx); 1136 goto err_gsc_config; 1137 } 1138 1139 gsc_data->src_cfg = src_cfg; 1140 gsc_data->dst_cfg = dst_cfg; 1141 1142 return 0; 1143 1144err_gsc_config: 1145 exynos_gsc_destroy(gsc_data->gsc); 1146 gsc_data->gsc = NULL; 1147err_alloc: 1148 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1149 if (gsc_data->dst_buf[i]) { 1150 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1151 gsc_data->dst_buf[i] = NULL; 1152 } 1153 } 1154 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1155 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1156 return ret; 1157} 1158 1159static void exynos5_config_handle(private_handle_t *handle, 1160 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1161 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1162 exynos5_hwc_composer_device_1_t *pdev) 1163{ 1164 uint32_t x, y; 1165 uint32_t w = WIDTH(displayFrame); 1166 uint32_t h = HEIGHT(displayFrame); 1167 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1168 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1169 1170 if (displayFrame.left < 0) { 1171 unsigned int crop = -displayFrame.left; 1172 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1173 crop); 1174 x = 0; 1175 w -= crop; 1176 offset += crop * bpp / 8; 1177 } else { 1178 x = displayFrame.left; 1179 } 1180 1181 if (displayFrame.right > pdev->xres) { 1182 unsigned int crop = displayFrame.right - pdev->xres; 1183 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1184 crop); 1185 w -= crop; 1186 } 1187 1188 if (displayFrame.top < 0) { 1189 unsigned int crop = -displayFrame.top; 1190 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1191 crop); 1192 y = 0; 1193 h -= crop; 1194 offset += handle->stride * crop * bpp / 8; 1195 } else { 1196 y = displayFrame.top; 1197 } 1198 1199 if (displayFrame.bottom > pdev->yres) { 1200 int crop = displayFrame.bottom - pdev->yres; 1201 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1202 crop); 1203 h -= crop; 1204 } 1205 1206 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1207 cfg.fd = handle->fd; 1208 cfg.x = x; 1209 cfg.y = y; 1210 cfg.w = w; 1211 cfg.h = h; 1212 cfg.format = exynos5_format_to_s3c_format(handle->format); 1213 cfg.offset = offset; 1214 cfg.stride = handle->stride * bpp / 8; 1215 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1216 cfg.fence_fd = fence_fd; 1217} 1218 1219static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1220 exynos5_hwc_composer_device_1_t *pdev) 1221{ 1222 if (layer->compositionType == HWC_BACKGROUND) { 1223 hwc_color_t color = layer->backgroundColor; 1224 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1225 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1226 cfg.x = 0; 1227 cfg.y = 0; 1228 cfg.w = pdev->xres; 1229 cfg.h = pdev->yres; 1230 return; 1231 } 1232 1233 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1234 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1235 layer->blending, layer->acquireFenceFd, cfg, pdev); 1236} 1237 1238static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1239 hwc_display_contents_1_t* contents) 1240{ 1241 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1242 struct s3c_fb_win_config_data win_data; 1243 struct s3c_fb_win_config *config = win_data.config; 1244 1245 memset(config, 0, sizeof(win_data.config)); 1246 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1247 config[i].fence_fd = -1; 1248 1249 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1250 int layer_idx = pdata->overlay_map[i]; 1251 if (layer_idx != -1) { 1252 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1253 private_handle_t *handle = 1254 private_handle_t::dynamicCast(layer.handle); 1255 1256 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1257 int gsc_idx = pdata->gsc_map[i].idx; 1258 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1259 1260 if (layer.acquireFenceFd != -1) { 1261 int err = sync_wait(layer.acquireFenceFd, 100); 1262 if (err != 0) 1263 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1264 i, strerror(errno)); 1265 close(layer.acquireFenceFd); 1266 } 1267 1268 // RGBX8888 surfaces are already in the right color order from the GPU, 1269 // RGB565 and YUV surfaces need the Gscaler to swap R & B 1270 int dst_format = HAL_PIXEL_FORMAT_BGRA_8888; 1271 if (exynos5_format_is_rgb(handle->format) && 1272 handle->format != HAL_PIXEL_FORMAT_RGB_565) 1273 dst_format = HAL_PIXEL_FORMAT_RGBX_8888; 1274 1275 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1276 gsc_idx, dst_format); 1277 if (err < 0) { 1278 ALOGE("failed to queue gscaler %u input for layer %u", 1279 gsc_idx, i); 1280 continue; 1281 } 1282 1283 err = exynos_gsc_stop_exclusive(gsc.gsc); 1284 exynos_gsc_destroy(gsc.gsc); 1285 gsc.gsc = NULL; 1286 if (err < 0) { 1287 ALOGE("failed to dequeue gscaler output for layer %u", i); 1288 continue; 1289 } 1290 1291 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1292 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1293 private_handle_t *dst_handle = 1294 private_handle_t::dynamicCast(dst_buf); 1295 hwc_rect_t sourceCrop = { 0, 0, 1296 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1297 exynos5_config_handle(dst_handle, sourceCrop, 1298 layer.displayFrame, layer.blending, -1, config[i], 1299 pdev); 1300 } else { 1301 exynos5_config_overlay(&layer, config[i], pdev); 1302 } 1303 } 1304 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1305 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1306 config[i].blending = S3C_FB_BLENDING_NONE; 1307 } 1308 1309 ALOGV("window %u configuration:", i); 1310 dump_config(config[i]); 1311 } 1312 1313 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1314 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1315 if (config[i].fence_fd != -1) 1316 close(config[i].fence_fd); 1317 if (ret < 0) { 1318 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1319 return ret; 1320 } 1321 1322 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1323 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1324 pdev->last_fb_window = pdata->fb_window; 1325 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1326 int layer_idx = pdata->overlay_map[i]; 1327 if (layer_idx != -1) { 1328 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1329 pdev->last_handles[i] = layer.handle; 1330 } 1331 } 1332 1333 return win_data.fence; 1334} 1335 1336static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1337 hwc_display_contents_1_t* contents) 1338{ 1339 if (!contents->dpy || !contents->sur) 1340 return 0; 1341 1342 hwc_layer_1_t *fb_layer = NULL; 1343 1344 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1345 for (size_t i = 0; i < contents->numHwLayers; i++) { 1346 if (contents->hwLayers[i].compositionType == 1347 HWC_FRAMEBUFFER_TARGET) { 1348 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1349 fb_layer = &contents->hwLayers[i]; 1350 break; 1351 } 1352 } 1353 1354 if (CC_UNLIKELY(!fb_layer)) { 1355 ALOGE("framebuffer target expected, but not provided"); 1356 return -EINVAL; 1357 } 1358 1359 ALOGV("framebuffer target buffer:"); 1360 dump_layer(fb_layer); 1361 } 1362 1363 int fence = exynos5_post_fimd(pdev, contents); 1364 if (fence < 0) 1365 return fence; 1366 1367 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1368 if (pdev->bufs.overlay_map[i] != -1) { 1369 hwc_layer_1_t &layer = 1370 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1371 int dup_fd = dup(fence); 1372 if (dup_fd < 0) 1373 ALOGW("release fence dup failed: %s", strerror(errno)); 1374 layer.releaseFenceFd = dup_fd; 1375 } 1376 } 1377 close(fence); 1378 1379 return 0; 1380} 1381 1382static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1383 hwc_display_contents_1_t* contents) 1384{ 1385 hwc_layer_1_t *fb_layer = NULL; 1386 hwc_layer_1_t *video_layer = NULL; 1387 1388 if (!pdev->hdmi_enabled) { 1389 for (size_t i = 0; i < contents->numHwLayers; i++) { 1390 hwc_layer_1_t &layer = contents->hwLayers[i]; 1391 if (layer.acquireFenceFd != -1) 1392 close(layer.acquireFenceFd); 1393 } 1394 return 0; 1395 } 1396 1397 for (size_t i = 0; i < contents->numHwLayers; i++) { 1398 hwc_layer_1_t &layer = contents->hwLayers[i]; 1399 1400 if (layer.flags & HWC_SKIP_LAYER) { 1401 ALOGV("HDMI skipping layer %d", i); 1402 continue; 1403 } 1404 1405 if (layer.compositionType == HWC_OVERLAY) { 1406 if (!layer.handle) 1407 continue; 1408 1409 ALOGV("HDMI video layer:"); 1410 dump_layer(&layer); 1411 1412 if (layer.acquireFenceFd != -1) { 1413 int err = sync_wait(layer.acquireFenceFd, 100); 1414 if (err != 0) 1415 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1416 i, strerror(errno)); 1417 close(layer.acquireFenceFd); 1418 layer.acquireFenceFd = -1; 1419 } 1420 1421 exynos5_gsc_data_t &gsc = pdev->gsc[HDMI_GSC_IDX]; 1422 exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1, 1423 HAL_PIXEL_FORMAT_RGBX_8888); 1424 1425 int err = exynos_gsc_stop_exclusive(gsc.gsc); 1426 exynos_gsc_destroy(gsc.gsc); 1427 gsc.gsc = NULL; 1428 if (err < 0) { 1429 ALOGE("failed to dequeue gscaler output for layer"); 1430 continue; 1431 } 1432 1433 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1434 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1435 private_handle_t *h = private_handle_t::dynamicCast(dst_buf); 1436 1437 hdmi_output(pdev, pdev->hdmi_layers[0], layer, h); 1438 video_layer = &layer; 1439 } 1440 1441 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1442 if (!layer.handle) 1443 continue; 1444 1445 ALOGV("HDMI FB layer:"); 1446 dump_layer(&layer); 1447 1448 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 1449 hdmi_output(pdev, pdev->hdmi_layers[1], layer, h); 1450 fb_layer = &layer; 1451 } 1452 } 1453 1454 if (!video_layer) 1455 hdmi_disable_layer(pdev, pdev->hdmi_layers[0]); 1456 if (!fb_layer) 1457 hdmi_disable_layer(pdev, pdev->hdmi_layers[1]); 1458 1459 return 0; 1460} 1461 1462static int exynos5_set(struct hwc_composer_device_1 *dev, 1463 size_t numDisplays, hwc_display_contents_1_t** displays) 1464{ 1465 if (!numDisplays || !displays) 1466 return 0; 1467 1468 exynos5_hwc_composer_device_1_t *pdev = 1469 (exynos5_hwc_composer_device_1_t *)dev; 1470 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1471 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1472 1473 if (fimd_contents) { 1474 int err = exynos5_set_fimd(pdev, fimd_contents); 1475 if (err) 1476 return err; 1477 } 1478 1479 if (hdmi_contents) { 1480 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1481 if (err) 1482 return err; 1483 } 1484 1485 return 0; 1486} 1487 1488static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1489 hwc_procs_t const* procs) 1490{ 1491 struct exynos5_hwc_composer_device_1_t* pdev = 1492 (struct exynos5_hwc_composer_device_1_t*)dev; 1493 pdev->procs = procs; 1494} 1495 1496static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1497{ 1498 struct exynos5_hwc_composer_device_1_t *pdev = 1499 (struct exynos5_hwc_composer_device_1_t *)dev; 1500 1501 switch (what) { 1502 case HWC_BACKGROUND_LAYER_SUPPORTED: 1503 // we support the background layer 1504 value[0] = 1; 1505 break; 1506 case HWC_VSYNC_PERIOD: 1507 // vsync period in nanosecond 1508 value[0] = pdev->vsync_period; 1509 break; 1510 default: 1511 // unsupported query 1512 return -EINVAL; 1513 } 1514 return 0; 1515} 1516 1517static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1518 int event, int enabled) 1519{ 1520 struct exynos5_hwc_composer_device_1_t *pdev = 1521 (struct exynos5_hwc_composer_device_1_t *)dev; 1522 1523 switch (event) { 1524 case HWC_EVENT_VSYNC: 1525 __u32 val = !!enabled; 1526 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1527 if (err < 0) { 1528 ALOGE("vsync ioctl failed"); 1529 return -errno; 1530 } 1531 1532 return 0; 1533 } 1534 1535 return -EINVAL; 1536} 1537 1538static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1539 const char *buff, int len) 1540{ 1541 const char *s = buff; 1542 s += strlen(s) + 1; 1543 1544 while (*s) { 1545 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1546 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1547 1548 s += strlen(s) + 1; 1549 if (s - buff >= len) 1550 break; 1551 } 1552 1553 if (pdev->hdmi_hpd) { 1554 if (hdmi_get_config(pdev)) { 1555 ALOGE("Error reading HDMI configuration"); 1556 pdev->hdmi_hpd = false; 1557 return; 1558 } 1559 } 1560 1561 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1562 if (pdev->hdmi_hpd) 1563 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1564 1565 /* hwc_dev->procs is set right after the device is opened, but there is 1566 * still a race condition where a hotplug event might occur after the open 1567 * but before the procs are registered. */ 1568 if (pdev->procs) 1569 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd); 1570} 1571 1572static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1573{ 1574 if (!pdev->procs) 1575 return; 1576 1577 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1578 if (err < 0) { 1579 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1580 return; 1581 } 1582 1583 char buf[4096]; 1584 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1585 if (err < 0) { 1586 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1587 return; 1588 } 1589 buf[sizeof(buf) - 1] = '\0'; 1590 1591 errno = 0; 1592 uint64_t timestamp = strtoull(buf, NULL, 0); 1593 if (!errno) 1594 pdev->procs->vsync(pdev->procs, 0, timestamp); 1595} 1596 1597static void *hwc_vsync_thread(void *data) 1598{ 1599 struct exynos5_hwc_composer_device_1_t *pdev = 1600 (struct exynos5_hwc_composer_device_1_t *)data; 1601 char uevent_desc[4096]; 1602 memset(uevent_desc, 0, sizeof(uevent_desc)); 1603 1604 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1605 1606 uevent_init(); 1607 1608 char temp[4096]; 1609 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1610 if (err < 0) { 1611 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1612 return NULL; 1613 } 1614 1615 struct pollfd fds[2]; 1616 fds[0].fd = pdev->vsync_fd; 1617 fds[0].events = POLLPRI; 1618 fds[1].fd = uevent_get_fd(); 1619 fds[1].events = POLLIN; 1620 1621 while (true) { 1622 int err = poll(fds, 2, -1); 1623 1624 if (err > 0) { 1625 if (fds[0].revents & POLLPRI) { 1626 handle_vsync_event(pdev); 1627 } 1628 else if (fds[1].revents & POLLIN) { 1629 int len = uevent_next_event(uevent_desc, 1630 sizeof(uevent_desc) - 2); 1631 1632 bool hdmi = !strcmp(uevent_desc, 1633 "change@/devices/virtual/switch/hdmi"); 1634 if (hdmi) 1635 handle_hdmi_uevent(pdev, uevent_desc, len); 1636 } 1637 } 1638 else if (err == -1) { 1639 if (errno == EINTR) 1640 break; 1641 ALOGE("error in vsync thread: %s", strerror(errno)); 1642 } 1643 } 1644 1645 return NULL; 1646} 1647 1648static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1649{ 1650 struct exynos5_hwc_composer_device_1_t *pdev = 1651 (struct exynos5_hwc_composer_device_1_t *)dev; 1652 1653 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1654 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1655 if (err < 0) { 1656 if (errno == EBUSY) 1657 ALOGI("%sblank ioctl failed (display already %sblanked)", 1658 blank ? "" : "un", blank ? "" : "un"); 1659 else 1660 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un", 1661 strerror(errno)); 1662 return -errno; 1663 } 1664 1665 if (pdev->hdmi_hpd) { 1666 if (blank && !pdev->hdmi_blanked) 1667 hdmi_disable(pdev); 1668 pdev->hdmi_blanked = !!blank; 1669 } 1670 1671 return 0; 1672} 1673 1674static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1675{ 1676 if (buff_len <= 0) 1677 return; 1678 1679 struct exynos5_hwc_composer_device_1_t *pdev = 1680 (struct exynos5_hwc_composer_device_1_t *)dev; 1681 1682 android::String8 result; 1683 1684 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1685 if (pdev->hdmi_enabled) 1686 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1687 result.append( 1688 " type | handle | color | blend | format | position | size | gsc \n" 1689 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1690 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1691 1692 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1693 struct s3c_fb_win_config &config = pdev->last_config[i]; 1694 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1695 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1696 "DISABLED", "-", "-", "-", "-", "-", "-"); 1697 } 1698 else { 1699 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1700 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1701 "-", config.color, "-", "-"); 1702 else 1703 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1704 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1705 intptr_t(pdev->last_handles[i]), 1706 "-", config.blending, config.format); 1707 1708 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1709 config.w, config.h); 1710 } 1711 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1712 result.appendFormat(" | %3s", "-"); 1713 else 1714 result.appendFormat(" | %3d", 1715 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1716 result.append("\n"); 1717 } 1718 1719 strlcpy(buff, result.string(), buff_len); 1720} 1721 1722static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1723 int disp, uint32_t *configs, size_t *numConfigs) 1724{ 1725 struct exynos5_hwc_composer_device_1_t *pdev = 1726 (struct exynos5_hwc_composer_device_1_t *)dev; 1727 1728 if (*numConfigs == 0) 1729 return 0; 1730 1731 if (disp == HWC_DISPLAY_PRIMARY) { 1732 configs[0] = 0; 1733 *numConfigs = 1; 1734 return 0; 1735 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1736 if (!pdev->hdmi_hpd) { 1737 return -EINVAL; 1738 } 1739 1740 int err = hdmi_get_config(pdev); 1741 if (err) { 1742 return -EINVAL; 1743 } 1744 1745 configs[0] = 0; 1746 *numConfigs = 1; 1747 return 0; 1748 } 1749 1750 return -EINVAL; 1751} 1752 1753static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1754 const uint32_t attribute) 1755{ 1756 switch(attribute) { 1757 case HWC_DISPLAY_VSYNC_PERIOD: 1758 return pdev->vsync_period; 1759 1760 case HWC_DISPLAY_WIDTH: 1761 return pdev->xres; 1762 1763 case HWC_DISPLAY_HEIGHT: 1764 return pdev->yres; 1765 1766 case HWC_DISPLAY_DPI_X: 1767 return pdev->xdpi; 1768 1769 case HWC_DISPLAY_DPI_Y: 1770 return pdev->ydpi; 1771 1772 default: 1773 ALOGE("unknown display attribute %u", attribute); 1774 return -EINVAL; 1775 } 1776} 1777 1778static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1779 const uint32_t attribute) 1780{ 1781 switch(attribute) { 1782 case HWC_DISPLAY_VSYNC_PERIOD: 1783 return pdev->vsync_period; 1784 1785 case HWC_DISPLAY_WIDTH: 1786 return pdev->hdmi_w; 1787 1788 case HWC_DISPLAY_HEIGHT: 1789 return pdev->hdmi_h; 1790 1791 case HWC_DISPLAY_DPI_X: 1792 case HWC_DISPLAY_DPI_Y: 1793 return 0; // unknown 1794 1795 default: 1796 ALOGE("unknown display attribute %u", attribute); 1797 return -EINVAL; 1798 } 1799} 1800 1801static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1802 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1803{ 1804 struct exynos5_hwc_composer_device_1_t *pdev = 1805 (struct exynos5_hwc_composer_device_1_t *)dev; 1806 1807 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1808 if (disp == HWC_DISPLAY_PRIMARY) 1809 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1810 else if (disp == HWC_DISPLAY_EXTERNAL) 1811 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1812 else { 1813 ALOGE("unknown display type %u", disp); 1814 return -EINVAL; 1815 } 1816 } 1817 1818 return 0; 1819} 1820 1821static int exynos5_close(hw_device_t* device); 1822 1823static int exynos5_open(const struct hw_module_t *module, const char *name, 1824 struct hw_device_t **device) 1825{ 1826 int ret; 1827 int refreshRate; 1828 int sw_fd; 1829 1830 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1831 return -EINVAL; 1832 } 1833 1834 struct exynos5_hwc_composer_device_1_t *dev; 1835 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1836 memset(dev, 0, sizeof(*dev)); 1837 1838 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1839 (const struct hw_module_t **)&dev->gralloc_module)) { 1840 ALOGE("failed to get gralloc hw module"); 1841 ret = -EINVAL; 1842 goto err_get_module; 1843 } 1844 1845 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1846 &dev->alloc_device)) { 1847 ALOGE("failed to open gralloc"); 1848 ret = -EINVAL; 1849 goto err_get_module; 1850 } 1851 1852 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1853 if (dev->fd < 0) { 1854 ALOGE("failed to open framebuffer"); 1855 ret = dev->fd; 1856 goto err_open_fb; 1857 } 1858 1859 struct fb_var_screeninfo info; 1860 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1861 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1862 ret = -errno; 1863 goto err_ioctl; 1864 } 1865 1866 refreshRate = 1000000000000LLU / 1867 ( 1868 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1869 * ( info.left_margin + info.right_margin + info.xres ) 1870 * info.pixclock 1871 ); 1872 1873 if (refreshRate == 0) { 1874 ALOGW("invalid refresh rate, assuming 60 Hz"); 1875 refreshRate = 60; 1876 } 1877 1878 dev->xres = 2560; 1879 dev->yres = 1600; 1880 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1881 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1882 dev->vsync_period = 1000000000 / refreshRate; 1883 1884 ALOGV("using\n" 1885 "xres = %d px\n" 1886 "yres = %d px\n" 1887 "width = %d mm (%f dpi)\n" 1888 "height = %d mm (%f dpi)\n" 1889 "refresh rate = %d Hz\n", 1890 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1891 info.height, dev->ydpi / 1000.0, refreshRate); 1892 1893 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1894 if (dev->hdmi_mixer0 < 0) { 1895 ALOGE("failed to open hdmi mixer0 subdev"); 1896 ret = dev->hdmi_mixer0; 1897 goto err_ioctl; 1898 } 1899 1900 dev->hdmi_layers[0].id = 0; 1901 dev->hdmi_layers[0].fd = open("/dev/video16", O_RDWR); 1902 if (dev->hdmi_layers[0].fd < 0) { 1903 ALOGE("failed to open hdmi layer0 device"); 1904 ret = dev->hdmi_layers[0].fd; 1905 goto err_mixer0; 1906 } 1907 1908 dev->hdmi_layers[1].id = 1; 1909 dev->hdmi_layers[1].fd = open("/dev/video17", O_RDWR); 1910 if (dev->hdmi_layers[1].fd < 0) { 1911 ALOGE("failed to open hdmi layer1 device"); 1912 ret = dev->hdmi_layers[1].fd; 1913 goto err_hdmi0; 1914 } 1915 1916 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1917 if (dev->vsync_fd < 0) { 1918 ALOGE("failed to open vsync attribute"); 1919 ret = dev->vsync_fd; 1920 goto err_hdmi1; 1921 } 1922 1923 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1924 if (sw_fd) { 1925 char val; 1926 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1927 dev->hdmi_hpd = true; 1928 if (hdmi_get_config(dev)) { 1929 ALOGE("Error reading HDMI configuration"); 1930 dev->hdmi_hpd = false; 1931 } 1932 } 1933 } 1934 1935 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1936 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1937 dev->base.common.module = const_cast<hw_module_t *>(module); 1938 dev->base.common.close = exynos5_close; 1939 1940 dev->base.prepare = exynos5_prepare; 1941 dev->base.set = exynos5_set; 1942 dev->base.eventControl = exynos5_eventControl; 1943 dev->base.blank = exynos5_blank; 1944 dev->base.query = exynos5_query; 1945 dev->base.registerProcs = exynos5_registerProcs; 1946 dev->base.dump = exynos5_dump; 1947 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1948 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1949 1950 *device = &dev->base.common; 1951 1952 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1953 if (ret) { 1954 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1955 ret = -ret; 1956 goto err_vsync; 1957 } 1958 1959 char value[PROPERTY_VALUE_MAX]; 1960 property_get("debug.hwc.force_gpu", value, "0"); 1961 dev->force_gpu = atoi(value); 1962 1963 return 0; 1964 1965err_vsync: 1966 close(dev->vsync_fd); 1967err_mixer0: 1968 close(dev->hdmi_mixer0); 1969err_hdmi1: 1970 close(dev->hdmi_layers[0].fd); 1971err_hdmi0: 1972 close(dev->hdmi_layers[1].fd); 1973err_ioctl: 1974 close(dev->fd); 1975err_open_fb: 1976 gralloc_close(dev->alloc_device); 1977err_get_module: 1978 free(dev); 1979 return ret; 1980} 1981 1982static int exynos5_close(hw_device_t *device) 1983{ 1984 struct exynos5_hwc_composer_device_1_t *dev = 1985 (struct exynos5_hwc_composer_device_1_t *)device; 1986 pthread_kill(dev->vsync_thread, SIGTERM); 1987 pthread_join(dev->vsync_thread, NULL); 1988 for (size_t i = 0; i < NUM_GSC_UNITS; i++) { 1989 if (dev->gsc[i].gsc) 1990 exynos_gsc_destroy(dev->gsc[i].gsc); 1991 for (size_t j = 0; i < NUM_GSC_DST_BUFS; j++) 1992 if (dev->gsc[i].dst_buf[j]) 1993 dev->alloc_device->free(dev->alloc_device, dev->gsc[i].dst_buf[j]); 1994 } 1995 gralloc_close(dev->alloc_device); 1996 close(dev->vsync_fd); 1997 close(dev->hdmi_mixer0); 1998 close(dev->hdmi_layers[0].fd); 1999 close(dev->hdmi_layers[1].fd); 2000 close(dev->fd); 2001 return 0; 2002} 2003 2004static struct hw_module_methods_t exynos5_hwc_module_methods = { 2005 open: exynos5_open, 2006}; 2007 2008hwc_module_t HAL_MODULE_INFO_SYM = { 2009 common: { 2010 tag: HARDWARE_MODULE_TAG, 2011 module_api_version: HWC_MODULE_API_VERSION_0_1, 2012 hal_api_version: HARDWARE_HAL_API_VERSION, 2013 id: HWC_HARDWARE_MODULE_ID, 2014 name: "Samsung exynos5 hwcomposer module", 2015 author: "Google", 2016 methods: &exynos5_hwc_module_methods, 2017 } 2018}; 2019