hwc.cpp revision efd9853a27a57c13b90fd9c2871aea206d4d6338
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const size_t FIMD_GSC_IDX = 0; 59const size_t HDMI_GSC_IDX = 1; 60const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 61const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 62 sizeof(AVAILABLE_GSC_UNITS[0]); 63const size_t BURSTLEN_BYTES = 16 * 8; 64const size_t NUM_HDMI_BUFFERS = 3; 65 66struct exynos5_hwc_composer_device_1_t; 67 68struct exynos5_gsc_map_t { 69 enum { 70 GSC_NONE = 0, 71 GSC_M2M, 72 // TODO: GSC_LOCAL_PATH 73 } mode; 74 int idx; 75}; 76 77struct exynos5_hwc_post_data_t { 78 int overlay_map[NUM_HW_WINDOWS]; 79 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 80 size_t fb_window; 81}; 82 83const size_t NUM_GSC_DST_BUFS = 3; 84struct exynos5_gsc_data_t { 85 void *gsc; 86 exynos_gsc_img src_cfg; 87 exynos_gsc_img dst_cfg; 88 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 89 size_t current_buf; 90}; 91 92struct hdmi_layer_t { 93 int id; 94 int fd; 95 bool enabled; 96 exynos_gsc_img cfg; 97 98 bool streaming; 99 size_t current_buf; 100 size_t queued_buf; 101}; 102 103struct exynos5_hwc_composer_device_1_t { 104 hwc_composer_device_1_t base; 105 106 int fd; 107 int vsync_fd; 108 exynos5_hwc_post_data_t bufs; 109 110 const private_module_t *gralloc_module; 111 alloc_device_t *alloc_device; 112 const hwc_procs_t *procs; 113 pthread_t vsync_thread; 114 int force_gpu; 115 116 int32_t xres; 117 int32_t yres; 118 int32_t xdpi; 119 int32_t ydpi; 120 int32_t vsync_period; 121 122 int hdmi_mixer0; 123 bool hdmi_hpd; 124 bool hdmi_enabled; 125 bool hdmi_blanked; 126 int hdmi_w; 127 int hdmi_h; 128 129 hdmi_layer_t hdmi_layers[2]; 130 131 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 132 133 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 134 size_t last_fb_window; 135 const void *last_handles[NUM_HW_WINDOWS]; 136 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 137}; 138 139static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 140 size_t gsc_idx); 141 142static void dump_handle(private_handle_t *h) 143{ 144 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 145 h->format, h->width, h->height, h->stride, h->vstride); 146} 147 148static void dump_layer(hwc_layer_1_t const *l) 149{ 150 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 151 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 152 l->compositionType, l->flags, l->handle, l->transform, 153 l->blending, 154 l->sourceCrop.left, 155 l->sourceCrop.top, 156 l->sourceCrop.right, 157 l->sourceCrop.bottom, 158 l->displayFrame.left, 159 l->displayFrame.top, 160 l->displayFrame.right, 161 l->displayFrame.bottom); 162 163 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 164 dump_handle(private_handle_t::dynamicCast(l->handle)); 165} 166 167static void dump_config(s3c_fb_win_config &c) 168{ 169 ALOGV("\tstate = %u", c.state); 170 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 171 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 172 "x = %d, y = %d, w = %u, h = %u, " 173 "format = %u, blending = %u", 174 c.fd, c.offset, c.stride, 175 c.x, c.y, c.w, c.h, 176 c.format, c.blending); 177 } 178 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 179 ALOGV("\t\tcolor = %u", c.color); 180 } 181} 182 183static void dump_gsc_img(exynos_gsc_img &c) 184{ 185 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 186 c.x, c.y, c.w, c.h, c.fw, c.fh); 187 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 188 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 189} 190 191inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 192inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 193template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 194template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 195 196static bool is_transformed(const hwc_layer_1_t &layer) 197{ 198 return layer.transform != 0; 199} 200 201static bool is_rotated(const hwc_layer_1_t &layer) 202{ 203 return (layer.transform & HAL_TRANSFORM_ROT_90) || 204 (layer.transform & HAL_TRANSFORM_ROT_180); 205} 206 207static bool is_scaled(const hwc_layer_1_t &layer) 208{ 209 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 210 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 211} 212 213static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 214{ 215 return c1.x != c2.x || 216 c1.y != c2.y || 217 c1.w != c2.w || 218 c1.h != c2.h || 219 c1.format != c2.format || 220 c1.rot != c2.rot || 221 c1.cacheable != c2.cacheable || 222 c1.drmMode != c2.drmMode; 223} 224 225static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 226{ 227 return gsc_dst_cfg_changed(c1, c2) || 228 c1.fw != c2.fw || 229 c1.fh != c2.fh; 230} 231 232static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 233{ 234 switch (format) { 235 case HAL_PIXEL_FORMAT_RGBA_8888: 236 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 237 case HAL_PIXEL_FORMAT_RGBX_8888: 238 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 239 case HAL_PIXEL_FORMAT_RGBA_5551: 240 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 241 case HAL_PIXEL_FORMAT_RGB_565: 242 return S3C_FB_PIXEL_FORMAT_RGB_565; 243 case HAL_PIXEL_FORMAT_BGRA_8888: 244 return S3C_FB_PIXEL_FORMAT_BGRA_8888; 245 default: 246 return S3C_FB_PIXEL_FORMAT_MAX; 247 } 248} 249 250static bool exynos5_format_is_supported(int format) 251{ 252 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 253} 254 255static bool exynos5_format_is_rgb(int format) 256{ 257 switch (format) { 258 case HAL_PIXEL_FORMAT_RGBA_8888: 259 case HAL_PIXEL_FORMAT_RGBX_8888: 260 case HAL_PIXEL_FORMAT_RGB_888: 261 case HAL_PIXEL_FORMAT_RGB_565: 262 case HAL_PIXEL_FORMAT_BGRA_8888: 263 case HAL_PIXEL_FORMAT_RGBA_5551: 264 case HAL_PIXEL_FORMAT_RGBA_4444: 265 return true; 266 267 default: 268 return false; 269 } 270} 271 272static bool exynos5_format_is_supported_by_gscaler(int format) 273{ 274 switch (format) { 275 case HAL_PIXEL_FORMAT_RGBX_8888: 276 case HAL_PIXEL_FORMAT_RGB_565: 277 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 278 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 279 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 280 return true; 281 282 default: 283 return false; 284 } 285} 286 287static bool exynos5_format_is_ycrcb(int format) 288{ 289 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 290} 291 292static bool exynos5_format_requires_gscaler(int format) 293{ 294 return (exynos5_format_is_supported_by_gscaler(format) && 295 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565)); 296} 297 298static uint8_t exynos5_format_to_bpp(int format) 299{ 300 switch (format) { 301 case HAL_PIXEL_FORMAT_RGBA_8888: 302 case HAL_PIXEL_FORMAT_RGBX_8888: 303 case HAL_PIXEL_FORMAT_BGRA_8888: 304 return 32; 305 306 case HAL_PIXEL_FORMAT_RGBA_5551: 307 case HAL_PIXEL_FORMAT_RGBA_4444: 308 case HAL_PIXEL_FORMAT_RGB_565: 309 return 16; 310 311 default: 312 ALOGW("unrecognized pixel format %u", format); 313 return 0; 314 } 315} 316 317static bool is_x_aligned(const hwc_layer_1_t &layer, int format) 318{ 319 if (!exynos5_format_is_supported(format)) 320 return true; 321 322 uint8_t bpp = exynos5_format_to_bpp(format); 323 uint8_t pixel_alignment = 32 / bpp; 324 325 return (layer.displayFrame.left % pixel_alignment) == 0 && 326 (layer.displayFrame.right % pixel_alignment) == 0; 327} 328 329static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 330 bool local_path) 331{ 332 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 333 334 int max_w = is_rotated(layer) ? 2048 : 4800; 335 int max_h = is_rotated(layer) ? 2048 : 3344; 336 337 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 338 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 339 // HAL_TRANSFORM_ROT_180 340 341 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 342 int dest_w, dest_h; 343 if (rot90or270) { 344 dest_w = HEIGHT(layer.displayFrame); 345 dest_h = WIDTH(layer.displayFrame); 346 } else { 347 dest_w = WIDTH(layer.displayFrame); 348 dest_h = HEIGHT(layer.displayFrame); 349 } 350 int max_downscale = local_path ? 4 : 16; 351 const int max_upscale = 8; 352 353 return exynos5_format_is_supported_by_gscaler(format) && 354 handle->stride <= max_w && 355 handle->stride % GSC_W_ALIGNMENT == 0 && 356 src_w <= dest_w * max_downscale && 357 dest_w <= src_w * max_upscale && 358 handle->vstride <= max_h && 359 handle->vstride % GSC_H_ALIGNMENT == 0 && 360 src_h <= dest_h * max_downscale && 361 dest_h <= src_h * max_upscale && 362 // per 46.2 363 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 364 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 365 // per 46.3.1.6 366} 367 368static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 369{ 370 return exynos5_format_requires_gscaler(format) || is_scaled(layer) 371 || is_transformed(layer) || !is_x_aligned(layer, format); 372} 373 374int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 375{ 376 struct v4l2_dv_preset preset; 377 struct v4l2_dv_enum_preset enum_preset; 378 int index = 0; 379 bool found = false; 380 int ret; 381 382 if (ioctl(dev->hdmi_layers[0].fd, VIDIOC_G_DV_PRESET, &preset) < 0) { 383 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 384 return -1; 385 } 386 387 while (true) { 388 enum_preset.index = index++; 389 ret = ioctl(dev->hdmi_layers[0].fd, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 390 391 if (ret < 0) { 392 if (errno == EINVAL) 393 break; 394 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 395 return -1; 396 } 397 398 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 399 __func__, enum_preset.index, enum_preset.preset, 400 enum_preset.width, enum_preset.height, enum_preset.name); 401 402 if (preset.preset == enum_preset.preset) { 403 dev->hdmi_w = enum_preset.width; 404 dev->hdmi_h = enum_preset.height; 405 found = true; 406 } 407 } 408 409 return found ? 0 : -1; 410} 411 412static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 413{ 414 switch (blending) { 415 case HWC_BLENDING_NONE: 416 return S3C_FB_BLENDING_NONE; 417 case HWC_BLENDING_PREMULT: 418 return S3C_FB_BLENDING_PREMULT; 419 case HWC_BLENDING_COVERAGE: 420 return S3C_FB_BLENDING_COVERAGE; 421 422 default: 423 return S3C_FB_BLENDING_MAX; 424 } 425} 426 427static bool exynos5_blending_is_supported(int32_t blending) 428{ 429 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 430} 431 432 433static int hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t *dev, 434 hdmi_layer_t &hl) 435{ 436 if (hl.enabled) 437 return 0; 438 439 struct v4l2_requestbuffers reqbuf; 440 memset(&reqbuf, 0, sizeof(reqbuf)); 441 reqbuf.count = NUM_HDMI_BUFFERS; 442 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 443 reqbuf.memory = V4L2_MEMORY_DMABUF; 444 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) { 445 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 446 return -1; 447 } 448 449 if (reqbuf.count != NUM_HDMI_BUFFERS) { 450 ALOGE("%s: layer%d: didn't get buffer", __func__, hl.id); 451 return -1; 452 } 453 454 if (hl.id == 1) { 455 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_PIXEL_BLEND_ENABLE, 1) < 0) { 456 ALOGE("%s: layer%d: PIXEL_BLEND_ENABLE failed %d", __func__, 457 hl.id, errno); 458 return -1; 459 } 460 } 461 462 ALOGV("%s: layer%d enabled", __func__, hl.id); 463 hl.enabled = true; 464 return 0; 465} 466 467static void hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t *dev, 468 hdmi_layer_t &hl) 469{ 470 if (!hl.enabled) 471 return; 472 473 if (hl.streaming) { 474 if (exynos_v4l2_streamoff(hl.fd, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) 475 ALOGE("%s: layer%d: streamoff failed %d", __func__, hl.id, errno); 476 hl.streaming = false; 477 } 478 479 struct v4l2_requestbuffers reqbuf; 480 memset(&reqbuf, 0, sizeof(reqbuf)); 481 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 482 reqbuf.memory = V4L2_MEMORY_DMABUF; 483 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) 484 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 485 486 memset(&hl.cfg, 0, sizeof(hl.cfg)); 487 hl.current_buf = 0; 488 hl.queued_buf = 0; 489 hl.enabled = false; 490 491 ALOGV("%s: layer%d disabled", __func__, hl.id); 492} 493 494static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 495{ 496 if (dev->hdmi_enabled) 497 return 0; 498 499 if (dev->hdmi_blanked) 500 return 0; 501 502 struct v4l2_subdev_format sd_fmt; 503 memset(&sd_fmt, 0, sizeof(sd_fmt)); 504 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SINK; 505 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 506 sd_fmt.format.width = dev->hdmi_w; 507 sd_fmt.format.height = dev->hdmi_h; 508 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 509 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 510 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 511 return -1; 512 } 513 514 struct v4l2_subdev_crop sd_crop; 515 memset(&sd_crop, 0, sizeof(sd_crop)); 516 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SINK; 517 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 518 sd_crop.rect.width = dev->hdmi_w; 519 sd_crop.rect.height = dev->hdmi_h; 520 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 521 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 522 return -1; 523 } 524 525 memset(&sd_fmt, 0, sizeof(sd_fmt)); 526 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 527 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 528 sd_fmt.format.width = dev->hdmi_w; 529 sd_fmt.format.height = dev->hdmi_h; 530 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 531 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 532 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 533 return -1; 534 } 535 536 memset(&sd_crop, 0, sizeof(sd_crop)); 537 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 538 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 539 sd_crop.rect.width = dev->hdmi_w; 540 sd_crop.rect.height = dev->hdmi_h; 541 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 542 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 543 return -1; 544 } 545 546 hdmi_enable_layer(dev, dev->hdmi_layers[1]); 547 548 dev->hdmi_enabled = true; 549 return 0; 550} 551 552static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 553{ 554 if (!dev->hdmi_enabled) 555 return; 556 557 hdmi_disable_layer(dev, dev->hdmi_layers[0]); 558 hdmi_disable_layer(dev, dev->hdmi_layers[1]); 559 560 exynos5_cleanup_gsc_m2m(dev, HDMI_GSC_IDX); 561 dev->hdmi_enabled = false; 562} 563 564static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, 565 hdmi_layer_t &hl, 566 hwc_layer_1_t &layer, 567 private_handle_t *h) 568{ 569 int ret = 0; 570 571 exynos_gsc_img cfg; 572 memset(&cfg, 0, sizeof(cfg)); 573 cfg.x = layer.displayFrame.left; 574 cfg.y = layer.displayFrame.top; 575 cfg.w = WIDTH(layer.displayFrame); 576 cfg.h = HEIGHT(layer.displayFrame); 577 578 if (gsc_src_cfg_changed(hl.cfg, cfg)) { 579 hdmi_disable_layer(dev, hl); 580 581 struct v4l2_format fmt; 582 memset(&fmt, 0, sizeof(fmt)); 583 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 584 fmt.fmt.pix_mp.width = cfg.w; 585 fmt.fmt.pix_mp.height = cfg.h; 586 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 587 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 588 fmt.fmt.pix_mp.num_planes = 1; 589 ret = exynos_v4l2_s_fmt(hl.fd, &fmt); 590 if (ret < 0) { 591 ALOGE("%s: layer%d: s_fmt failed %d", __func__, hl.id, errno); 592 goto err; 593 } 594 595 struct v4l2_subdev_crop sd_crop; 596 memset(&sd_crop, 0, sizeof(sd_crop)); 597 if (hl.id == 0) 598 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 599 else 600 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 601 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 602 sd_crop.rect.left = cfg.x; 603 sd_crop.rect.top = cfg.y; 604 sd_crop.rect.width = cfg.w; 605 sd_crop.rect.height = cfg.h; 606 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 607 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 608 goto err; 609 } 610 611 hdmi_enable_layer(dev, hl); 612 613 ALOGV("HDMI layer%d configuration:", hl.id); 614 dump_gsc_img(cfg); 615 hl.cfg = cfg; 616 } 617 618 struct v4l2_buffer buffer; 619 struct v4l2_plane planes[1]; 620 621 if (hl.queued_buf == NUM_HDMI_BUFFERS) { 622 memset(&buffer, 0, sizeof(buffer)); 623 memset(planes, 0, sizeof(planes)); 624 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 625 buffer.memory = V4L2_MEMORY_DMABUF; 626 buffer.length = 1; 627 buffer.m.planes = planes; 628 ret = exynos_v4l2_dqbuf(hl.fd, &buffer); 629 if (ret < 0) { 630 ALOGE("%s: layer%d: dqbuf failed %d", __func__, hl.id, errno); 631 goto err; 632 } 633 hl.queued_buf--; 634 } 635 636 memset(&buffer, 0, sizeof(buffer)); 637 memset(planes, 0, sizeof(planes)); 638 buffer.index = hl.current_buf; 639 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 640 buffer.memory = V4L2_MEMORY_DMABUF; 641 buffer.flags = V4L2_BUF_FLAG_USE_SYNC; 642 buffer.reserved = layer.acquireFenceFd; 643 buffer.length = 1; 644 buffer.m.planes = planes; 645 buffer.m.planes[0].m.fd = h->fd; 646 if (exynos_v4l2_qbuf(hl.fd, &buffer) < 0) { 647 ALOGE("%s: layer%d: qbuf failed %d", __func__, hl.id, errno); 648 ret = -1; 649 goto err; 650 } 651 652 layer.releaseFenceFd = buffer.reserved; 653 654 hl.queued_buf++; 655 hl.current_buf = (hl.current_buf + 1) % NUM_HDMI_BUFFERS; 656 657 if (!hl.streaming) { 658 if (exynos_v4l2_streamon(hl.fd, buffer.type) < 0) { 659 ALOGE("%s: layer%d: streamon failed %d", __func__, hl.id, errno); 660 ret = -1; 661 goto err; 662 } 663 hl.streaming = true; 664 } 665 666err: 667 if (layer.acquireFenceFd >= 0) 668 close(layer.acquireFenceFd); 669 670 return ret; 671} 672 673bool exynos5_is_offscreen(hwc_layer_1_t &layer, 674 struct exynos5_hwc_composer_device_1_t *pdev) 675{ 676 return layer.sourceCrop.left > pdev->xres || 677 layer.sourceCrop.right < 0 || 678 layer.sourceCrop.top > pdev->yres || 679 layer.sourceCrop.bottom < 0; 680} 681 682size_t exynos5_visible_width(hwc_layer_1_t &layer, int format, 683 struct exynos5_hwc_composer_device_1_t *pdev) 684{ 685 int bpp; 686 if (exynos5_requires_gscaler(layer, format)) 687 bpp = 32; 688 else 689 bpp = exynos5_format_to_bpp(format); 690 int left = max(layer.displayFrame.left, 0); 691 int right = min(layer.displayFrame.right, pdev->xres); 692 693 return (right - left) * bpp / 8; 694} 695 696bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 697 struct exynos5_hwc_composer_device_1_t *pdev) 698{ 699 if (layer.flags & HWC_SKIP_LAYER) { 700 ALOGV("\tlayer %u: skipping", i); 701 return false; 702 } 703 704 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 705 706 if (!handle) { 707 ALOGV("\tlayer %u: handle is NULL", i); 708 return false; 709 } 710 if (!exynos5_format_is_rgb(handle->format) && 711 !exynos5_format_is_supported_by_gscaler(handle->format)) { 712 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 713 return false; 714 } 715 716 if (exynos5_requires_gscaler(layer, handle->format)) { 717 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 718 ALOGV("\tlayer %u: gscaler required but not supported", i); 719 return false; 720 } 721 } else { 722 if (!exynos5_format_is_supported(handle->format)) { 723 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 724 return false; 725 } 726 } 727 if (!exynos5_blending_is_supported(layer.blending)) { 728 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 729 return false; 730 } 731 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 732 ALOGW("\tlayer %u: off-screen", i); 733 return false; 734 } 735 if (exynos5_visible_width(layer, handle->format, pdev) < BURSTLEN_BYTES) { 736 ALOGV("\tlayer %u: visible area is too narrow", i); 737 return false; 738 } 739 740 return true; 741} 742 743inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 744{ 745 return !(r1.left > r2.right || 746 r1.right < r2.left || 747 r1.top > r2.bottom || 748 r1.bottom < r2.top); 749} 750 751inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 752{ 753 hwc_rect i; 754 i.top = max(r1.top, r2.top); 755 i.bottom = min(r1.bottom, r2.bottom); 756 i.left = max(r1.left, r2.left); 757 i.right = min(r1.right, r2.right); 758 return i; 759} 760 761static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 762 hwc_display_contents_1_t* contents) 763{ 764 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 765 766 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 767 768 bool force_fb = pdev->force_gpu; 769 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 770 pdev->bufs.overlay_map[i] = -1; 771 772 bool fb_needed = false; 773 size_t first_fb = 0, last_fb = 0; 774 775 // find unsupported overlays 776 for (size_t i = 0; i < contents->numHwLayers; i++) { 777 hwc_layer_1_t &layer = contents->hwLayers[i]; 778 779 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 780 ALOGV("\tlayer %u: framebuffer target", i); 781 continue; 782 } 783 784 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 785 ALOGV("\tlayer %u: background supported", i); 786 dump_layer(&contents->hwLayers[i]); 787 continue; 788 } 789 790 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 791 !force_fb) { 792 ALOGV("\tlayer %u: overlay supported", i); 793 layer.compositionType = HWC_OVERLAY; 794 dump_layer(&contents->hwLayers[i]); 795 continue; 796 } 797 798 if (!fb_needed) { 799 first_fb = i; 800 fb_needed = true; 801 } 802 last_fb = i; 803 layer.compositionType = HWC_FRAMEBUFFER; 804 805 dump_layer(&contents->hwLayers[i]); 806 } 807 808 // can't composite overlays sandwiched between framebuffers 809 if (fb_needed) 810 for (size_t i = first_fb; i < last_fb; i++) 811 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 812 813 // Incrementally try to add our supported layers to hardware windows. 814 // If adding a layer would violate a hardware constraint, force it 815 // into the framebuffer and try again. (Revisiting the entire list is 816 // necessary because adding a layer to the framebuffer can cause other 817 // windows to retroactively violate constraints.) 818 bool changed; 819 bool gsc_used; 820 do { 821 android::Vector<hwc_rect> rects; 822 android::Vector<hwc_rect> overlaps; 823 size_t pixels_left, windows_left; 824 825 gsc_used = false; 826 827 if (fb_needed) { 828 hwc_rect_t fb_rect; 829 fb_rect.top = fb_rect.left = 0; 830 fb_rect.right = pdev->xres - 1; 831 fb_rect.bottom = pdev->yres - 1; 832 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 833 windows_left = NUM_HW_WINDOWS - 1; 834 rects.push_back(fb_rect); 835 } 836 else { 837 pixels_left = MAX_PIXELS; 838 windows_left = NUM_HW_WINDOWS; 839 } 840 841 changed = false; 842 843 for (size_t i = 0; i < contents->numHwLayers; i++) { 844 hwc_layer_1_t &layer = contents->hwLayers[i]; 845 if ((layer.flags & HWC_SKIP_LAYER) || 846 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 847 continue; 848 849 private_handle_t *handle = private_handle_t::dynamicCast( 850 layer.handle); 851 852 // we've already accounted for the framebuffer above 853 if (layer.compositionType == HWC_FRAMEBUFFER) 854 continue; 855 856 // only layer 0 can be HWC_BACKGROUND, so we can 857 // unconditionally allow it without extra checks 858 if (layer.compositionType == HWC_BACKGROUND) { 859 windows_left--; 860 continue; 861 } 862 863 size_t pixels_needed = WIDTH(layer.displayFrame) * 864 HEIGHT(layer.displayFrame); 865 bool can_compose = windows_left && pixels_needed <= pixels_left; 866 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 867 if (gsc_required) 868 can_compose = can_compose && !gsc_used; 869 870 // hwc_rect_t right and bottom values are normally exclusive; 871 // the intersection logic is simpler if we make them inclusive 872 hwc_rect_t visible_rect = layer.displayFrame; 873 visible_rect.right--; visible_rect.bottom--; 874 875 // no more than 2 layers can overlap on a given pixel 876 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 877 if (intersect(visible_rect, overlaps.itemAt(j))) 878 can_compose = false; 879 } 880 881 if (!can_compose) { 882 layer.compositionType = HWC_FRAMEBUFFER; 883 if (!fb_needed) { 884 first_fb = last_fb = i; 885 fb_needed = true; 886 } 887 else { 888 first_fb = min(i, first_fb); 889 last_fb = max(i, last_fb); 890 } 891 changed = true; 892 break; 893 } 894 895 for (size_t j = 0; j < rects.size(); j++) { 896 const hwc_rect_t &other_rect = rects.itemAt(j); 897 if (intersect(visible_rect, other_rect)) 898 overlaps.push_back(intersection(visible_rect, other_rect)); 899 } 900 rects.push_back(visible_rect); 901 pixels_left -= pixels_needed; 902 windows_left--; 903 if (gsc_required) 904 gsc_used = true; 905 } 906 907 if (changed) 908 for (size_t i = first_fb; i < last_fb; i++) 909 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 910 } while(changed); 911 912 unsigned int nextWindow = 0; 913 914 for (size_t i = 0; i < contents->numHwLayers; i++) { 915 hwc_layer_1_t &layer = contents->hwLayers[i]; 916 917 if (fb_needed && i == first_fb) { 918 ALOGV("assigning framebuffer to window %u\n", 919 nextWindow); 920 nextWindow++; 921 continue; 922 } 923 924 if (layer.compositionType != HWC_FRAMEBUFFER && 925 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 926 ALOGV("assigning layer %u to window %u", i, nextWindow); 927 pdev->bufs.overlay_map[nextWindow] = i; 928 if (layer.compositionType == HWC_OVERLAY) { 929 private_handle_t *handle = 930 private_handle_t::dynamicCast(layer.handle); 931 if (exynos5_requires_gscaler(layer, handle->format)) { 932 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[FIMD_GSC_IDX]); 933 pdev->bufs.gsc_map[nextWindow].mode = 934 exynos5_gsc_map_t::GSC_M2M; 935 pdev->bufs.gsc_map[nextWindow].idx = FIMD_GSC_IDX; 936 } 937 } 938 nextWindow++; 939 } 940 } 941 942 if (!gsc_used) 943 exynos5_cleanup_gsc_m2m(pdev, FIMD_GSC_IDX); 944 945 if (fb_needed) 946 pdev->bufs.fb_window = first_fb; 947 else 948 pdev->bufs.fb_window = NO_FB_NEEDED; 949 950 return 0; 951} 952 953static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 954 hwc_display_contents_1_t* contents) 955{ 956 ALOGV("preparing %u layers for HDMI", contents->numHwLayers); 957 hwc_layer_1_t *video_layer = NULL; 958 959 for (size_t i = 0; i < contents->numHwLayers; i++) { 960 hwc_layer_1_t &layer = contents->hwLayers[i]; 961 962 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 963 ALOGV("\tlayer %u: framebuffer target", i); 964 continue; 965 } 966 967 if (layer.compositionType == HWC_BACKGROUND) { 968 ALOGV("\tlayer %u: background layer", i); 969 dump_layer(&layer); 970 continue; 971 } 972 973 if (layer.handle) { 974 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 975 if (h->flags & GRALLOC_USAGE_PROTECTED) { 976 if (!video_layer) { 977 video_layer = &layer; 978 layer.compositionType = HWC_OVERLAY; 979 ALOGV("\tlayer %u: video layer", i); 980 dump_layer(&layer); 981 continue; 982 } 983 } 984 } 985 986 layer.compositionType = HWC_FRAMEBUFFER; 987 dump_layer(&layer); 988 } 989 990 return 0; 991} 992 993static int exynos5_prepare(hwc_composer_device_1_t *dev, 994 size_t numDisplays, hwc_display_contents_1_t** displays) 995{ 996 if (!numDisplays || !displays) 997 return 0; 998 999 exynos5_hwc_composer_device_1_t *pdev = 1000 (exynos5_hwc_composer_device_1_t *)dev; 1001 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1002 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1003 1004 if (pdev->hdmi_hpd) { 1005 hdmi_enable(pdev); 1006 } else { 1007 hdmi_disable(pdev); 1008 } 1009 1010 if (fimd_contents) { 1011 int err = exynos5_prepare_fimd(pdev, fimd_contents); 1012 if (err) 1013 return err; 1014 } 1015 1016 if (hdmi_contents) { 1017 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 1018 if (err) 1019 return err; 1020 } 1021 1022 return 0; 1023} 1024 1025static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 1026 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 1027 int gsc_idx, int dst_format) 1028{ 1029 ALOGV("configuring gscaler %u for memory-to-memory", AVAILABLE_GSC_UNITS[gsc_idx]); 1030 1031 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1032 buffer_handle_t dst_buf; 1033 private_handle_t *dst_handle; 1034 int ret = 0; 1035 1036 exynos_gsc_img src_cfg, dst_cfg; 1037 memset(&src_cfg, 0, sizeof(src_cfg)); 1038 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1039 1040 src_cfg.x = layer.sourceCrop.left; 1041 src_cfg.y = layer.sourceCrop.top; 1042 src_cfg.w = WIDTH(layer.sourceCrop); 1043 src_cfg.fw = src_handle->stride; 1044 src_cfg.h = HEIGHT(layer.sourceCrop); 1045 src_cfg.fh = src_handle->vstride; 1046 src_cfg.yaddr = src_handle->fd; 1047 if (exynos5_format_is_ycrcb(src_handle->format)) { 1048 src_cfg.uaddr = src_handle->fd2; 1049 src_cfg.vaddr = src_handle->fd1; 1050 } else { 1051 src_cfg.uaddr = src_handle->fd1; 1052 src_cfg.vaddr = src_handle->fd2; 1053 } 1054 src_cfg.format = src_handle->format; 1055 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1056 1057 dst_cfg.x = 0; 1058 dst_cfg.y = 0; 1059 dst_cfg.w = WIDTH(layer.displayFrame); 1060 dst_cfg.h = HEIGHT(layer.displayFrame); 1061 dst_cfg.rot = layer.transform; 1062 dst_cfg.drmMode = src_cfg.drmMode; 1063 dst_cfg.format = dst_format; 1064 1065 ALOGV("source configuration:"); 1066 dump_gsc_img(src_cfg); 1067 1068 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1069 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 1070 int dst_stride; 1071 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1072 GRALLOC_USAGE_SW_WRITE_NEVER | 1073 GRALLOC_USAGE_HW_COMPOSER; 1074 1075 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1076 usage |= GRALLOC_USAGE_PROTECTED; 1077 1078 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1079 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1080 1081 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1082 if (gsc_data->dst_buf[i]) { 1083 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1084 gsc_data->dst_buf[i] = NULL; 1085 } 1086 1087 int ret = alloc_device->alloc(alloc_device, w, h, 1088 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1089 &dst_stride); 1090 if (ret < 0) { 1091 ALOGE("failed to allocate destination buffer: %s", 1092 strerror(-ret)); 1093 goto err_alloc; 1094 } 1095 } 1096 1097 gsc_data->current_buf = 0; 1098 } 1099 1100 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1101 dst_handle = private_handle_t::dynamicCast(dst_buf); 1102 1103 dst_cfg.fw = dst_handle->stride; 1104 dst_cfg.fh = dst_handle->vstride; 1105 dst_cfg.yaddr = dst_handle->fd; 1106 1107 ALOGV("destination configuration:"); 1108 dump_gsc_img(dst_cfg); 1109 1110 if (gsc_data->gsc) { 1111 ALOGV("reusing open gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1112 } else { 1113 ALOGV("opening gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1114 gsc_data->gsc = exynos_gsc_create_exclusive( 1115 AVAILABLE_GSC_UNITS[gsc_idx], GSC_M2M_MODE, GSC_DUMMY); 1116 if (!gsc_data->gsc) { 1117 ALOGE("failed to create gscaler handle"); 1118 ret = -1; 1119 goto err_alloc; 1120 } 1121 } 1122 1123 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1124 if (ret < 0) { 1125 ALOGE("failed to configure gscaler %u", gsc_idx); 1126 goto err_gsc_config; 1127 } 1128 1129 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1130 if (ret < 0) { 1131 ALOGE("failed to run gscaler %u", gsc_idx); 1132 goto err_gsc_config; 1133 } 1134 1135 gsc_data->src_cfg = src_cfg; 1136 gsc_data->dst_cfg = dst_cfg; 1137 1138 return 0; 1139 1140err_gsc_config: 1141 exynos_gsc_destroy(gsc_data->gsc); 1142 gsc_data->gsc = NULL; 1143err_alloc: 1144 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1145 if (gsc_data->dst_buf[i]) { 1146 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1147 gsc_data->dst_buf[i] = NULL; 1148 } 1149 } 1150 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1151 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1152 return ret; 1153} 1154 1155 1156static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 1157 size_t gsc_idx) 1158{ 1159 exynos5_gsc_data_t &gsc_data = pdev->gsc[gsc_idx]; 1160 if (!gsc_data.gsc) 1161 return; 1162 1163 ALOGV("closing gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1164 1165 exynos_gsc_destroy(gsc_data.gsc); 1166 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) 1167 if (gsc_data.dst_buf[i]) 1168 pdev->alloc_device->free(pdev->alloc_device, gsc_data.dst_buf[i]); 1169 1170 memset(&gsc_data, 0, sizeof(gsc_data)); 1171} 1172 1173static void exynos5_config_handle(private_handle_t *handle, 1174 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1175 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1176 exynos5_hwc_composer_device_1_t *pdev) 1177{ 1178 uint32_t x, y; 1179 uint32_t w = WIDTH(displayFrame); 1180 uint32_t h = HEIGHT(displayFrame); 1181 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1182 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1183 1184 if (displayFrame.left < 0) { 1185 unsigned int crop = -displayFrame.left; 1186 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1187 crop); 1188 x = 0; 1189 w -= crop; 1190 offset += crop * bpp / 8; 1191 } else { 1192 x = displayFrame.left; 1193 } 1194 1195 if (displayFrame.right > pdev->xres) { 1196 unsigned int crop = displayFrame.right - pdev->xres; 1197 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1198 crop); 1199 w -= crop; 1200 } 1201 1202 if (displayFrame.top < 0) { 1203 unsigned int crop = -displayFrame.top; 1204 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1205 crop); 1206 y = 0; 1207 h -= crop; 1208 offset += handle->stride * crop * bpp / 8; 1209 } else { 1210 y = displayFrame.top; 1211 } 1212 1213 if (displayFrame.bottom > pdev->yres) { 1214 int crop = displayFrame.bottom - pdev->yres; 1215 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1216 crop); 1217 h -= crop; 1218 } 1219 1220 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1221 cfg.fd = handle->fd; 1222 cfg.x = x; 1223 cfg.y = y; 1224 cfg.w = w; 1225 cfg.h = h; 1226 cfg.format = exynos5_format_to_s3c_format(handle->format); 1227 cfg.offset = offset; 1228 cfg.stride = handle->stride * bpp / 8; 1229 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1230 cfg.fence_fd = fence_fd; 1231} 1232 1233static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1234 exynos5_hwc_composer_device_1_t *pdev) 1235{ 1236 if (layer->compositionType == HWC_BACKGROUND) { 1237 hwc_color_t color = layer->backgroundColor; 1238 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1239 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1240 cfg.x = 0; 1241 cfg.y = 0; 1242 cfg.w = pdev->xres; 1243 cfg.h = pdev->yres; 1244 return; 1245 } 1246 1247 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1248 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1249 layer->blending, layer->acquireFenceFd, cfg, pdev); 1250} 1251 1252static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1253 hwc_display_contents_1_t* contents) 1254{ 1255 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1256 struct s3c_fb_win_config_data win_data; 1257 struct s3c_fb_win_config *config = win_data.config; 1258 1259 memset(config, 0, sizeof(win_data.config)); 1260 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1261 config[i].fence_fd = -1; 1262 1263 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1264 int layer_idx = pdata->overlay_map[i]; 1265 if (layer_idx != -1) { 1266 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1267 private_handle_t *handle = 1268 private_handle_t::dynamicCast(layer.handle); 1269 1270 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1271 int gsc_idx = pdata->gsc_map[i].idx; 1272 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1273 1274 if (layer.acquireFenceFd != -1) { 1275 int err = sync_wait(layer.acquireFenceFd, 100); 1276 if (err != 0) 1277 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1278 i, strerror(errno)); 1279 close(layer.acquireFenceFd); 1280 } 1281 1282 // RGBX8888 surfaces are already in the right color order from the GPU, 1283 // RGB565 and YUV surfaces need the Gscaler to swap R & B 1284 int dst_format = HAL_PIXEL_FORMAT_BGRA_8888; 1285 if (exynos5_format_is_rgb(handle->format) && 1286 handle->format != HAL_PIXEL_FORMAT_RGB_565) 1287 dst_format = HAL_PIXEL_FORMAT_RGBX_8888; 1288 1289 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1290 gsc_idx, dst_format); 1291 if (err < 0) { 1292 ALOGE("failed to queue gscaler %u input for layer %u", 1293 gsc_idx, i); 1294 continue; 1295 } 1296 1297 err = exynos_gsc_stop_exclusive(gsc.gsc); 1298 if (err < 0) { 1299 ALOGE("failed to dequeue gscaler output for layer %u", i); 1300 continue; 1301 } 1302 1303 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1304 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1305 private_handle_t *dst_handle = 1306 private_handle_t::dynamicCast(dst_buf); 1307 hwc_rect_t sourceCrop = { 0, 0, 1308 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1309 exynos5_config_handle(dst_handle, sourceCrop, 1310 layer.displayFrame, layer.blending, -1, config[i], 1311 pdev); 1312 } else { 1313 exynos5_config_overlay(&layer, config[i], pdev); 1314 } 1315 } 1316 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1317 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1318 config[i].blending = S3C_FB_BLENDING_NONE; 1319 } 1320 1321 ALOGV("window %u configuration:", i); 1322 dump_config(config[i]); 1323 } 1324 1325 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1326 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1327 if (config[i].fence_fd != -1) 1328 close(config[i].fence_fd); 1329 if (ret < 0) { 1330 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1331 return ret; 1332 } 1333 1334 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1335 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1336 pdev->last_fb_window = pdata->fb_window; 1337 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1338 int layer_idx = pdata->overlay_map[i]; 1339 if (layer_idx != -1) { 1340 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1341 pdev->last_handles[i] = layer.handle; 1342 } 1343 } 1344 1345 return win_data.fence; 1346} 1347 1348static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1349 hwc_display_contents_1_t* contents) 1350{ 1351 if (!contents->dpy || !contents->sur) 1352 return 0; 1353 1354 hwc_layer_1_t *fb_layer = NULL; 1355 1356 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1357 for (size_t i = 0; i < contents->numHwLayers; i++) { 1358 if (contents->hwLayers[i].compositionType == 1359 HWC_FRAMEBUFFER_TARGET) { 1360 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1361 fb_layer = &contents->hwLayers[i]; 1362 break; 1363 } 1364 } 1365 1366 if (CC_UNLIKELY(!fb_layer)) { 1367 ALOGE("framebuffer target expected, but not provided"); 1368 return -EINVAL; 1369 } 1370 1371 ALOGV("framebuffer target buffer:"); 1372 dump_layer(fb_layer); 1373 } 1374 1375 int fence = exynos5_post_fimd(pdev, contents); 1376 if (fence < 0) 1377 return fence; 1378 1379 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1380 if (pdev->bufs.overlay_map[i] != -1) { 1381 hwc_layer_1_t &layer = 1382 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1383 int dup_fd = dup(fence); 1384 if (dup_fd < 0) 1385 ALOGW("release fence dup failed: %s", strerror(errno)); 1386 layer.releaseFenceFd = dup_fd; 1387 } 1388 } 1389 close(fence); 1390 1391 return 0; 1392} 1393 1394static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1395 hwc_display_contents_1_t* contents) 1396{ 1397 hwc_layer_1_t *fb_layer = NULL; 1398 hwc_layer_1_t *video_layer = NULL; 1399 1400 if (!pdev->hdmi_enabled) { 1401 for (size_t i = 0; i < contents->numHwLayers; i++) { 1402 hwc_layer_1_t &layer = contents->hwLayers[i]; 1403 if (layer.acquireFenceFd != -1) 1404 close(layer.acquireFenceFd); 1405 } 1406 return 0; 1407 } 1408 1409 for (size_t i = 0; i < contents->numHwLayers; i++) { 1410 hwc_layer_1_t &layer = contents->hwLayers[i]; 1411 1412 if (layer.flags & HWC_SKIP_LAYER) { 1413 ALOGV("HDMI skipping layer %d", i); 1414 continue; 1415 } 1416 1417 if (layer.compositionType == HWC_OVERLAY) { 1418 if (!layer.handle) 1419 continue; 1420 1421 ALOGV("HDMI video layer:"); 1422 dump_layer(&layer); 1423 1424 if (layer.acquireFenceFd != -1) { 1425 int err = sync_wait(layer.acquireFenceFd, 100); 1426 if (err != 0) 1427 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1428 i, strerror(errno)); 1429 close(layer.acquireFenceFd); 1430 layer.acquireFenceFd = -1; 1431 } 1432 1433 exynos5_gsc_data_t &gsc = pdev->gsc[HDMI_GSC_IDX]; 1434 exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1, 1435 HAL_PIXEL_FORMAT_RGBX_8888); 1436 1437 int err = exynos_gsc_stop_exclusive(gsc.gsc); 1438 if (err < 0) { 1439 ALOGE("failed to dequeue gscaler output for layer"); 1440 continue; 1441 } 1442 1443 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1444 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1445 private_handle_t *h = private_handle_t::dynamicCast(dst_buf); 1446 1447 hdmi_output(pdev, pdev->hdmi_layers[0], layer, h); 1448 video_layer = &layer; 1449 } 1450 1451 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1452 if (!layer.handle) 1453 continue; 1454 1455 ALOGV("HDMI FB layer:"); 1456 dump_layer(&layer); 1457 1458 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 1459 hdmi_output(pdev, pdev->hdmi_layers[1], layer, h); 1460 fb_layer = &layer; 1461 } 1462 } 1463 1464 if (!video_layer) { 1465 hdmi_disable_layer(pdev, pdev->hdmi_layers[0]); 1466 exynos5_cleanup_gsc_m2m(pdev, HDMI_GSC_IDX); 1467 } 1468 if (!fb_layer) 1469 hdmi_disable_layer(pdev, pdev->hdmi_layers[1]); 1470 1471 return 0; 1472} 1473 1474static int exynos5_set(struct hwc_composer_device_1 *dev, 1475 size_t numDisplays, hwc_display_contents_1_t** displays) 1476{ 1477 if (!numDisplays || !displays) 1478 return 0; 1479 1480 exynos5_hwc_composer_device_1_t *pdev = 1481 (exynos5_hwc_composer_device_1_t *)dev; 1482 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1483 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1484 1485 if (fimd_contents) { 1486 int err = exynos5_set_fimd(pdev, fimd_contents); 1487 if (err) 1488 return err; 1489 } 1490 1491 if (hdmi_contents) { 1492 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1493 if (err) 1494 return err; 1495 } 1496 1497 return 0; 1498} 1499 1500static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1501 hwc_procs_t const* procs) 1502{ 1503 struct exynos5_hwc_composer_device_1_t* pdev = 1504 (struct exynos5_hwc_composer_device_1_t*)dev; 1505 pdev->procs = procs; 1506} 1507 1508static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1509{ 1510 struct exynos5_hwc_composer_device_1_t *pdev = 1511 (struct exynos5_hwc_composer_device_1_t *)dev; 1512 1513 switch (what) { 1514 case HWC_BACKGROUND_LAYER_SUPPORTED: 1515 // we support the background layer 1516 value[0] = 1; 1517 break; 1518 case HWC_VSYNC_PERIOD: 1519 // vsync period in nanosecond 1520 value[0] = pdev->vsync_period; 1521 break; 1522 default: 1523 // unsupported query 1524 return -EINVAL; 1525 } 1526 return 0; 1527} 1528 1529static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1530 int event, int enabled) 1531{ 1532 struct exynos5_hwc_composer_device_1_t *pdev = 1533 (struct exynos5_hwc_composer_device_1_t *)dev; 1534 1535 switch (event) { 1536 case HWC_EVENT_VSYNC: 1537 __u32 val = !!enabled; 1538 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1539 if (err < 0) { 1540 ALOGE("vsync ioctl failed"); 1541 return -errno; 1542 } 1543 1544 return 0; 1545 } 1546 1547 return -EINVAL; 1548} 1549 1550static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1551 const char *buff, int len) 1552{ 1553 const char *s = buff; 1554 s += strlen(s) + 1; 1555 1556 while (*s) { 1557 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1558 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1559 1560 s += strlen(s) + 1; 1561 if (s - buff >= len) 1562 break; 1563 } 1564 1565 if (pdev->hdmi_hpd) { 1566 if (hdmi_get_config(pdev)) { 1567 ALOGE("Error reading HDMI configuration"); 1568 pdev->hdmi_hpd = false; 1569 return; 1570 } 1571 } 1572 1573 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1574 if (pdev->hdmi_hpd) 1575 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1576 1577 /* hwc_dev->procs is set right after the device is opened, but there is 1578 * still a race condition where a hotplug event might occur after the open 1579 * but before the procs are registered. */ 1580 if (pdev->procs) 1581 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd); 1582} 1583 1584static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1585{ 1586 if (!pdev->procs) 1587 return; 1588 1589 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1590 if (err < 0) { 1591 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1592 return; 1593 } 1594 1595 char buf[4096]; 1596 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1597 if (err < 0) { 1598 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1599 return; 1600 } 1601 buf[sizeof(buf) - 1] = '\0'; 1602 1603 errno = 0; 1604 uint64_t timestamp = strtoull(buf, NULL, 0); 1605 if (!errno) 1606 pdev->procs->vsync(pdev->procs, 0, timestamp); 1607} 1608 1609static void *hwc_vsync_thread(void *data) 1610{ 1611 struct exynos5_hwc_composer_device_1_t *pdev = 1612 (struct exynos5_hwc_composer_device_1_t *)data; 1613 char uevent_desc[4096]; 1614 memset(uevent_desc, 0, sizeof(uevent_desc)); 1615 1616 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1617 1618 uevent_init(); 1619 1620 char temp[4096]; 1621 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1622 if (err < 0) { 1623 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1624 return NULL; 1625 } 1626 1627 struct pollfd fds[2]; 1628 fds[0].fd = pdev->vsync_fd; 1629 fds[0].events = POLLPRI; 1630 fds[1].fd = uevent_get_fd(); 1631 fds[1].events = POLLIN; 1632 1633 while (true) { 1634 int err = poll(fds, 2, -1); 1635 1636 if (err > 0) { 1637 if (fds[0].revents & POLLPRI) { 1638 handle_vsync_event(pdev); 1639 } 1640 else if (fds[1].revents & POLLIN) { 1641 int len = uevent_next_event(uevent_desc, 1642 sizeof(uevent_desc) - 2); 1643 1644 bool hdmi = !strcmp(uevent_desc, 1645 "change@/devices/virtual/switch/hdmi"); 1646 if (hdmi) 1647 handle_hdmi_uevent(pdev, uevent_desc, len); 1648 } 1649 } 1650 else if (err == -1) { 1651 if (errno == EINTR) 1652 break; 1653 ALOGE("error in vsync thread: %s", strerror(errno)); 1654 } 1655 } 1656 1657 return NULL; 1658} 1659 1660static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1661{ 1662 struct exynos5_hwc_composer_device_1_t *pdev = 1663 (struct exynos5_hwc_composer_device_1_t *)dev; 1664 1665 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1666 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1667 if (err < 0) { 1668 if (errno == EBUSY) 1669 ALOGI("%sblank ioctl failed (display already %sblanked)", 1670 blank ? "" : "un", blank ? "" : "un"); 1671 else 1672 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un", 1673 strerror(errno)); 1674 return -errno; 1675 } 1676 1677 if (pdev->hdmi_hpd) { 1678 if (blank && !pdev->hdmi_blanked) 1679 hdmi_disable(pdev); 1680 pdev->hdmi_blanked = !!blank; 1681 } 1682 1683 return 0; 1684} 1685 1686static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1687{ 1688 if (buff_len <= 0) 1689 return; 1690 1691 struct exynos5_hwc_composer_device_1_t *pdev = 1692 (struct exynos5_hwc_composer_device_1_t *)dev; 1693 1694 android::String8 result; 1695 1696 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1697 if (pdev->hdmi_enabled) 1698 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1699 result.append( 1700 " type | handle | color | blend | format | position | size | gsc \n" 1701 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1702 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1703 1704 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1705 struct s3c_fb_win_config &config = pdev->last_config[i]; 1706 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1707 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1708 "DISABLED", "-", "-", "-", "-", "-", "-"); 1709 } 1710 else { 1711 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1712 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1713 "-", config.color, "-", "-"); 1714 else 1715 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1716 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1717 intptr_t(pdev->last_handles[i]), 1718 "-", config.blending, config.format); 1719 1720 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1721 config.w, config.h); 1722 } 1723 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1724 result.appendFormat(" | %3s", "-"); 1725 else 1726 result.appendFormat(" | %3d", 1727 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1728 result.append("\n"); 1729 } 1730 1731 strlcpy(buff, result.string(), buff_len); 1732} 1733 1734static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1735 int disp, uint32_t *configs, size_t *numConfigs) 1736{ 1737 struct exynos5_hwc_composer_device_1_t *pdev = 1738 (struct exynos5_hwc_composer_device_1_t *)dev; 1739 1740 if (*numConfigs == 0) 1741 return 0; 1742 1743 if (disp == HWC_DISPLAY_PRIMARY) { 1744 configs[0] = 0; 1745 *numConfigs = 1; 1746 return 0; 1747 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1748 if (!pdev->hdmi_hpd) { 1749 return -EINVAL; 1750 } 1751 1752 int err = hdmi_get_config(pdev); 1753 if (err) { 1754 return -EINVAL; 1755 } 1756 1757 configs[0] = 0; 1758 *numConfigs = 1; 1759 return 0; 1760 } 1761 1762 return -EINVAL; 1763} 1764 1765static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1766 const uint32_t attribute) 1767{ 1768 switch(attribute) { 1769 case HWC_DISPLAY_VSYNC_PERIOD: 1770 return pdev->vsync_period; 1771 1772 case HWC_DISPLAY_WIDTH: 1773 return pdev->xres; 1774 1775 case HWC_DISPLAY_HEIGHT: 1776 return pdev->yres; 1777 1778 case HWC_DISPLAY_DPI_X: 1779 return pdev->xdpi; 1780 1781 case HWC_DISPLAY_DPI_Y: 1782 return pdev->ydpi; 1783 1784 default: 1785 ALOGE("unknown display attribute %u", attribute); 1786 return -EINVAL; 1787 } 1788} 1789 1790static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1791 const uint32_t attribute) 1792{ 1793 switch(attribute) { 1794 case HWC_DISPLAY_VSYNC_PERIOD: 1795 return pdev->vsync_period; 1796 1797 case HWC_DISPLAY_WIDTH: 1798 return pdev->hdmi_w; 1799 1800 case HWC_DISPLAY_HEIGHT: 1801 return pdev->hdmi_h; 1802 1803 case HWC_DISPLAY_DPI_X: 1804 case HWC_DISPLAY_DPI_Y: 1805 return 0; // unknown 1806 1807 default: 1808 ALOGE("unknown display attribute %u", attribute); 1809 return -EINVAL; 1810 } 1811} 1812 1813static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1814 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1815{ 1816 struct exynos5_hwc_composer_device_1_t *pdev = 1817 (struct exynos5_hwc_composer_device_1_t *)dev; 1818 1819 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1820 if (disp == HWC_DISPLAY_PRIMARY) 1821 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1822 else if (disp == HWC_DISPLAY_EXTERNAL) 1823 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1824 else { 1825 ALOGE("unknown display type %u", disp); 1826 return -EINVAL; 1827 } 1828 } 1829 1830 return 0; 1831} 1832 1833static int exynos5_close(hw_device_t* device); 1834 1835static int exynos5_open(const struct hw_module_t *module, const char *name, 1836 struct hw_device_t **device) 1837{ 1838 int ret; 1839 int refreshRate; 1840 int sw_fd; 1841 1842 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1843 return -EINVAL; 1844 } 1845 1846 struct exynos5_hwc_composer_device_1_t *dev; 1847 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1848 memset(dev, 0, sizeof(*dev)); 1849 1850 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1851 (const struct hw_module_t **)&dev->gralloc_module)) { 1852 ALOGE("failed to get gralloc hw module"); 1853 ret = -EINVAL; 1854 goto err_get_module; 1855 } 1856 1857 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1858 &dev->alloc_device)) { 1859 ALOGE("failed to open gralloc"); 1860 ret = -EINVAL; 1861 goto err_get_module; 1862 } 1863 1864 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1865 if (dev->fd < 0) { 1866 ALOGE("failed to open framebuffer"); 1867 ret = dev->fd; 1868 goto err_open_fb; 1869 } 1870 1871 struct fb_var_screeninfo info; 1872 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1873 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1874 ret = -errno; 1875 goto err_ioctl; 1876 } 1877 1878 refreshRate = 1000000000000LLU / 1879 ( 1880 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1881 * ( info.left_margin + info.right_margin + info.xres ) 1882 * info.pixclock 1883 ); 1884 1885 if (refreshRate == 0) { 1886 ALOGW("invalid refresh rate, assuming 60 Hz"); 1887 refreshRate = 60; 1888 } 1889 1890 dev->xres = 2560; 1891 dev->yres = 1600; 1892 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1893 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1894 dev->vsync_period = 1000000000 / refreshRate; 1895 1896 ALOGV("using\n" 1897 "xres = %d px\n" 1898 "yres = %d px\n" 1899 "width = %d mm (%f dpi)\n" 1900 "height = %d mm (%f dpi)\n" 1901 "refresh rate = %d Hz\n", 1902 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1903 info.height, dev->ydpi / 1000.0, refreshRate); 1904 1905 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1906 if (dev->hdmi_mixer0 < 0) { 1907 ALOGE("failed to open hdmi mixer0 subdev"); 1908 ret = dev->hdmi_mixer0; 1909 goto err_ioctl; 1910 } 1911 1912 dev->hdmi_layers[0].id = 0; 1913 dev->hdmi_layers[0].fd = open("/dev/video16", O_RDWR); 1914 if (dev->hdmi_layers[0].fd < 0) { 1915 ALOGE("failed to open hdmi layer0 device"); 1916 ret = dev->hdmi_layers[0].fd; 1917 goto err_mixer0; 1918 } 1919 1920 dev->hdmi_layers[1].id = 1; 1921 dev->hdmi_layers[1].fd = open("/dev/video17", O_RDWR); 1922 if (dev->hdmi_layers[1].fd < 0) { 1923 ALOGE("failed to open hdmi layer1 device"); 1924 ret = dev->hdmi_layers[1].fd; 1925 goto err_hdmi0; 1926 } 1927 1928 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1929 if (dev->vsync_fd < 0) { 1930 ALOGE("failed to open vsync attribute"); 1931 ret = dev->vsync_fd; 1932 goto err_hdmi1; 1933 } 1934 1935 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1936 if (sw_fd) { 1937 char val; 1938 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1939 dev->hdmi_hpd = true; 1940 if (hdmi_get_config(dev)) { 1941 ALOGE("Error reading HDMI configuration"); 1942 dev->hdmi_hpd = false; 1943 } 1944 } 1945 } 1946 1947 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1948 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1949 dev->base.common.module = const_cast<hw_module_t *>(module); 1950 dev->base.common.close = exynos5_close; 1951 1952 dev->base.prepare = exynos5_prepare; 1953 dev->base.set = exynos5_set; 1954 dev->base.eventControl = exynos5_eventControl; 1955 dev->base.blank = exynos5_blank; 1956 dev->base.query = exynos5_query; 1957 dev->base.registerProcs = exynos5_registerProcs; 1958 dev->base.dump = exynos5_dump; 1959 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1960 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1961 1962 *device = &dev->base.common; 1963 1964 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1965 if (ret) { 1966 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1967 ret = -ret; 1968 goto err_vsync; 1969 } 1970 1971 char value[PROPERTY_VALUE_MAX]; 1972 property_get("debug.hwc.force_gpu", value, "0"); 1973 dev->force_gpu = atoi(value); 1974 1975 return 0; 1976 1977err_vsync: 1978 close(dev->vsync_fd); 1979err_mixer0: 1980 close(dev->hdmi_mixer0); 1981err_hdmi1: 1982 close(dev->hdmi_layers[0].fd); 1983err_hdmi0: 1984 close(dev->hdmi_layers[1].fd); 1985err_ioctl: 1986 close(dev->fd); 1987err_open_fb: 1988 gralloc_close(dev->alloc_device); 1989err_get_module: 1990 free(dev); 1991 return ret; 1992} 1993 1994static int exynos5_close(hw_device_t *device) 1995{ 1996 struct exynos5_hwc_composer_device_1_t *dev = 1997 (struct exynos5_hwc_composer_device_1_t *)device; 1998 pthread_kill(dev->vsync_thread, SIGTERM); 1999 pthread_join(dev->vsync_thread, NULL); 2000 for (size_t i = 0; i < NUM_GSC_UNITS; i++) 2001 exynos5_cleanup_gsc_m2m(dev, i); 2002 gralloc_close(dev->alloc_device); 2003 close(dev->vsync_fd); 2004 close(dev->hdmi_mixer0); 2005 close(dev->hdmi_layers[0].fd); 2006 close(dev->hdmi_layers[1].fd); 2007 close(dev->fd); 2008 return 0; 2009} 2010 2011static struct hw_module_methods_t exynos5_hwc_module_methods = { 2012 open: exynos5_open, 2013}; 2014 2015hwc_module_t HAL_MODULE_INFO_SYM = { 2016 common: { 2017 tag: HARDWARE_MODULE_TAG, 2018 module_api_version: HWC_MODULE_API_VERSION_0_1, 2019 hal_api_version: HARDWARE_HAL_API_VERSION, 2020 id: HWC_HARDWARE_MODULE_ID, 2021 name: "Samsung exynos5 hwcomposer module", 2022 author: "Google", 2023 methods: &exynos5_hwc_module_methods, 2024 } 2025}; 2026