| 34fa79ece5b3a1940d412cd94dbdcc4225aae72f |
15-Sep-2014 |
Brian Carlstrom <bdc@google.com> |
Avoid printing absolute addresses in oatdump
- Added printing of OatClass offsets.
- Added printing of OatMethod offsets.
- Added bounds checks for code size size, code size, mapping table, gc map, vmap table.
- Added sanity check of 100k for code size.
- Added partial disassembly of questionable code.
- Added --no-disassemble to disable disassembly.
- Added --no-dump:vmap to disable vmap dumping.
- Reordered OatMethod info to be in file order.
Bug: 15567083
Change-Id: Id86a21e06d4a28f29f16fd018cba7e55c57f849a
isassembler.cc
isassembler.h
isassembler_arm.cc
isassembler_arm.h
isassembler_arm64.cc
isassembler_arm64.h
isassembler_mips.cc
isassembler_mips.h
isassembler_x86.cc
isassembler_x86.h
|
| ec95f72490de0a7f86c35de3d00b50bb80d036a1 |
22-Jul-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: Correct disassembling of 64bit immediates on x86_64
The patch fixes an issue with disassembling 'movsxd' and 'movabsq'
instructions altered with 64bit immediates: not only a REX.W prefix
may be prepended to these instructions.
Change-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| 3c7bb98698f77af10372cf31824d3bb115d9bf0f |
23-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement array get and array put in optimizing.
Also fix a couple of assembler/disassembler issues.
Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
isassembler.h
isassembler_arm.cc
|
| 79bb184ec0a661bf1276eef555dd5e20828bc528 |
01-Jul-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: Correct disassembling of regs from opcodes
Registers, which are part of opcode might have 1-byte size
or 2-byte size depending on the instruction and 66h prefix.
This patch makes the decoding of such instruction correct.
Examples:
- '664155' should be decoded as 'push r13w'
(66h + REX.B)
- '41B320' should be decoded as 'mov r11l, 0x20'
(byte-operand + REX.B)
Change-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| 2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565 |
09-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86 Backend support for vectorized float and byte 16x16 operations"
|
| 60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43 |
09-Jul-2014 |
Udayan Banerji <udayan.banerji@intel.com> |
X86 Backend support for vectorized float and byte 16x16 operations
Add support for reserving vector registers for the duration of vector loop.
Add support for 16x16 multiplication, shifts, and add reduce.
Changed the vectorization implementation to be able to use the dataflow
elements for SSA recreation and fixed a few implementation details.
Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Olivier Come <olivier.come@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
isassembler_x86.cc
|
| 94f3eb0c757d0a6a145e24ef95ef7d35c091bb01 |
24-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Clean-up after cmp-long fix
The patch adresses the coments from review done by Ian Rogers.
Clean-up of assembler.
Change-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
isassembler_x86.cc
|
| ae2efea4582df773f80be274bdc754f732b07df3 |
07-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"
|
| e443a8063518fb1c5229afa3081b9fd1f6d33b16 |
30-Jun-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: FF-opcodes are target-specific
Some of the FF-opcodes' (i.e., push, call, jmp) register names
depend on the the target (32-bit vs 64-bit). This patch makes
such opcodes target-specific.
Change-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| 5192cbb12856b12620dc346758605baaa1469ced |
01-Jul-2014 |
Yixin Shou <yixin.shou@intel.com> |
Load 64 bit constant into GPR by single instruction for 64bit mode
This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.
Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
isassembler_x86.cc
|
| d48b8a2bc111d30ebafdd2c661e9c0789f5c66a7 |
24-Jun-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: FPU instructions support in disassembler
This patch extends the disassembler with new FPU instructions:
- fstsw
- fucompp
- fprem
Change-Id: I9458510bc17f2b3b286edec102552f64be05147e
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| fb0fecffb31398adb6f74f58482f2c4aac95b9bf |
20-Jun-2014 |
Olivier Come <olivier.come@intel.com> |
ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation
The patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation
for X86.
Change-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6
Signed-off-by: Olivier Come <olivier.come@intel.com>
isassembler_x86.cc
|
| afd9acc30bdd11cdd12d8209eb994cb371c65e33 |
17-Jun-2014 |
Ian Rogers <irogers@google.com> |
Multilib ART host.
Build ART for the host as a multilib project with dalvikvm32 and dalvikvm64
running as 32 or 64-bit repsectfully. Note, currently multilib host builds
are not the default, you make the so by setting BUILD_HOST_64bit=1.
Extend tests to execute in both 32 and 64-bit modes. By default both 32 and
64-bit tests are run, add 32 or 64 to the end of a test name to run it in
purely that flavor.
Given the extra spam, modify oat tests to only generate console output when
the test fails.
Change the test harness so that common commands are run when a test should be
skipped, when it passes or when it fails. Use these commands to generate a
summary of passing, skipped and failing tests. Tests will be skipped if they
are known to be broken or if a test has already failed. Setting the variable
TEST_ART_KEEP_GOING=true will force working tests not to be skipped.
In this change all tests running on the optimizing compiler are marked broken
due to breakages running them in a multilib environment.
Break apart Android.common.mk into its constituent parts, along with other
pieces of reorganization.
Stylistic nit, we refer to make rule targets as targets thereby overloading
the term target. While consistent with make's terminology, its confusing with
the Android notion of target. I've switched to just calling targets rules to
avoid confusion in host tests.
Change-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9
ndroid.mk
|
| 20dfc797dc631bf8d655dcf123f46f13332d3074 |
17-Jun-2014 |
Dave Allison <dallison@google.com> |
Add some more instruction support to optimizing compiler.
This adds a few more DEX instructions to the optimizing compiler's
builder (constants, moves, if_xx, etc).
Also:
* Changes the codegen for IF_XX instructions to use a condition
rather than comparing a value against 0.
* Fixes some instructions in the ARM disassembler.
* Fixes PushList and PopList in the thumb2 assembler.
* Switches the assembler for the optimizing compiler to thumb2
rather than ARM.
Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
isassembler_arm.cc
|
| a33720c7370d1c9e0d6569d7126bb06f2083c614 |
19-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86 Dis: Add missing mov byte; Add size suffixes
Yet another instruction not disassembled properly.
Add 'b', 'w', 'q' to opcodes to diffferentiate between various versions
and make it more understandable.
Change-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
|
| c5f17732d8144491c642776b6b48c85dfadf4b52 |
06-Jun-2014 |
Ian Rogers <irogers@google.com> |
Remove deprecated WITH_HOST_DALVIK.
Bug: 13751317
Fix the Mac build:
- disable x86 selector removal that causes OS/X 10.9 kernel panics,
- madvise don't need does zero memory on the Mac, factor into MemMap
routine,
- switch to the elf.h in elfutils to avoid Linux kernel dependencies,
- we can't rely on exclusive_owner_ being available from other pthread
libraries so maintain our own when futexes aren't available (we
can't rely on the OS/X 10.8 hack any more),
- fix symbol naming in assembly code,
- work around C library differences,
- disable backtrace in DumpNativeStack to avoid a broken libbacktrace
dependency,
- disable main thread signal handling logic,
- align the stack in stub_test,
- use $(HOST_SHLIB_SUFFIX) rather than .so in host make file variables.
Not all host tests are passing on the Mac with this change. dex2oat
works as does running HelloWorld.
Change-Id: I5a232aedfb2028524d49daa6397a8e60f3ee40d3
ndroid.mk
|
| 33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e |
06-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Add Move with Sign Extend Double to disassembler
I noticed another missing instruction.
Change-Id: I71170496b014ac2609116eff2aeb13a13e71e263
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
|
| 88649c790cb437c130dcb6e428cddeb1ae62601c |
05-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix X86 disassambler printing of XMM, MM registers
Printing of uint8_t is done as a char, rather than an integer.
Change-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
|
| f3639b2653fe4e55ce6f753b991eeb015116541d |
04-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: x86_64 disassembler improvements"
|
| 5ca4eaace8ba513f97309bbdc2e156de4b1d648a |
29-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Make LOCAL_CLANG architecture dependent for the target
Be selective for which target we compile with Clang. Currently we
only want to compile with Clang for ARM64, which means we need to
be careful about ARM, which is the second architecture for that.
Bug: 15014252
(cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4)
Change-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04
ndroid.mk
|
| 122113a8a233f824c014a8fe9d90626218c4dcca |
30-May-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: x86_64 disassembler improvements
This patch
(a) enables full support of 64bit extended regs r8-r15,
including 8bit r8l-r15l, 16bit r8w-r15w and also
32bit r8d-r15d
(b) fixes an issue with decoding reg from ModRM byte
(REX.B should be used)
(c) fixes an issue with decoding regs from SIB byte
(regs that contain addr are target-specific)
Change-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| 67d18be2a5bddbd8ee9ef144b34ccaeba08a1db2 |
30-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Support disassembly of 16-bit immediates
Change-Id: I66f5ce93077241204311e52c547599f5287bae04
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
|
| fe94578b63380f464c3abd5c156b7b31d068db6c |
22-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Implement all vector instructions for X86
Add X86 code generation for the vector operations. Added support for
X86 disassembler for the new instructions.
Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
|
| 2a0e954ecf7c60e6ec62d64b9382cc4ee447e224 |
21-May-2014 |
Dan Albert <danalbert@google.com> |
Move art host to libc++
Change-Id: Ia51a4fdfdbae7377130a43c401c2d8d241671d1e
ndroid.mk
|
| 700a402244a1a423da4f3ba8032459f4b65fa18f |
20-May-2014 |
Ian Rogers <irogers@google.com> |
Now we have a proper C++ library, use std::unique_ptr.
Also remove the Android.libcxx.mk and other bits of stlport compatibility
mechanics.
Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
ndroid.mk
|
| ff093b31d75658c3404f9b51ee45760f346f06d9 |
01-May-2014 |
Ian Rogers <irogers@google.com> |
Fix a few 64-bit compilation of 32-bit code issues.
Bug: 13423943
Change-Id: I939389413af0a68c0d95b23cd598b7c42afa4383
isassembler_arm.cc
|
| e8861b30ac8b2b1ca49386f9c9218f1d6fedc511 |
18-Apr-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: Enables x86_64 disassembly
This patch
(a) cuts a REX prefix from the instruction and
(b) adds missed 32bit disp to instructions with ModR/M and SIB bytes.
Change-Id: I2674678224ca27746b33d4006ed38d497972309f
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| 96a4f29350bf279d48bff70e21e3264cce216683 |
24-Apr-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Fixes an issue with REX prefix for instructions with no ModRM byte"
|
| fba52f1b4bf753790c1d98265c4b0fabb54c7536 |
15-Apr-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: Fixes an issue with REX prefix for instructions with no ModRM byte
There are instructions (such as push, pop, mov) in the x86 ISA
that encode first operands in their opcodes (opcode + reg).
In order to enable an extended 64bit registers (R9-R15) a special
prefix REX.B should be emitted before such instructions.
This patch fixes the issue when REX.R prefix was emitted before
instructions with no MorRM byte. So, the REX-prefix was simply
ignored by CPU for those instructions whose operands are encoded
in their opcodes.
This patch makes the jni_compiler_test passed with JNI compiler
enabled for x86_64 target.
Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
isassembler_x86.cc
|
| bd5ea6a2f7c61c4cd7b66fead1bedd96e938369d |
17-Apr-2014 |
Ian Rogers <irogers@google.com> |
Preparation for transition to libc++.
Move the dependency on libc++ to its own makefile so that we can switch in a
single place between libc++ and stlport.
Change-Id: Ie61e7d054dcd049e36d5e7298c27d8a4abe6edf7
ndroid.mk
|
| d6ed642458c8820e1beca72f3d7b5f0be4a4b64b |
10-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Use trampolines for calls to helpers"""
This reverts commit f9487c039efb4112616d438593a2ab02792e0304.
Change-Id: Id48a4aae4ecce73db468587967968a3f7618b700
isassembler_arm.cc
|
| f9487c039efb4112616d438593a2ab02792e0304 |
09-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Use trampolines for calls to helpers""
This reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff.
Change-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61
Conflicts:
compiler/dex/quick/mir_to_lir.h
isassembler_arm.cc
|
| 081f73e888b3c246cf7635db37b7f1105cf1a2ff |
07-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Use trampolines for calls to helpers"
This reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6.
Change-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8
isassembler_arm.cc
|
| 754ddad084ccb610d0cf486f6131bdc69bae5bc6 |
19-Feb-2014 |
Dave Allison <dallison@google.com> |
Use trampolines for calls to helpers
This is an ARM specific optimization to the compiler
that uses trampoline islands to make calls to runtime
helper functions. The intention is to reduce the size
of the generated code (by 2 bytes per call) without
affecting performance.
By default this is on when generating an OAT file. It is
off when compiling to memory.
To switch this off in dex2oat, use the command line option:
--no-helper-trampolines
Enhances disassembler to print the trampoline entry on the
BL instruction like this:
0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend
Bug: 12607709
Change-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe
isassembler_arm.cc
|
| c777e0de83cdffdb2e240d439c5595a4836553e8 |
03-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Disassemble Thumb2 shifts and more VFP instructions.
Disassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP
instructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV.
Clean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These
could have been erroneously used for other insns (VSQRT for
VMOV was encountered) and one VSQRT branch was unreachable.
Remove duplicate VMOV opcodes from compiler.
Change-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d
isassembler_arm.cc
|
| dd7624d2b9e599d57762d12031b10b89defc9807 |
15-Mar-2014 |
Ian Rogers <irogers@google.com> |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
isassembler_arm.cc
isassembler_mips.cc
isassembler_x86.cc
|
| 99ad7230ccaace93bf323dea9790f35fe991a4a2 |
26-Feb-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Relaxed memory barriers for x86
X86 provides stronger memory guarantees and thus the memory barriers can be
optimized. This patch ensures that all memory barriers for x86 are treated
as scheduling barriers. And in cases where a barrier is needed (StoreLoad case),
an mfence is used.
Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
isassembler_x86.cc
|
| 7d180cb41d3104af7c85a5b808bb9f57c264c2a6 |
25-Mar-2014 |
Dmitriy Ivanov <dimitry@google.com> |
Fix imm5 and shift_type detection
Bug: 13628315
Change-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9
isassembler_arm.cc
|
| 38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be |
14-Mar-2014 |
Ian Rogers <irogers@google.com> |
x86-64 disassembler support.
Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
isassembler.cc
isassembler_arm.cc
isassembler_arm.h
isassembler_arm64.h
isassembler_mips.cc
isassembler_mips.h
isassembler_x86.cc
isassembler_x86.h
|
| c2687ef3ef95c9888af885ec3fa1516b218906ff |
13-Mar-2014 |
Brian Carlstrom <bdc@google.com> |
Avoid bus error from reading unaligned 64-bit literal
Change-Id: I5932f130e6a8d31e09ef615e8544ff0e1073ede9
isassembler_arm.cc
|
| 2b9aa967b22f6114f25a8f7c72c58dc476dc35a2 |
10-Mar-2014 |
Ian Rogers <irogers@google.com> |
Merge "AArch64: Add ARM64 Disassembler"
|
| e6622be6c353c7178f34adf814c58370a51c5ed7 |
27-Feb-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add ARM64 Disassembler
This patch adds disassembler support for ARM64 based on VIXL.
Change-Id: Ic7f5e197350809632145d932dbae8f6c16aebd13
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
ndroid.mk
isassembler.cc
isassembler_arm64.cc
isassembler_arm64.h
|
| e19649a91702234f9aa9941d76da447a1e0dcc2a |
27-Feb-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.
Remove kThumb2VcvtID in the assembler which was duplicated.
Add vcvt, vmla, vmls in the disassembler.
Change-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26
isassembler_arm.cc
|
| b48b9eb6d181a1f52e2e605cf26a21505f1d46ed |
01-Mar-2014 |
Ian Rogers <irogers@google.com> |
Fix clang to compile and run host tests.
Don't use the computed goto interpreter with clang 3.4 as it causes compilation
to hang.
Avoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it
sets clang incompatible cflags.
Most fixes are self-evident, for the quick dex file method inliner the enums
were being used with ostreams, so fix the enums and operator out python script
to allow this.
Note this change effects portable but this is untestable as portable was broken
by ELF file and mc linker changes.
Change-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903
ndroid.mk
|
| 4028a6c83a339036864999fdfd2855b012a9f1a7 |
20-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Inline x86 String.indexOf
Take advantage of the presence of a constant search char or start index
to tune the generated code.
Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
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| dc781a13ddb4dabf646bb45d0c53b65cab948e5b |
05-Feb-2014 |
Colin Cross <ccross@android.com> |
art: convert makefiles to support multilib build
Convert makefiles to allow for building two architectures at the
same time. More changes may be necessary to get the tests to
build.
Change-Id: I02ba11706b7e5b5592d76e43c167bcbf0e665b93
ndroid.mk
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| 614c2b4e219631e8c190fd9fd5d4d9cd343434e1 |
29-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Support to generate inline long to FP bytecodes for x86
long-to-float and long-to-double are now generated inline instead of calling
a helper routine. The conversion is done by using x87.
Change-Id: I196e526afec1be212898baceca8527549c3655b6
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
isassembler_x86.cc
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| ef7d42fca18c16fbaf103822ad16f23246e2905d |
06-Jan-2014 |
Ian Rogers <irogers@google.com> |
Object model changes to support 64bit.
Modify mirror objects so that references between them use an ObjectReference
value type rather than an Object* so that functionality to compress larger
references can be captured in the ObjectRefererence implementation.
ObjectReferences are 32bit and all other aspects of object layout remain as
they are currently.
Expand fields in objects holding pointers so they can hold 64bit pointers. Its
expected the size of these will come down by improving where we hold compiler
meta-data.
Stub out x86_64 architecture specific runtime implementation.
Modify OutputStream so that reads and writes are of unsigned quantities.
Make the use of portable or quick code more explicit.
Templatize AtomicInteger to support more than just int32_t as a type.
Add missing, and fix issues relating to, missing annotalysis information on the
mutator lock.
Refactor and share implementations for array copy between System and uses
elsewhere in the runtime.
Fix numerous 64bit build issues.
Change-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822
isassembler_arm.cc
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| 2c498d1f28e62e81fbdb477ff93ca7454e7493d7 |
30-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Specializing x86 range argument copying
The ARM implementation of range argument copying was specialized in some cases.
For all other architectures, it would fall back to generating memcpy. This patch
updates the x86 implementation so it does not call memcpy and instead generates
loads and stores, favoring movement of 128-bit chunks.
Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
isassembler_x86.cc
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| 7ea5dafc81b2bba7cabad26130bb75dc8f709803 |
28-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Improve x86 long multiply and shifts"
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| d3266bcc340d653e178e3ab9d74512c8db122eee |
24-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Reduce x86 sequence for GP pair to XMM
Added support for punpckldq which is useful for interleaving
32-bit values from two xmm registers.
This new instruction is now used for transfers from GP pairs
to XMM in order to reduce path length.
Change-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
isassembler_x86.cc
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| 4708dcd68eebf1173aef1097dad8ab13466059aa |
22-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve x86 long multiply and shifts
Generate inline code for long shifts by constants and do long
multiplication inline. Convert multiplication by a constant to a
shift when we can. Fix some x86 assembler problems and add the new
instructions that were needed (64 bit shifts).
Change-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
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| 2bf31e67694da24a19fc1f328285cebb1a4b9964 |
23-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve x86 long divide
Implement inline division for literal and variable divisors. Use the
general case for dividing by a literal by using a double length multiply
by the appropriate constant with fixups. This is the Hacker's Delight
algorithm.
Change-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
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| 0adc680c388913a63666797e907f87c4c6b0b4ea |
08-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Add conditional move support to x86 and allow GenMinMax to use it"
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| ef6a776af2b4b8607d5f91add0ed0e8497100e31 |
20-Dec-2013 |
Ian Rogers <irogers@google.com> |
Inline codegen for long-to-double on ARM.
Change-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584
isassembler_arm.cc
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| bd288c2c1206bc99fafebfb9120a83f13cf9723b |
21-Dec-2013 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Add conditional move support to x86 and allow GenMinMax to use it
X86 supports conditional moves which is useful for reducing branchiness.
This patch adds support to the x86 backend to generate conditional reg
to reg operations. Both encoder and decoder support was added for cmov.
The x86 version of GenMinMax used for generating inlined version Math.min/max
has been updated to make use of the conditional move support.
Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
isassembler_x86.cc
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| b122a4bbed34ab22b4c1541ee25e5cf22f12a926 |
20-Nov-2013 |
Ian Rogers <irogers@google.com> |
Tidy up memory barriers.
Change-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b
isassembler_arm.cc
isassembler_arm.h
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| d19b55a05b52b7f7da9f894eba63ed03e2a62283 |
12-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Disassemble more x86 instructions
By using oatdump on the core.oat, I found a couple more instructions
that didn't disassemble properly. These included another form of imul
and some FP instructions used by the JNI code.
Now the only unknown opcodes I could find seem to be literal data at
the end of the method.
Change-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
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| f723f0cdc693f81581c0781fa472b1c85a8b42d6 |
12-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Add missing x86 imul opcode to disassembler
When playing with ART, I noticed that an integer multiply didn't
disassemble properly. This patch adds the instruction.
Change-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
isassembler_x86.cc
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| 70b797d998f2a28e39f7d6ffc8a07c9cbc47da14 |
03-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Unsafe.compareAndSwapLong() intrinsic for x86.
Change-Id: Idbc5371a62dfdd84485a657d4548990519200205
isassembler_x86.cc
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| 3e5af82ae1a2cd69b7b045ac008ac3b394d17f41 |
21-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Intrinsic Unsafe.CompareAndSwapLong() for ARM.
(cherry picked from cb53fcd79b1a5ce608208ec454b5c19f64aaba37)
Change-Id: Iadd3cc8b4ed390670463b80f8efd579ce6ece226
isassembler_arm.cc
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| 2247984899247b1402408d39731ff64048f0e274 |
19-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Clean up kOpCmp on ARM.
kThumb2CmnRI8M is now used.
Change-Id: I300299258ed99d86c300dee45c904c360dd44638
isassembler_arm.cc
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| ad435ebd9d011eef66ef77e96b065024220c10ad |
15-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix Thumb2 ldrd/strd disassembly.
Change-Id: Ie75aeab5b970640e90e567621ac45ce1a3a7c377
isassembler_arm.cc
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| dd577a3c9849105429fe7afb3559773d59aaafb6 |
07-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Disassemble Thumb2 vstm/vldm/vstr/vldr/vpush/vpop/vmov/vmrs.
Not all versions of vmov are disassembled.
Change-Id: I876199f7536d2a9429106deab821016fe8972469
isassembler_arm.cc
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| 7020278bce98a0735dc6abcbd33bdf1ed2634f1d |
23-Oct-2013 |
Dave Allison <dallison@google.com> |
Support hardware divide instruction
Bug: 11299025
Uses sdiv for division and a combo of sdiv, mul and sub for modulus.
Only does this on processors that are capable of the sdiv instruction, as determined
by the build system.
Also provides a command line arg --instruction-set-features= to allow cross compilation.
Makefile adds the --instruction-set-features= arg to build-time dex2oat runs and defaults
it to something obtained from the target architecture.
Provides a GetInstructionSetFeatures() function on CompilerDriver that can be
queried for various features. The only feature supported right now is hasDivideInstruction().
Also adds a few more instructions to the ARM disassembler
b/11535253 is an addition to this CL to be done later.
Change-Id: Ia8aaf801fd94bc71e476902749cf20f74eba9f68
isassembler_arm.cc
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| 1f6754dc482f0175acb05275a82b9950c3d268ee |
28-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Fix whitespace-sensitive build.
Change-Id: I82c6c49e253275543831dbaf288cb63d759ea20a
isassembler_arm.cc
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| a8b4caf7526b6b66a8ae0826bd52c39c66e3c714 |
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add byte swap instructions for ARM and x86.
Change-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d
isassembler_arm.cc
isassembler_x86.cc
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| a9650dd5e7195aec987a69a6ebbdaf33f73a6b00 |
04-Oct-2013 |
Ian Rogers <irogers@google.com> |
Implement thumb expansion of immediates.
Change-Id: Ie50c17f82cbf97a16b58350b378914030cc0499f
isassembler_arm.cc
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| 02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4 |
06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Move disassembler out of runtime.
Bug: 9877500.
Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
ndroid.mk
isassembler.cc
isassembler.h
isassembler_arm.cc
isassembler_arm.h
isassembler_mips.cc
isassembler_mips.h
isassembler_x86.cc
isassembler_x86.h
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