Cross Reference: /art/compiler/dex/quick/arm64/int

Lines Matching refs:base
470       uint64_t base = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_base);
473         reconstructed_imm = base ^ eor;
475         reconstructed_imm = base + 1;
1173     // Offset base, then use indexed load
1420 static void SpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {
1427       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);
1430                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);
1436 static void SpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {
1443       m2l->NewLIR3(FWIDE(kA64Str3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),
1447                    RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), offset);
1452 static int SpillRegsPreSub(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask,
1474 static int SpillRegsPreIndexed(Arm64Mir2Lir* m2l, RegStorage base, uint32_t core_reg_mask,
1494   int cur_offset = 2;  // What's the starting offset after the first stp? We expect the base slot
1513                      base.GetReg(), -all_offset);
1518                      base.GetReg(), -all_offset);
1525                      RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), -all_offset);
1529                      base.GetReg(), -all_offset);
1541                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), -all_offset);
1545                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), -all_offset);
1554         m2l->NewLIR3(FWIDE(kA64Str3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),
1559                      RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), cur_offset);
1570       m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(),
1581                  RegStorage::Solo64(reg1).GetReg(), base.GetReg(), cur_offset);
1589 int Arm64Mir2Lir::SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,
1598     return SpillRegsPreSub(this, base, core_reg_mask, fp_reg_mask, frame_size);
1600     return SpillRegsPreIndexed(this, base, core_reg_mask, fp_reg_mask, frame_size);
1604 static void UnSpillCoreRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {
1611       m2l->NewLIR3(WIDE(kA64Ldr3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);
1615                    RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset);
1620 static void UnSpillFPRegs(Arm64Mir2Lir* m2l, RegStorage base, int offset, uint32_t reg_mask) {
1627       m2l->NewLIR3(FWIDE(kA64Ldr3fXD), RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(),
1631                    RegStorage::FloatSolo64(reg1).GetReg(), base.GetReg(), offset);
1636 void Arm64Mir2Lir::UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask,