Cross Reference: /art/compiler/dex/quick/arm64/utility

Lines Matching refs:shift
288   for (int shift = 0; shift < 64; shift += 16) {
289     uint16_t halfword = static_cast<uint16_t>(value >> shift);
422       int shift;
425         shift = 0;
429         shift = 1;
435         res = NewLIR3(kA64Movn3rdM, r_dest.GetReg(), ~useful_bits, shift);
437         res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), useful_bits, shift);
503     int shift;
504     for (shift = 0; shift < 4; shift++) {
505       uint16_t halfword = static_cast<uint16_t>(uvalue >> (shift << 4));
507         res = NewLIR3(op, r_dest.GetReg(), halfword ^ background, shift);
513     for (shift++; shift < 4; shift++) {
514       uint16_t halfword = static_cast<uint16_t>(uvalue >> (shift << 4));
516         NewLIR3(WIDE(kA64Movk3rdM), r_dest.GetReg(), halfword, shift);
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) {
591       DCHECK_EQ(shift, 0);
602       DCHECK_EQ(shift, ENCODE_NO_SHIFT);
607       DCHECK_EQ(shift, ENCODE_NO_SHIFT);
613       DCHECK_EQ(shift, ENCODE_NO_SHIFT);
616       return OpRegRegRegShift(op, r_dest_src1, r_dest_src1, r_src2, shift);
621     DCHECK_EQ(shift, ENCODE_NO_SHIFT);
626       return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(), shift);
696                                     RegStorage r_src2, int shift) {
748   // - 4-operands instructions, where the last operand is a shift/extend immediate,
749   // - 3-operands instructions with no shift/extend.
754     DCHECK(!IsExtendEncoding(shift));
755     return NewLIR4(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(), shift);
758     DCHECK_EQ(shift, ENCODE_NO_SHIFT);
876       // TUNING: power of 2, shift & add
943   bool shift;
949     shift = false;
952     shift = true;
1003                    (shift) ? 1 : 0);
1005     return NewLIR3(opcode | wide, r_dest_src1.GetReg(), abs_value, (shift) ? 1 : 0);