Lines Matching refs:imm
294 arr, arr_kind, arr_flags, imm, \
297 { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \
298 { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \
299 { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \
300 { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \
301 { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \
302 { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \
303 { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \
304 { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \
305 { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \
306 { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \
307 { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \
308 { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" }
730 case kThreadImm: // lir operands - 0: disp, 1: imm
733 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
736 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
739 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
741 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
1022 void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) {
1025 DCHECK(IS_SIMM8(imm));
1026 code_buffer_.push_back(imm & 0xFF);
1029 DCHECK(IS_SIMM16(imm));
1030 code_buffer_.push_back(imm & 0xFF);
1031 code_buffer_.push_back((imm >> 8) & 0xFF);
1034 DCHECK(IS_SIMM32(imm));
1035 code_buffer_.push_back(imm & 0xFF);
1036 code_buffer_.push_back((imm >> 8) & 0xFF);
1037 code_buffer_.push_back((imm >> 16) & 0xFF);
1038 code_buffer_.push_back((imm >> 24) & 0xFF);
1041 code_buffer_.push_back(imm & 0xFF);
1042 code_buffer_.push_back((imm >> 8) & 0xFF);
1043 code_buffer_.push_back((imm >> 16) & 0xFF);
1044 code_buffer_.push_back((imm >> 24) & 0xFF);
1045 code_buffer_.push_back((imm >> 32) & 0xFF);
1046 code_buffer_.push_back((imm >> 40) & 0xFF);
1047 code_buffer_.push_back((imm >> 48) & 0xFF);
1048 code_buffer_.push_back((imm >> 56) & 0xFF);
1150 int32_t imm) {
1156 EmitImm(entry, imm);
1161 int32_t imm) {
1168 EmitImm(entry, imm);
1202 int32_t imm) {
1211 EmitImm(entry, imm);
1215 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) {
1224 EmitImm(entry, imm);
1228 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) {
1230 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm);
1233 void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1244 EmitImm(entry, imm);
1247 void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) {
1255 EmitImm(entry, imm);
1259 void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) {
1266 code_buffer_.push_back(imm & 0xFF);
1267 code_buffer_.push_back((imm >> 8) & 0xFF);
1268 code_buffer_.push_back((imm >> 16) & 0xFF);
1269 code_buffer_.push_back((imm >> 24) & 0xFF);
1272 code_buffer_.push_back(imm & 0xFF);
1273 code_buffer_.push_back((imm >> 8) & 0xFF);
1274 code_buffer_.push_back((imm >> 16) & 0xFF);
1275 code_buffer_.push_back((imm >> 24) & 0xFF);
1276 code_buffer_.push_back((imm >> 32) & 0xFF);
1277 code_buffer_.push_back((imm >> 40) & 0xFF);
1278 code_buffer_.push_back((imm >> 48) & 0xFF);
1279 code_buffer_.push_back((imm >> 56) & 0xFF);
1287 void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1290 if (imm != 1) {
1302 if (imm != 1) {
1304 DCHECK(IS_SIMM8(imm));
1305 code_buffer_.push_back(imm & 0xFF);
1340 int32_t imm) {
1343 if (imm != 1) {
1354 if (imm != 1) {
1356 DCHECK(IS_SIMM8(imm));
1357 code_buffer_.push_back(imm & 0xFF);
1795 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
1798 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
1801 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm