Lines Matching refs:opcode
291 if (lir->opcode == kX86RepneScasw) {
557 bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) {
558 switch (opcode) {
594 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) {
756 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
789 if (X86Mir2Lir::EncodingMap[i].opcode != i) {
792 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
894 uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
895 DCHECK(!IsPseudoLirOp(opcode));
896 return X86Mir2Lir::EncodingMap[opcode].flags;
899 const char* X86Mir2Lir::GetTargetInstName(int opcode) {
900 DCHECK(!IsPseudoLirOp(opcode));
901 return X86Mir2Lir::EncodingMap[opcode].name;
904 const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
905 DCHECK(!IsPseudoLirOp(opcode));
906 return X86Mir2Lir::EncodingMap[opcode].fmt;
1058 DCHECK_EQ(p->opcode, kX86Mov32RI);
1075 DCHECK_EQ(p->opcode, kX86Mov32RI);
1087 DCHECK_EQ(p->opcode, kX86CallI);
1449 // Encoding in opcode.
1686 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
1799 // Append the mov const vector to reg opcode.
1803 void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) {
1823 LIR *load = NewLIR2(opcode, reg, rl_method.reg.GetReg());
1883 int opcode = 0;
1886 opcode = kX86PmulldRR;
1889 opcode = kX86PmullwRR;
1892 opcode = kX86MulpsRR;
1895 opcode = kX86MulpdRR;
1905 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg());
1913 int opcode = 0;
1916 opcode = kX86PadddRR;
1920 opcode = kX86PaddwRR;
1924 opcode = kX86PaddbRR;
1927 opcode = kX86AddpsRR;
1930 opcode = kX86AddpdRR;
1936 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg());
1944 int opcode = 0;
1947 opcode = kX86PsubdRR;
1951 opcode = kX86PsubwRR;
1955 opcode = kX86PsubbRR;
1958 opcode = kX86SubpsRR;
1961 opcode = kX86SubpdRR;
1967 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg());
1974 int opcode = 0;
1977 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
1979 opcode = kX86PsllwRI;
1982 opcode = kX86PsrawRI;
1985 opcode = kX86PsrlwRI;
1988 LOG(FATAL) << "Unsupported shift operation on byte vector " << opcode;
2007 NewLIR2(opcode, rs_dest_src1.GetReg(), imm);
2013 NewLIR2(opcode, rs_tmp.GetReg(), imm);
2024 int opcode = 0;
2027 opcode = kX86PslldRI;
2030 opcode = kX86PsllqRI;
2034 opcode = kX86PsllwRI;
2044 NewLIR2(opcode, rs_dest_src1.GetReg(), imm);
2052 int opcode = 0;
2055 opcode = kX86PsradRI;
2059 opcode = kX86PsrawRI;
2069 NewLIR2(opcode, rs_dest_src1.GetReg(), imm);
2077 int opcode = 0;
2080 opcode = kX86PsrldRI;
2083 opcode = kX86PsrlqRI;
2087 opcode = kX86PsrlwRI;
2097 NewLIR2(opcode, rs_dest_src1.GetReg(), imm);
2128 void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) {
2132 const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector);
2139 AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp);
2150 int opcode = 0;
2157 opcode = kX86PhadddRR;
2163 opcode = kX86PhaddwRR;
2169 opcode = kX86PhaddwRR;
2206 NewLIR2(opcode, rs_tmp.GetReg(), rs_tmp.GetReg());
2208 NewLIR2(opcode, rs_src1.GetReg(), rs_src1.GetReg());