Lines Matching refs:opcode
385 // MR - Memory Register - opcode [base + disp], reg
387 // AR - Array Register - opcode [base + index * scale + disp], reg
389 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current()
391 // RR - Register Register - opcode reg1, reg2
393 // RM - Register Memory - opcode reg, [base + disp]
395 // RA - Register Array - opcode reg, [base + index * scale + disp]
397 // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current()
399 // RI - Register Immediate - opcode reg, #immediate
401 // MI - Memory Immediate - opcode [base + disp], #immediate
403 // AI - Array Immediate - opcode [base + index * scale + disp], #immediate
405 // TI - Thread Immediate - opcode fs:[disp], imm - where fs: is equal to Thread::Current()
407 #define BinaryOpCode(opcode) \
408 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \
409 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \
410 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \
411 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \
412 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \
413 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \
414 opcode ## 16RI8, opcode ## 16MI8, opcode ## 16AI8, opcode ## 16TI8, \
415 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \
416 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \
417 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, opcode ## 32TI, \
418 opcode ## 32RI8, opcode ## 32MI8, opcode ## 32AI8, opcode ## 32TI8, \
419 opcode ## 64MR, opcode ## 64AR, opcode ## 64TR, \
420 opcode ## 64RR, opcode ## 64RM, opcode ## 64RA, opcode ## 64RT, \
421 opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, opcode ## 64TI, \
422 opcode ## 64RI8, opcode ## 64MI8, opcode ## 64AI8, opcode ## 64TI8
462 // RC - Register CL - opcode reg, CL
464 // MC - Memory CL - opcode [base + disp], CL
466 // AC - Array CL - opcode [base + index * scale + disp], CL
468 #define BinaryShiftOpCode(opcode) \
469 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, \
470 opcode ## 8RC, opcode ## 8MC, opcode ## 8AC, \
471 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, \
472 opcode ## 16RC, opcode ## 16MC, opcode ## 16AC, \
473 opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, \
474 opcode ## 32RC, opcode ## 32MC, opcode ## 32AC, \
475 opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, \
476 opcode ## 64RC, opcode ## 64MC, opcode ## 64AC
494 #define UnaryOpcode(opcode, reg, mem, array) \
495 opcode ## 8 ## reg, opcode ## 8 ## mem, opcode ## 8 ## array, \
496 opcode ## 16 ## reg, opcode ## 16 ## mem, opcode ## 16 ## array, \
497 opcode ## 32 ## reg, opcode ## 32 ## mem, opcode ## 32 ## array, \
498 opcode ## 64 ## reg, opcode ## 64 ## mem, opcode ## 64 ## array
515 #define Binary0fOpCode(opcode) \
516 opcode ## RR, opcode ## RM, opcode ## RA
665 kRegOpcode, // Shorter form of R instruction kind (opcode+rd)
676 kShiftRegImm, kShiftMemImm, kShiftArrayImm, // Shift opcode with immediate.
677 kShiftRegCl, kShiftMemCl, kShiftArrayCl, // Shift opcode with register CL.
688 /* Struct used to define the EncodingMap positions for each X86 opcode */
690 X86OpCode opcode; // e.g. kOpAddRI
692 // hold meaning for the opcode.
698 uint8_t opcode; // 1 byte opcode.
699 uint8_t extra_opcode1; // Possible extra opcode byte.
700 uint8_t extra_opcode2; // Possible second extra opcode byte.
701 // 3-bit opcode that gets encoded in the register bits of the modrm byte, use determined by the