Cross Reference: /art/compiler/utils/arm/assembler

Lines Matching refs:rn
28 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so,
30   EmitType01(cond, so.type(), AND, 0, rn, rd, so);
34 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so,
36   EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
40 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so,
42   EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
45 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so,
47   EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
50 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so,
52   EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
56 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so,
58   EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
62 void Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so,
64   EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
68 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so,
70   EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
74 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so,
76   EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
80 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so,
82   EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
86 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so,
88   EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
92 void Arm32Assembler::tst(Register rn, const ShifterOperand& so, Condition cond) {
93   CHECK_NE(rn, PC);  // Reserve tst pc instruction for exception handler marker.
94   EmitType01(cond, so.type(), TST, 1, rn, R0, so);
98 void Arm32Assembler::teq(Register rn, const ShifterOperand& so, Condition cond) {
99   CHECK_NE(rn, PC);  // Reserve teq pc instruction for exception handler marker.
100   EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
104 void Arm32Assembler::cmp(Register rn, const ShifterOperand& so, Condition cond) {
105   EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
109 void Arm32Assembler::cmn(Register rn, const ShifterOperand& so, Condition cond) {
110   EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
114 void Arm32Assembler::orr(Register rd, Register rn,
116   EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
120 void Arm32Assembler::orrs(Register rd, Register rn,
122   EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
136 void Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so,
138   EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
152 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
153   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
154   EmitMulOp(cond, 0, R0, rd, rn, rm);
158 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra,
160   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
161   EmitMulOp(cond, B21, ra, rd, rn, rm);
165 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra,
167   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
168   EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
172 void Arm32Assembler::umull(Register rd_lo, Register rd_hi, Register rn,
174   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
175   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
179 void Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
181   CHECK_NE(rn, kNoRegister);
187       (static_cast<int32_t>(rn) << 0) |
195 void Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
197   CHECK_NE(rn, kNoRegister);
203       (static_cast<int32_t>(rn) << 0) |
518                                 Register rn,
527                      static_cast<int32_t>(rn) << kRnShift |
695                                Register rd, Register rn,
698   CHECK_NE(rn, kNoRegister);
704       (static_cast<int32_t>(rn) << kRnShift) |
712 void Arm32Assembler::ldrex(Register rt, Register rn, Condition cond) {
713   CHECK_NE(rn, kNoRegister);
720                      (static_cast<int32_t>(rn) << kLdExRnShift) |
729                            Register rn,
731   CHECK_NE(rn, kNoRegister);
738                      (static_cast<int32_t>(rn) << kStrExRnShift) |
1096 void Arm32Assembler::Lsl(Register rd, Register rm, Register rn,
1099     movs(rd, ShifterOperand(rm, LSL, rn), cond);
1101     mov(rd, ShifterOperand(rm, LSL, rn), cond);
1106 void Arm32Assembler::Lsr(Register rd, Register rm, Register rn,
1109     movs(rd, ShifterOperand(rm, LSR, rn), cond);
1111     mov(rd, ShifterOperand(rm, LSR, rn), cond);
1116 void Arm32Assembler::Asr(Register rd, Register rm, Register rn,
1119     movs(rd, ShifterOperand(rm, ASR, rn), cond);
1121     mov(rd, ShifterOperand(rm, ASR, rn), cond);
1126 void Arm32Assembler::Ror(Register rd, Register rm, Register rn,
1129     movs(rd, ShifterOperand(rm, ROR, rn), cond);
1131     mov(rd, ShifterOperand(rm, ROR, rn), cond);
1244 void Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value,
1247     if (rd != rn) {
1248       mov(rd, ShifterOperand(rn), cond);
1257     add(rd, rn, shifter_op, cond);
1259     sub(rd, rn, shifter_op, cond);
1261     CHECK(rn != IP);
1264       add(rd, rn, ShifterOperand(IP), cond);
1267       sub(rd, rn, ShifterOperand(IP), cond);
1274       add(rd, rn, ShifterOperand(IP), cond);
1280 void Arm32Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
1284     adds(rd, rn, shifter_op, cond);
1286     subs(rd, rn, shifter_op, cond);
1288     CHECK(rn != IP);
1291       adds(rd, rn, ShifterOperand(IP), cond);
1294       subs(rd, rn, ShifterOperand(IP), cond);
1301       adds(rd, rn, ShifterOperand(IP), cond);
1479 void Arm32Assembler::cbz(Register rn, Label* target) {
1484 void Arm32Assembler::cbnz(Register rn, Label* target) {