Cross Reference: /art/compiler/utils/arm64/assembler

Lines Matching refs:dst
288   Arm64ManagedRegister dst = m_dst.AsArm64();
289   CHECK(dst.IsCoreRegister()) << dst;
290   LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), SP, offs.Int32Value());
295   Arm64ManagedRegister dst = m_dst.AsArm64();
297   CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
298   LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), base.AsCoreRegister(),
303   Arm64ManagedRegister dst = m_dst.AsArm64();
305   CHECK(dst.IsCoreRegister() && base.IsCoreRegister());
306   // Remove dst and base form the temp list - higher level API uses IP1, IP0.
308   temps.Exclude(reg_x(dst.AsCoreRegister()), reg_x(base.AsCoreRegister()));
309   ___ Ldr(reg_x(dst.AsCoreRegister()), MEM_OP(reg_x(base.AsCoreRegister()), offs.Int32Value()));
313   Arm64ManagedRegister dst = m_dst.AsArm64();
314   CHECK(dst.IsCoreRegister()) << dst;
315   LoadFromOffset(dst.AsCoreRegister(), ETR, offs.Int32Value());
320   Arm64ManagedRegister dst = m_dst.AsArm64();
322   if (!dst.Equals(src)) {
323     if (dst.IsCoreRegister()) {
326         ___ Mov(reg_x(dst.AsCoreRegister()), reg_w(src.AsWRegister()));
329           ___ Mov(reg_x(dst.AsCoreRegister()), reg_x(src.AsCoreRegister()));
331           ___ Mov(reg_x(dst.AsCoreRegister()), reg_w(src.AsWRegister()));
334     } else if (dst.IsWRegister()) {
336       ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister()));
337     } else if (dst.IsSRegister()) {
339       ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister()));
341       CHECK(dst.IsDRegister()) << dst;
343       ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));
430 void Arm64Assembler::Copy(FrameOffset /*dst*/, FrameOffset /*src_base*/, Offset /*src_offset*/,
465 void Arm64Assembler::Copy(FrameOffset /*dst*/, Offset /*dest_offset*/,