Lines Matching refs:offs

122 void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) {
128 StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value());
131 StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
133 StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value());
136 StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value());
140 void Arm64Assembler::StoreRef(FrameOffset offs, ManagedRegister m_src) {
144 offs.Int32Value());
147 void Arm64Assembler::StoreRawPtr(FrameOffset offs, ManagedRegister m_src) {
150 StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value());
153 void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm,
159 offs.Int32Value());
162 void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm,
167 StoreToOffset(scratch.AsCoreRegister(), ETR, offs.Int32Value());
287 void Arm64Assembler::LoadRef(ManagedRegister m_dst, FrameOffset offs) {
290 LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), SP, offs.Int32Value());
294 MemberOffset offs) {
299 offs.Int32Value());
302 void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) {
309 ___ Ldr(reg_x(dst.AsCoreRegister()), MEM_OP(reg_x(base.AsCoreRegister()), offs.Int32Value()));
312 void Arm64Assembler::LoadRawPtrFromThread64(ManagedRegister m_dst, ThreadOffset<8> offs) {
315 LoadFromOffset(dst.AsCoreRegister(), ETR, offs.Int32Value());
508 void Arm64Assembler::Call(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) {
513 LoadFromOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value());
517 void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) {
525 ___ Ldr(reg_x(scratch.AsCoreRegister()), MEM_OP(reg_x(base.AsCoreRegister()), offs.Int32Value()));
529 void Arm64Assembler::Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) {
534 LoadFromOffset(scratch.AsCoreRegister(), scratch.AsCoreRegister(), offs.Int32Value());