Lines Matching defs:op

269         uint32_t op = (instruction >> 21) & 0xf;
270 opcode = kDataProcessingOperations[op];
271 bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN.
272 bool is_mov = op == 0b1101 || op == 0b1111;
400 uint64_t AdvSIMDExpand(uint32_t op, uint32_t cmode, uint32_t imm8) {
401 CHECK_EQ(op & 1, op);
421 if ((cmode & 1) == 0 && op == 0) {
424 } else if ((cmode & 1) == 0 && op != 0) {
430 } else if ((cmode & 1) != 0 && op == 0) {
467 // |111|01|00|op|0|WL| Rn | |
473 uint32_t op = (instr >> 23) & 3;
477 if (op == 1 || op == 2) {
478 if (op == 1) {
835 } else if ((op3 >> 4) == 2 && op4 == 0) { // 10xxxx, op = 0
891 // |1110|1110|1|D|11|0100| Vd |101|S|op|1|M|0| Vm | VCMP
892 // |1110|1110|1|D|11|0101| Vd |101|S|op|1|0|0|0000| VCMPE
893 // |1110|1110|1|D|11|op5 | Vd |101|S|op|1|M|0| Vm | VCVT
895 uint32_t op = (instr >> 7) & 1;
902 opcode << (op == 0 ? "vmov" : "vabs") << (S != 0 ? ".f64" : ".f32");
905 opcode << (op != 0 ? "vsqrt" : "vneg") << (S != 0 ? ".f64" : ".f32");
910 if (op != 0) {
916 if (op != 0) {
925 opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f64";
929 opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f32";
935 opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f64";
939 opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f32";
945 opcode << "vcvt.f64." << (op == 0 ? "u" : "s") << "32";
949 opcode << "vcvt.f32." << (op == 0 ? "u" : "s") << "32";
953 if (op == 1) {
969 } else if ((op3 >> 4) == 2 && op4 == 1) { // 10xxxx, op = 1
978 // |1110|1110|000|op| Vn | Rt |1010|N|00|1|0000|
979 uint32_t op = op3 & 1;
983 if (op) {
1838 uint16_t op = (instr >> 11) & 1;
1842 opcode << (op != 0 ? "cbnz" : "cbz");
1851 uint16_t op = (instr >> 6) & 3;
1852 opcode << kThumbReverseOperations[op];