Lines Matching refs:getSUnit

201     Topo.AddPred(SU, D.getSUnit());
209 Topo.RemovePred(SU, D.getSUnit());
367 SUnit *PredSU = PredEdge->getSUnit();
537 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
539 LiveRegDefs[I->getReg()] = I->getSUnit();
793 SUnit *PredSU = PredEdge->getSUnit();
815 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
861 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
862 LiveRegGens[I->getReg()] = I->getSUnit();
1027 else if (isOperandOf(I->getSUnit(), LoadNode))
1060 SUnit *SuccDep = D.getSUnit();
1072 SUnit *SuccDep = D.getSUnit();
1116 SUnit *SuccSU = I->getSUnit();
1156 SUnit *SuccSU = I->getSUnit();
1269 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1844 SUnit *PredSU = I->getSUnit();
1947 SUnit *PredSU = I->getSUnit();
1997 SUnit *PredSU = I->getSUnit();
2041 SUnit *PredSU = I->getSUnit();
2123 SUnit *PredSU = I->getSUnit();
2191 unsigned Height = I->getSUnit()->getHeight();
2194 if (I->getSUnit()->getNode() &&
2195 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2196 Height = closestSucc(I->getSUnit())+1;
2222 const SUnit *PredSU = I->getSUnit();
2245 const SUnit *SuccSU = I->getSUnit();
2283 I->getSUnit()->isVRegCycle = true;
2296 SUnit *PredSU = I->getSUnit();
2300 I->getSUnit()->isVRegCycle = 0;
2315 if (I->getSUnit()->isVRegCycle &&
2316 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2715 SUnit *SuccSU = SI->getSUnit();
2722 scheduleDAG->IsReachable(DepSU, PI->getSUnit()))
2731 scheduleDAG->IsReachable(DepSU, PI->getSUnit()))
2833 PredSU = II->getSUnit();
2856 SUnit *PredSuccSU = II->getSUnit();
2879 SUnit *SuccSU = Edge.getSUnit();
2926 SUnit *SuccSU = I->getSUnit();
2942 SuccSU = SuccSU->Succs.front().getSUnit();