Lines Matching refs:i8

64   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
80 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
92 setOperationAction(ISD::SRA, MVT::i8, Custom);
93 setOperationAction(ISD::SHL, MVT::i8, Custom);
94 setOperationAction(ISD::SRL, MVT::i8, Custom);
98 setOperationAction(ISD::ROTL, MVT::i8, Expand);
99 setOperationAction(ISD::ROTR, MVT::i8, Expand);
106 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i8, Custom);
111 setOperationAction(ISD::SELECT, MVT::i8, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
121 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
123 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
125 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
130 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
132 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
140 setOperationAction(ISD::MUL, MVT::i8, Expand);
141 setOperationAction(ISD::MULHS, MVT::i8, Expand);
142 setOperationAction(ISD::MULHU, MVT::i8, Expand);
143 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
144 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
151 setOperationAction(ISD::UDIV, MVT::i8, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
153 setOperationAction(ISD::UREM, MVT::i8, Expand);
154 setOperationAction(ISD::SDIV, MVT::i8, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
156 setOperationAction(ISD::SREM, MVT::i8, Expand);
234 if (VT == MVT::i8)
307 // Promote i8 to i16
308 if (LocVT == MVT::i8) {
889 TargetCC = DAG.getConstant(TCC, MVT::i8);
1123 if (VT != MVT::i8 && VT != MVT::i16)
1132 (VT == MVT::i8 && RHSC != 1))
1185 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;