Lines Matching refs:Emit
78 void Emit(uint32_t value, raw_ostream &OS) const;
79 void Emit(uint64_t value, raw_ostream &OS) const;
166 Emit(inst, OS);
180 Emit(InstWord01, OS);
181 Emit(InstWord2, OS);
212 // Emit instruction type
224 // Emit zeros for unused sources
242 // Emit the source select (2 bytes). For GPRs, this is the register index.
263 // Emit the source channel (1 byte)
270 // XXX: Emit isNegated (1 byte)
280 // Emit isAbsolute (1 byte)
287 // XXX: Emit relative addressing mode (1 byte)
290 // Emit kc_bank, This will be adjusted later by r600_asm
293 // Emit the literal value, if applicable (4 bytes).
294 Emit(Value.i, OS);
302 // Emit the destination register index (1 byte)
305 // Emit the element of the destination register (1 byte)
308 // Emit isClamped (1 byte)
315 // Emit writemask (1 byte).
322 // XXX: Emit relative addressing mode
335 // Emit the instruction (2 bytes)
338 // Emit IsLast (for this instruction group) (1 byte)
345 // Emit isOp3 (1 byte)
352 // XXX: Emit push modifier
359 // XXX: Emit predicate (1 byte)
378 // XXX: Emit bank swizzle. (1 byte) Do we need this? It looks like
382 // XXX: Emit bank_swizzle_force (1 byte) Not sure what this is for.
385 // XXX: Emit OMOD (1 byte) Not implemented.
388 // XXX: Emit index_mode. I think this is for indirect addressing, so we
404 // Emit instruction type
407 // Emit instruction
410 // XXX: Emit resource id r600_shader.c uses sampler + 1. Why?
413 // Emit source register
416 // XXX: Emit src isRelativeAddress
419 // Emit destination register
422 // XXX: Emit dst isRealtiveAddress
425 // XXX: Emit dst select
431 // XXX: Emit lod bias
434 // XXX: Emit coord types
460 // XXX: Emit offsets
467 // Emit sampler id
470 // XXX:Emit source select
487 // Emit instruction type
490 // Emit SRC
499 // Emit FC Instruction
563 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
569 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {