Lines Matching refs:reg2
1415 const Register& reg2,
1418 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1427 const FPRegister& reg2,
1430 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1446 const Register& reg2,
1449 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1455 const FPRegister& reg2,
1458 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1464 const CPURegister& reg2,
1470 const CPURegister regs[] = {reg1, reg2, reg3, reg4};