Cross Reference: /hardware/intel/img/psb_video/src/psb

Lines Matching defs:regs
135     struct drm_psb_register_rw_arg regs;
143     memset(&regs, 0, sizeof(regs));
145         regs.overlay_write_mask |= OV_REGRWBITS_OGAM_ALL | OVC_REGRWBITS_OGAM_ALL;
147         regs.overlay_write_mask |= OV_REGRWBITS_OGAM_ALL;
148     regs.overlay.OGAMC0 = gamma0;
149     regs.overlay.OGAMC1 = gamma1;
150     regs.overlay.OGAMC2 = gamma2;
151     regs.overlay.OGAMC3 = gamma3;
152     regs.overlay.OGAMC4 = gamma4;
153     regs.overlay.OGAMC5 = gamma5;
154     drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
164     struct drm_psb_register_rw_arg regs;
176     memset(&regs, 0, sizeof(regs));
178         regs.subpicture_disable_mask = pPriv->subpicture_enable_mask;
180         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
183     memset(&regs, 0, sizeof(regs));
187             regs.overlay_read_mask = OVC_REGRWBITS_OVADD;
188             drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
192             regs.overlay_read_mask = 0;
193             regs.overlay_write_mask = OVC_REGRWBITS_OVADD;
194             regs.overlay.b_wait_vblank = 1;
195             drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
197             memset(&regs, 0, sizeof(regs));
201             regs.overlay_read_mask = OV_REGRWBITS_OVADD;
202             drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
206             regs.overlay_read_mask = 0;
207             regs.overlay_write_mask = OV_REGRWBITS_OVADD;
208             regs.overlay.b_wait_vblank = 1;
209             drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
213         regs.overlay_read_mask = OV_REGRWBITS_OVADD;
214         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
218         regs.overlay_read_mask = 0;
219         regs.overlay_write_mask = OV_REGRWBITS_OVADD;
220         regs.overlay.b_wait_vblank = 1;
221         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
233     struct drm_psb_register_rw_arg regs;
244     memset(&regs, 0, sizeof(regs));
256     regs.overlay_read_mask = overlay_mask;
257     drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
270     regs.overlay_read_mask = 0;
271     regs.overlay_write_mask = overlay_mask;
272     regs.overlay.b_wait_vblank = 1;
273     drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
427     struct drm_psb_register_rw_arg regs;
433         memset(&regs, 0, sizeof(regs));
434         regs.overlay_read_mask = OV_REGRWBITS_OVADD;
435         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
438         regs.overlay_read_mask = 0;
439         regs.overlay_write_mask = OV_REGRWBITS_OVADD;
440         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
777     memset(&regs, 0, sizeof(regs));
781         regs.overlay_write_mask = OV_REGRWBITS_OVADD;
785         regs.overlay_write_mask = OVC_REGRWBITS_OVADD;
798             regs.overlay.OVADD = offset | 1;
799             regs.overlay.IEP_ENABLED = 0;
800             regs.overlay.buffer_handle = wsbmKBufHandle(wsbmKBuf(pPriv->wsbo[overlayId]));
805         regs.overlay.OVADD = offset | 1;
817             regs.overlay.OVADD |= 0x80;
822             regs.overlay.OVADD |= 0x40;
830         regs.overlay.b_wms = 1;
832     drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
835         if (regs.overlay.IEP_ENABLED) {
837             printf("regs.overlay BLE minmax 0x%x, BSSCC control 0x%x\n",
838                    regs.overlay.IEP_BLE_MINMAX, regs.overlay.IEP_BSSCC_CONTROL);
840             *(unsigned int *)((unsigned int)&(overlay->IEP_SPACE[0]) + 0x804)  = regs.overlay.IEP_BLE_MINMAX;
1378     struct drm_psb_register_rw_arg regs;
1393         memset(&regs, 0, sizeof(regs));
1394         regs.display_read_mask = REGRWBITS_DSPBCNTR;
1395         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
1396         regs.display.dspcntr_b |= DISPPLANE_BOTTOM;
1397         regs.display_write_mask = REGRWBITS_DSPBCNTR;
1398         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
1418     struct drm_psb_register_rw_arg regs;
1423         memset(&regs, 0, sizeof(regs));
1424         regs.display_read_mask = REGRWBITS_DSPBCNTR;
1425         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));
1426         regs.display.dspcntr_b &= ~DISPPLANE_BOTTOM;
1427         regs.display_write_mask = REGRWBITS_DSPBCNTR;
1428         drmCommandWriteRead(driver_data->drm_fd, DRM_PSB_REGISTER_RW, &regs, sizeof(regs));