Searched defs:Ins (Results 1 - 25 of 32) sorted by relevance

12

/external/chromium_org/third_party/yasm/source/patched-yasm/tools/re2c/
H A Dins.h15 typedef union Ins { union
26 } Ins; typedef in typeref:union:Ins
28 static int isMarked(Ins *i){
32 static void mark(Ins *i){
36 static void unmark(Ins *i){
/external/llvm/lib/Transforms/IPO/
H A DIPConstantPropagation.cpp250 Instruction *Ins = cast<Instruction>(*I); local
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
H A DPartialInlining.cpp94 BasicBlock::iterator Ins = newReturnBlock->begin(); local
99 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
101 Ins = newReturnBlock->getFirstNonPHI();
/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
69 unsigned NumArgs = Ins.size();
72 MVT ArgVT = Ins[i].VT;
73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
157 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
158 MVT VT = Ins[i].VT;
159 ISD::ArgFlagsTy Flags = Ins[i].Flags;
H A DRegAllocGreedy.cpp896 unsigned Ins = 0; local
901 BC.Entry = SpillPlacement::MustSpill, ++Ins; local
903 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local
905 ++Ins;
911 BC.Exit = SpillPlacement::MustSpill, ++Ins; local
913 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local
915 ++Ins;
919 while (Ins--)
1107 unsigned Ins = 0; local
1110 Ins
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp67 &Ins,
70 unsigned NumArgs = Ins.size();
81 EVT ArgVT = Ins[i].VT;
82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
184 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
185 EVT VT = Ins[i].VT;
66 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) argument
H A DHexagonISelLowering.cpp366 SmallVectorImpl<ISD::InputArg> &Ins,
378 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
401 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
446 Outs, OutVals, Ins, DAG);
611 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
832 SmallVectorImpl<ISD::InputArg> &Ins,
849 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
862 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1673 const SmallVectorImpl<ISD::InputArg> &Ins,
363 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument
828 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1665 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp52 const SmallVectorImpl<ISD::InputArg> &Ins,
58 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/include/llvm/Transforms/Utils/
H A DSSAUpdaterImpl.h73 SmallVectorImpl<PhiT*> *Ins) :
74 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { }
72 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp289 MachineBasicBlock::iterator Ins = MBB->begin(); local
291 if (Ins != MBB->end())
292 DL = Ins->getDebugLoc();
300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp52 const SmallVectorImpl<ISD::InputArg> &Ins,
58 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp587 MachineBasicBlock::iterator Ins = MBB->begin(); local
589 if (Ins != MBB->end())
590 DL = Ins->getDebugLoc();
598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp948 MachineBasicBlock::iterator Ins = MBB->begin(); local
950 if (Ins != MBB->end())
951 DL = Ins->getDebugLoc();
959 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp272 const SmallVectorImpl<ISD::InputArg> &Ins) {
273 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
347 const SmallVectorImpl<ISD::InputArg> &Ins) {
348 State.AnalyzeCallResult(Ins, RetCC_MSP430);
372 &Ins,
383 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
385 if (Ins.empty())
398 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
414 Outs, OutVals, Ins, d
271 AnalyzeVarArgs(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
346 AnalyzeRetResult(CCState &State, const SmallVectorImpl<ISD::InputArg> &Ins) argument
368 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
424 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
575 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
714 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h104 Ins, enumerator in enum:llvm::MipsISD::NodeType
364 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
368 void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
466 const SmallVectorImpl<ISD::InputArg> &Ins,
529 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h82 std::pair<CompMap::iterator, bool> Ins = local
93 return (Ins.second || Ins.first->second == B) ? nullptr
94 : Ins.first->second;
H A DCodeGenRegisters.cpp327 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = local
329 if (Ins->second == SI->first)
337 SI->first->getName() + " and " + Ins->second->getName());
/external/llvm/include/llvm/TableGen/
H A DRecord.h1668 bool Ins = Classes.insert(std::make_pair(R->getName(), R)).second; local
1669 (void)Ins;
1670 assert(Ins && "Class already exists");
1673 bool Ins = Defs.insert(std::make_pair(R->getName(), R)).second; local
1674 (void)Ins;
1675 assert(Ins && "Record already exists");
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp1662 const SmallVectorImpl<ISD::InputArg> &Ins,
1673 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1677 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1679 EVT VT = Ins[i].VT;
1702 //ISD::LoadExtType Ext = Ins[i].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1658 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
H A DSIISelLowering.cpp308 const SmallVectorImpl<ISD::InputArg> &Ins,
323 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
324 const ISD::InputArg &Arg = Ins[i];
383 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
389 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
391 const ISD::InputArg &Arg = Ins[i];
401 VT = Ins[i].VT;
407 Ins[i].Flags.isSExt());
304 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
H A DAMDGPUISelLowering.cpp483 const SmallVectorImpl<ISD::InputArg> &Ins) const {
485 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
2041 const SmallVectorImpl<ISD::InputArg> &Ins,
2044 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2045 if (Ins[i].ArgVT == Ins[i].VT) {
2046 OrigIns.push_back(Ins[i]);
2051 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2053 VT = Ins[
2038 getOriginalFunctionArgs( SelectionDAG &DAG, const Function *F, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<ISD::InputArg> &OrigIns) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1038 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
1056 Outs, OutVals, Ins, dl, DAG, InVals);
1115 const SmallVectorImpl<ISD::InputArg> &Ins,
1135 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1251 const SmallVectorImpl<ISD::InputArg> &Ins,
1263 Ins, dl, DAG, InVals);
1276 &Ins,
1290 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1356 const ArgDataPair ADP = { ArgIn, Ins[
1110 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1248 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1272 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp75 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
657 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
967 if (Ins.size() > 0) {
1020 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
1066 if (Ins.size() > 0) {
1197 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1199 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1220 LoadRetVTs.push_back(Ins[i].VT);
1237 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[
1626 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp324 const SmallVectorImpl<ISD::InputArg> &Ins,
329 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
331 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
342 const SmallVectorImpl<ISD::InputArg> &Ins,
354 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
362 if (Ins[InIdx].Flags.isSRet()) {
544 const SmallVectorImpl<ISD::InputArg> &Ins,
554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
689 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; local
321 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
541 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp3034 SmallVector<ISD::InputArg, 32> Ins; local
3051 Ins.push_back(MyFlags);
3061 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);

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