/external/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 22 bool IsCPSRDead(InstrType *Instr); 25 inline bool isV8EligibleForIT(InstrType *Instr) { argument 26 switch (Instr->getOpcode()) { 53 return IsCPSRDead(Instr); 79 return Instr->getOperand(2).getReg() != ARM::PC; 84 return Instr->getOperand(0).getReg() != ARM::PC; 86 return Instr->getOperand(0).getReg() != ARM::PC && 87 Instr->getOperand(2).getReg() != ARM::PC; 90 return Instr->getOperand(0).getReg() != ARM::PC && 91 Instr [all...] |
H A D | ARMBaseInstrInfo.cpp | 2312 const MachineInstr &Instr = *I; local 2314 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 2315 Instr.readsRegister(ARM::CPSR, TRI)) 2389 const MachineInstr &Instr = *I; local 2390 for (unsigned IO = 0, EO = Instr.getNumOperands(); 2392 const MachineOperand &MO = Instr.getOperand(IO); 2406 switch (Instr.getOpcode()) { 2409 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXImageOptimizer.cpp | 61 Instruction &Instr = *I; local 69 Changed |= replaceIsTypePSampler(Instr); 72 Changed |= replaceIsTypePSurface(Instr); 75 Changed |= replaceIsTypePTexture(Instr);
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreLowerThreadLocal.cpp | 78 createReplacementInstr(ConstantExpr *CE, Instruction *Instr) { argument 79 IRBuilder<true,NoFolder> Builder(Instr); 145 } else if (Instruction *Instr = dyn_cast<Instruction>(WU)) { 146 Instruction *NewInst = createReplacementInstr(CE, Instr); 147 Instr->replaceUsesOfWith(CE, NewInst);
|
/external/chromium_org/v8/src/mips64/ |
H A D | constants-mips64.h | 189 typedef int32_t Instr; typedef in namespace:v8::internal 721 extern const Instr kPopInstruction; 723 extern const Instr kPushInstruction; 725 extern const Instr kPushRegPattern; 727 extern const Instr kPopRegPattern; 728 extern const Instr kLwRegFpOffsetPattern; 729 extern const Instr kSwRegFpOffsetPattern; 730 extern const Instr kLwRegFpNegOffsetPattern; 731 extern const Instr kSwRegFpNegOffsetPattern; 733 extern const Instr kRtMas [all...] |
/external/llvm/include/llvm/IR/ |
H A D | DiagnosticInfo.h | 106 const Instruction *Instr; member in class:llvm::DiagnosticInfoInlineAsm 115 Instr(nullptr) {} 124 MsgStr(MsgStr), Instr(nullptr) {} 126 /// \p Instr gives the original instruction that triggered the diagnostic. 136 const Instruction *getInstruction() const { return Instr; }
|
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | WinCodeViewLineTables.cpp | 176 MCSymbol *Instr = FI.Instrs[J]; local 177 assert(InstrInfo.count(Instr)); 206 EmitLabelDiff(Asm->OutStreamer, Fn, Instr); 207 Asm->EmitInt32(InstrInfo[Instr].LineNumber);
|
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64PromoteConstant.cpp | 239 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr, argument 243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) 247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) 251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) 254 if (isa<const AllocaInst>(Instr) && OpIdx > 0) 258 if (isa<const LoadInst>(Instr) && OpIdx > 0) 262 if (isa<const StoreInst>(Instr) && OpIdx > 1) 266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) 271 if (isa<const LandingPadInst>(Instr)) 275 if (isa<const SwitchInst>(Instr)) [all...] |
H A D | AArch64CollectLOH.cpp | 540 static bool isCandidateStore(const MachineInstr *Instr) { argument 541 switch (Instr->getOpcode()) { 554 if (Instr->getOperand(0).getReg() != Instr->getOperand(1).getReg()) 655 static bool isCandidateLoad(const MachineInstr *Instr) { argument 656 switch (Instr->getOpcode()) { 671 if (Instr->getOperand(2).getTargetFlags() & AArch64II::MO_GOT) 680 static bool supportLoadFromLiteral(const MachineInstr *Instr) { argument 681 switch (Instr->getOpcode()) { 697 /// \param UseToDefs is used to check that Instr i 701 isCandidate(const MachineInstr *Instr, const InstrToInstrs &UseToDefs, const MachineDominatorTree *MDT) argument [all...] |
H A D | AArch64InstrInfo.cpp | 661 static bool UpdateOperandRegClass(MachineInstr *Instr) { argument 662 MachineBasicBlock *MBB = Instr->getParent(); 671 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx; 673 MachineOperand &MO = Instr->getOperand(OpIdx); 675 Instr->getRegClassConstraint(OpIdx, TII, TRI); 772 const MachineInstr &Instr = *I; local 774 if (Instr.modifiesRegister(AArch64::NZCV, TRI) || 775 Instr.readsRegister(AArch64::NZCV, TRI)) 823 const MachineInstr &Instr = *I; local 824 for (unsigned IO = 0, EO = Instr [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600OptimizeVectorRegisters.cpp | 63 MachineInstr *Instr; member in class:__anon26117::RegSeqInfo 66 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { 68 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { 69 MachineOperand &MO = Instr->getOperand(i); 70 unsigned Chan = Instr->getOperand(i + 1).getImm(); 80 return RSI.Instr == Instr; 180 unsigned Reg = RSI->Instr->getOperand(0).getReg(); 181 MachineBasicBlock::iterator Pos = RSI->Instr; 185 unsigned SrcVec = BaseRSI->Instr [all...] |
/external/chromium_org/v8/src/mips/ |
H A D | constants-mips.h | 227 typedef int32_t Instr; typedef in namespace:v8::internal 707 extern const Instr kPopInstruction; 709 extern const Instr kPushInstruction; 711 extern const Instr kPushRegPattern; 713 extern const Instr kPopRegPattern; 714 extern const Instr kLwRegFpOffsetPattern; 715 extern const Instr kSwRegFpOffsetPattern; 716 extern const Instr kLwRegFpNegOffsetPattern; 717 extern const Instr kSwRegFpNegOffsetPattern; 719 extern const Instr kRtMas [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | BypassSlowDivision.cpp | 85 Instruction *Instr = J; local 86 Value *Dividend = Instr->getOperand(0); 87 Value *Divisor = Instr->getOperand(1); 142 PHINode *QuoPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2); 145 PHINode *RemPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2); 149 // Replace Instr with appropriate phi node 151 Instr->replaceAllUsesWith(QuoPhi); 153 Instr->replaceAllUsesWith(RemPhi); 154 Instr->eraseFromParent(); 193 Instruction *Instr local [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 307 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); local 308 assert(Instr && "Missing target independent instruction"); 309 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 310 InstrsByEnum.push_back(Instr);
|
H A D | CodeGenDAGPatterns.cpp | 2993 Record *Instr = II->first; local 2995 PatternToMatch(Instr, 2996 Instr->getValueAsListInit("Predicates"), 3000 Instr->getValueAsInt("AddedComplexity"), 3001 Instr->getID()));
|
/external/llvm/tools/llvm-stress/ |
H A D | llvm-stress.cpp | 673 Instruction *Instr = *it; local 674 BasicBlock *Curr = Instr->getParent(); 675 BasicBlock::iterator Loc= Instr; 677 Instr->moveBefore(Curr->getTerminator()); 679 BranchInst::Create(Curr, Next, Instr, Curr->getTerminator());
|
/external/chromium_org/v8/src/arm64/ |
H A D | instructions-arm64.h | 19 typedef uint32_t Instr; typedef in namespace:v8::internal 99 V8_INLINE Instr InstructionBits() const { 100 return *reinterpret_cast<const Instr*>(this); 103 V8_INLINE void SetInstructionBits(Instr new_instr) { 104 *reinterpret_cast<Instr*>(this) = new_instr; 120 Instr Mask(uint32_t mask) const { 410 const Instr kImmExceptionIsRedirectedCall = 0xca11; 414 const Instr kImmExceptionIsUnreachable = 0xdebf; 418 const Instr kImmExceptionIsPrintf = 0xdeb1; 453 const Instr kImmExceptionIsDebu [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 260 MachineInstr *Instr; // Alternatively, a MachineInstr. variable 320 : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr), 336 : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr), 351 : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr), 376 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 383 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 389 bool isInstr() const { return Instr; } 395 Instr = MI; 402 return Instr;
|
/external/llvm/lib/Analysis/IPA/ |
H A D | InlineCost.cpp | 1043 Instruction *Instr = CS.getInstruction(); local 1044 if (InvokeInst *II = dyn_cast<InvokeInst>(Instr)) { 1047 } else if (isa<UnreachableInst>(++BasicBlock::iterator(Instr)))
|
/external/vixl/src/a64/ |
H A D | instructions-a64.h | 37 typedef uint32_t Instr; typedef in namespace:vixl 156 inline Instr InstructionBits() const { 157 return *(reinterpret_cast<const Instr*>(this)); 160 inline void SetInstructionBits(Instr new_instr) { 161 *(reinterpret_cast<Instr*>(this)) = new_instr; 177 inline Instr Mask(uint32_t mask) const {
|
/external/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 1034 const MCCFIInstruction &Instr); 1085 const MCCFIInstruction &Instr) { 1089 switch (Instr.getOperation()) { 1091 unsigned Reg1 = Instr.getRegister(); 1092 unsigned Reg2 = Instr.getRegister2(); 1108 unsigned Reg = Instr.getRegister(); 1120 Instr.getOperation() == MCCFIInstruction::OpAdjustCfaOffset; 1127 CFAOffset += Instr.getOffset(); 1129 CFAOffset = -Instr.getOffset(); 1143 Streamer.AddComment(Twine("Reg ") + Twine(Instr 1084 EmitCFIInstruction(MCObjectStreamer &Streamer, const MCCFIInstruction &Instr) argument 1240 const MCCFIInstruction &Instr = Instrs[i]; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 1432 const MachineInstr &Instr = *I; local 1433 unsigned IOpC = Instr.getOpcode(); 1436 Instr.modifiesRegister(PPC::CR0, TRI) || 1437 Instr.readsRegister(PPC::CR0, TRI))) 1449 ((Instr.getOperand(1).getReg() == SrcReg && 1450 Instr.getOperand(2).getReg() == SrcReg2) || 1451 (Instr.getOperand(1).getReg() == SrcReg2 && 1452 Instr.getOperand(2).getReg() == SrcReg))) {
|
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAddSub.cpp | 159 FAddCombine(InstCombiner::BuilderTy *B) : Builder(B), Instr(nullptr) {} 183 Instruction *Instr; member in class:__anon26243::FAddCombine 461 // Input Instr I Factor AddSub0 AddSub1 528 Instr = I; 689 Result = ConstantFP::get(Instr->getType(), 0.0); 794 NewInstr->setDebugLoc(Instr->getDebugLoc()); 801 NewInstr->setFastMathFlags(Instr->getFastMathFlags()); 849 return Coeff.getValue(Instr->getType()); 865 return createFMul(OpndVal, Coeff.getValue(Instr->getType()));
|
/external/chromium_org/v8/src/arm/ |
H A D | constants-arm.h | 55 // General constants are in an anonymous enum in class Instr. 120 // Instr is merely used by the Assembler to distinguish 32bit integers 124 typedef int32_t Instr; typedef in namespace:v8::internal 413 // Note that the Assembler uses typedef int32_t Instr. 435 static inline return_type Name(Instr instr) { \ 443 inline Instr InstructionBits() const { 444 return *reinterpret_cast<const Instr*>(this); 448 inline void SetInstructionBits(Instr value) { 449 *reinterpret_cast<Instr*>(this) = value; 470 static inline int Bit(Instr inst [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 3688 MachineInstr *Instr = &*RI; local 3691 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3692 Sub = Instr; 3696 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3697 Instr->readsRegister(X86::EFLAGS, TRI)) { 3703 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 && 3704 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3705 Movr0Inst = Instr; 3729 const MachineInstr &Instr = *I; local 3730 bool ModifyEFLAGS = Instr 3835 MachineInstr *Instr = &*InsertI; local [all...] |