/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { argument 65 MipsFI = MF.getInfo<MipsFunctionInfo>(); 77 MCP = MF.getConstantPool(); 81 NaClAlignIndirectJumpTargets(MF); 83 AsmPrinter::runOnMachineFunction(MF); 251 const MachineFrameInfo *MFI = MF->getFrameInfo(); 309 unsigned stackReg = RI.getFrameRegister(*MF); 311 unsigned stackSize = MF->getFrameInfo()->getStackSize(); 333 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); 354 MCInstLowering.Initialize(&MF 992 NaClAlignIndirectJumpTargets(MachineFunction &MF) argument [all...] |
H A D | MipsConstantIslandPass.cpp | 350 MachineFunction *MF; member in class:__anon26048::MipsConstantIslands 371 STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr), 451 MF = &mf; 458 TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo(); 459 MFI = MF->getInfo<MipsFunctionInfo>(); 469 MF->getRegInfo().invalidateLiveness(); 473 MF->RenumberBlocks(); 540 MachineBasicBlock *BB = MF->CreateMachineBasicBlock(); 541 MF->push_back(BB); 553 MF [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 211 MachineFunction *MF = Entry->getParent(); local 222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 256 MachineFunction *MF = MI->getParent()->getParent(); local 257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 268 I = MF->getRegInfo().livein_begin(), 269 E = MF->getRegInfo().livein_end(); I != E; ++I) { 276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF 338 spillsCR(const MachineFunction &MF) argument 343 spillsVRSAVE(const MachineFunction &MF) argument 348 hasSpills(const MachineFunction &MF) argument 353 hasNonRISpills(const MachineFunction &MF) argument 360 determineFrameLayout(MachineFunction &MF, bool UpdateMF, bool UseEstimate) const argument 810 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const argument 1042 MustSaveLR(const MachineFunction &MF, unsigned LR) argument 1054 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *) const argument 1109 processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const argument 1319 addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const argument 1431 MachineFunction *MF = MBB.getParent(); local 1463 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument [all...] |
H A D | PPCISelDAGToDAG.cpp | 65 bool runOnMachineFunction(MachineFunction &MF) override { 70 SelectionDAGISel::runOnMachineFunction(MF); 73 InsertVRSaveCode(MF); variable 181 void InsertVRSaveCode(MachineFunction &MF); 273 MachineBasicBlock &FirstMBB = MF->front();
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 53 MachineFunction &MF = *MBB->getParent(); local 57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); 84 MachineFunction &MF = *MBB->getParent(); local 85 MachineFrameInfo *MFFrame = MF.getFrameInfo(); 747 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, argument 751 const MachineFrameInfo *MFI = MF.getFrameInfo(); 760 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::AGSI)) 772 assert(Size == MF.getRegInfo() 781 return BuildMI(MF, MI->getDebugLoc(), get(Opcode)) 793 return BuildMI(MF, M 865 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr* LoadMI) const argument 1033 const MachineFunction *MF = MI->getParent()->getParent(); local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILPeepholeOptimizer.cpp | 274 AMDGPUPeepholeOpt::runOnFunction(Function &MF) argument 277 mF = &MF; 280 MF.dump(); 282 mCTX = &MF.getType()->getContext(); 284 safeNestedForEach(MF.begin(), MF.end(), MF.begin()->begin(), 288 doAtomicConversionIfNeeded(MF); 292 MF.dump();
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/external/clang/lib/Sema/ |
H A D | SemaExprMember.cpp | 1371 ObjCMethodFamily MF = MD->getMethodFamily(); local 1372 warn = (MF != OMF_init && MF != OMF_dealloc && 1373 MF != OMF_finalize &&
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/external/llvm/examples/Kaleidoscope/MCJIT/cached/ |
H A D | toy.cpp | 871 Function *MF = (*it)->getFunction(FnName); local 872 if (MF == F) {
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/external/llvm/examples/Kaleidoscope/MCJIT/complete/ |
H A D | toy.cpp | 1101 Function *MF = (*it)->getFunction(FnName); local 1102 if (MF == F) {
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/external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
H A D | toy.cpp | 782 Function *MF = (*it)->getFunction(FnName); local 783 if (MF == F) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineScheduler.h | 103 MachineFunction *MF; member in struct:llvm::MachineSchedContext 253 : ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, IsPostRA,
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/external/llvm/include/llvm/Support/ |
H A D | CommandLine.h | 1044 static void opt(MiscFlags MF, Option &O) { O.setMiscFlag(MF); } argument
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/external/llvm/lib/CodeGen/ |
H A D | IfConversion.cpp | 184 bool runOnMachineFunction(MachineFunction &MF) override; 200 void AnalyzeBlocks(MachineFunction &MF, std::vector<IfcvtToken*> &Tokens); 271 bool IfConverter::runOnMachineFunction(MachineFunction &MF) { argument 272 TLI = MF.getTarget().getTargetLowering(); 273 TII = MF.getTarget().getInstrInfo(); 274 TRI = MF.getTarget().getRegisterInfo(); 276 MRI = &MF.getRegInfo(); 279 MF.getTarget().getSubtarget<TargetSubtargetInfo>(); 290 BFChange = BF.OptimizeFunction(MF, TII, 291 MF 910 AnalyzeBlocks(MachineFunction &MF, std::vector<IfcvtToken*> &Tokens) argument 1573 MachineFunction &MF = *ToBBI.BB->getParent(); local [all...] |
H A D | MachineInstr.cpp | 56 if (MachineFunction *MF = MBB->getParent()) { 57 MachineRegisterInfo &MRI = MF->getRegInfo(); 98 if (MachineFunction *MF = MBB->getParent()) { 99 MachineRegisterInfo &MRI = MF->getRegInfo(); 118 if (MachineFunction *MF = MBB->getParent()) 119 MF->getRegInfo().removeRegOperandFromUseList(this); 134 if (MachineFunction *MF = MBB->getParent()) 135 RegInfo = &MF->getRegInfo(); 266 if (const MachineFunction *MF = MBB->getParent()) 267 TM = &MF 537 addImplicitDefUseOperands(MachineFunction &MF) argument 549 MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, const DebugLoc dl, bool NoImp) argument 567 MachineInstr(MachineFunction &MF, const MachineInstr &MI) argument 613 MachineFunction *MF = MBB->getParent(); local 639 addOperand(MachineFunction &MF, const MachineOperand &Op) argument 761 addMemOperand(MachineFunction &MF, MachineMemOperand *MO) argument 1437 copyImplicitOps(MachineFunction &MF, const MachineInstr *MI) argument 1453 printDebugLoc(DebugLoc DL, const MachineFunction *MF, raw_ostream &CommentOS) argument 1462 const MachineFunction *MF = nullptr; local [all...] |
H A D | MachineVerifier.cpp | 60 bool runOnMachineFunction(MachineFunction &MF); 66 const MachineFunction *MF; member in struct:__anon25778::MachineVerifier 100 // Is this MBB reachable from the MF entry point? 208 void report(const char *msg, const MachineFunction *MF); 212 void report(const char *msg, const MachineFunction *MF, 216 void report(const char *msg, const MachineFunction *MF, 254 bool runOnMachineFunction(MachineFunction &MF) override { 255 MF.verify(this, Banner); 275 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { argument 293 this->MF 378 report(const char *msg, const MachineFunction *MF) argument 420 report(const char *msg, const MachineFunction *MF, const LiveInterval &LI) argument 438 report(const char *msg, const MachineFunction *MF, const LiveRange &LR) argument [all...] |
H A D | RegAllocGreedy.cpp | 108 MachineFunction *MF; member in class:__anon25792::RAGreedy 1287 MF->verify(this, "After splitting live range around region"); 1406 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 1454 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 1484 MF->verify(this, "After splitting live range around basic blocks"); 1526 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 1846 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 2153 LLVMContext &Ctx = MF->getFunction()->getContext(); 2305 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this); 2310 MF [all...] |
H A D | RegisterCoalescer.cpp | 79 MachineFunction* MF; member in class:__anon25794::RegisterCoalescer 400 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS, 778 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); 1171 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); 2174 MBBs.reserve(MF->size()); 2175 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){ 2208 MF = &fn; 2229 << "********** Function: " << MF->getName() << '\n'); 2232 MF [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 281 const MachineFunction &MF) { 292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 1624 MachineFunction &MF; 1651 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) { 1660 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF); 1956 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); 2070 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); 2085 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); 2985 new BURegReductionPriorityQueue(*IS->MF, fals 276 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 258 MachineFunction *MF; member in class:__anon25967::ARMConstantIslands 270 bool runOnMachineFunction(MachineFunction &MF) override; 332 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end(); 351 DEBUG(MF->dump()); 378 MF = &mf; 385 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo(); 386 AFI = MF->getInfo<ARMFunctionInfo>(); 387 STI = &MF->getTarget().getSubtarget<ARMSubtarget>(); 396 MF [all...] |
H A D | ARMFrameLowering.cpp | 49 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 50 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 56 const MachineFrameInfo *MFI = MF.getFrameInfo(); 58 return ((MF.getTarget().Options.DisableFramePointerElim(MF) && 60 RegInfo->needsStackRealignment(MF) || 70 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 71 const MachineFrameInfo *FFI = MF.getFrameInfo(); 80 return !MF.getFrameInfo()->hasVarSizedObjects(); 88 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) cons 149 WindowsRequiresStackProbe(const MachineFunction &MF, size_t StackSizeInBytes) argument 569 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const argument 710 getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const argument 716 ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const argument 791 getFrameIndexOffset(const MachineFunction &MF, int FI) const argument 805 MachineFunction &MF = *MBB.getParent(); local 878 MachineFunction &MF = *MBB.getParent(); local 966 MachineFunction &MF = *MBB.getParent(); local 1125 MachineFunction &MF = *MBB.getParent(); local 1261 GetFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII) argument 1275 estimateRSStackSizeLimit(MachineFunction &MF, const TargetFrameLowering *TFI) argument 1328 checkNumAlignedDPRCS2Regs(MachineFunction &MF) argument 1375 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const argument 1628 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1771 MachineFunction *MF; member in struct:__anon25981::ARMPreAllocLoadStoreOpt 1801 MF = &Fn; 1865 MachineFunction *MF = MI->getParent()->getParent(); local 1866 MachineSDNode::mmo_iterator MemBegin = MF->allocateMemRefsArray(numMemRefs); 1913 const Function *Func = MF->getFunction(); 2050 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 81 bool runOnMachineFunction(MachineFunction &MF) override; 296 bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) { argument 302 MRI = &MF.getRegInfo(); 304 TM = static_cast<const HexagonTargetMachine*>(&MF.getTarget()); 1420 MachineFunction *MF = Header->getParent(); local 1447 MachineBasicBlock *NewPH = MF->CreateMachineBasicBlock(); 1448 MF->insert(Header, NewPH); 1461 MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
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H A D | HexagonISelLowering.cpp | 53 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, argument 56 : CCState(CC, isVarArg, MF, TM, locs, C), 691 MachineFunction &MF = DAG.getMachineFunction(); local 693 MF.getInfo<HexagonMachineFunctionInfo>(); 754 MachineFunction &MF = DAG.getMachineFunction(); local 755 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 837 MachineFunction &MF = DAG.getMachineFunction(); local 838 MachineFrameInfo *MFI = MF.getFrameInfo(); 839 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 841 MF 941 MachineFunction &MF = DAG.getMachineFunction(); local 968 MachineFunction &MF = DAG.getMachineFunction(); local 1581 MachineFunction *MF = BB->getParent(); local [all...] |
H A D | HexagonInstrInfo.cpp | 479 MachineFunction &MF = *MBB.getParent(); local 480 MachineFrameInfo &MFI = *MF.getFrameInfo(); 484 MF.getMachineMemOperand( 509 MachineFunction &MF, unsigned SrcReg, 525 MachineFunction &MF = *MBB.getParent(); local 526 MachineFrameInfo &MFI = *MF.getFrameInfo(); 530 MF.getMachineMemOperand( 550 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, argument 558 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, argument 566 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MV argument 508 storeRegToAddr( MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 153 !AP.MF ? nullptr : AP.MF->getFunction()->getParent()); 168 !AP.MF ? nullptr : AP.MF->getFunction()->getParent()); 286 const MachineFunction *MF = MI.getParent()->getParent(); local 287 //const TargetMachine &TM = MF->getTarget(); 289 const LLVMContext &ctx = MF->getFunction()->getContext(); 584 TargetMachine &TM = const_cast<TargetMachine&>(MF->getTarget()); 586 const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>(); 775 void NVPTXAsmPrinter::printReturnValStr(const MachineFunction &MF, argument 1963 emitFunctionParamList(const MachineFunction &MF, raw_ostream &O) argument 1969 setAndEmitFunctionVirtualRegisters( const MachineFunction &MF) argument [all...] |