/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, 190 assert(Offset2 > Offset1 195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); 187 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 231 int64_t Offset1, Offset2; local 232 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 233 Offset1 == Offset2) 237 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 238 Offsets.push_back(Offset1); 241 if (Offset2 < Offset1)
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H A D | SelectionDAG.cpp | 4609 // If this is (FI+Offset1)+Offset2, we can model it. 6508 int64_t Offset1 = 0; local 6511 bool isGA1 = TLI->isGAPlusOffset(Loc.getNode(), GV1, Offset1); 6514 return Offset1 == (Offset2 + Dist*Bytes);
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H A D | DAGCombiner.cpp | 7773 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); local 7784 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; 7785 else CNV = CNV - Offset1; 11499 int64_t Offset1, Offset2; local 11503 Base1, Offset1, GV1, CV1); 11509 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || 11510 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); 11518 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 11520 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || 11521 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, 190 assert(Offset2 > Offset1 195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); 187 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 219 int64_t Offset1, int64_t Offset2, 221 assert(Offset2 > Offset1 226 return (NumLoads < 16 && (Offset2 - Offset1) < 16); 218 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 635 int64_t &Offset1, int64_t &Offset2) const { 648 int64_t Offset1, int64_t Offset2, 634 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 647 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/lib/Transforms/Scalar/ |
H A D | MemCpyOptimizer.cpp | 117 int64_t Offset1 = GetOffsetFromIndex(GEP1, Idx, VariableIdxFound, TD); local 121 Offset = Offset2-Offset1;
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 4831 int64_t &Offset1, int64_t &Offset2) const { 4927 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4936 int64_t Offset1, int64_t Offset2, 4938 assert(Offset2 > Offset1); 4939 if ((Offset2 - Offset1) / 8 > 64) 4830 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 4935 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1429 int64_t &Offset1, 1490 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1510 int64_t Offset1, int64_t Offset2, 1515 assert(Offset2 > Offset1); 1517 if ((Offset2 - Offset1) / 8 > 64) 1428 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 1509 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 7300 int64_t Offset1 = 0; local 7302 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); 7305 return Offset1 == (Offset2 + Dist*Bytes);
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