Searched defs:Opc (Results 1 - 25 of 112) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMips16ISelDAGToDAG.cpp46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, argument
49 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
259 unsigned Opc = InFlag.getOpcode(); (void)Opc; local
260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
261 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
H A DMipsInstrInfo.cpp71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, argument
74 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
80 Cond.push_back(MachineOperand::CreateImm(Opc));
101 unsigned Opc = Cond[0].getImm(); local
102 const MCInstrDesc &MCID = get(Opc);
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h208 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } argument
210 static inline bool isCondBranchOpcode(int Opc) { argument
211 switch (Opc) {
227 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } argument
H A DAArch64AdvSIMDScalarPass.cpp160 static int getTransformOpcode(unsigned Opc) { argument
161 switch (Opc) {
171 return Opc;
175 int Opc = MI->getOpcode(); local
176 return Opc != getTransformOpcode(Opc);
H A DAArch64BranchRelaxation.cpp274 static bool isConditionalBranch(unsigned Opc) { argument
275 switch (Opc) {
309 static unsigned getOppositeConditionOpcode(unsigned Opc) { argument
310 switch (Opc) {
325 static unsigned getBranchDisplacementBits(unsigned Opc) { argument
326 switch (Opc) {
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
348 bool isUncondBranchOpcode(int Opc) { argument
349 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
353 bool isCondBranchOpcode(int Opc) { argument
354 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
358 isJumpTableBranchOpcode(int Opc) argument
364 isIndirectBranchOpcode(int Opc) argument
368 isPopOpcode(int Opc) argument
374 isPushOpcode(int Opc) argument
[all...]
H A DARMInstrInfo.cpp53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54 switch (Opc) {
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? variable
129 TII.get(Opc), TempReg)
131 if (Opc == ARM::LDRcp)
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
142 if (Opc == ARM::PICADD)
H A DThumb1FrameLowering.cpp73 unsigned Opc = Old->getOpcode(); local
74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
H A DThumb1RegisterInfo.cpp127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); local
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130 if (Opc != ARM::tADDhirr)
141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, argument
146 if (Opc == ARM::tADDrSPi) {
180 int Opc = 0;
188 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
201 Opc = ARM::tADDrSPi;
210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
215 Opc
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp85 int Opc = MI->getOpcode(); local
86 if (Opc == Hexagon::STriw_pred) {
130 } else if (Opc == Hexagon::LDriw_pred) {
H A DHexagonSplitConst32AndConst64.cpp87 int Opc = MI->getOpcode(); local
88 if (Opc == Hexagon::CONST32_set) {
101 else if (Opc == Hexagon::CONST32_set_jt) {
114 else if (Opc == Hexagon::CONST32_Label) {
127 else if (Opc == Hexagon::CONST32_Int_Real) {
138 else if (Opc == Hexagon::CONST64_Int_Real) {
H A DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { argument
62 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
63 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
67 static bool IsUnconditionalJump(int Opc) { argument
68 return (Opc == Hexagon::JMP);
114 int Opc = MI->getOpcode(); local
115 if (IsConditionalBranch(Opc)) {
/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp142 unsigned Opc = PI->getOpcode(); local
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
H A DMSP430InstrInfo.cpp95 unsigned Opc; local
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
H A DMSP430ISelDAGToDAG.cpp366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); local
371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp108 unsigned Opc = MBBI->getOpcode(); local
109 switch (Opc) {
155 unsigned Opc;
157 Opc = getLEArOpcode(IsLP64);
159 Opc = isSub
174 Opc = isSub
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
212 unsigned Opc
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp180 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, argument
H A DAMDILISelDAGToDAG.cpp155 unsigned int Opc = N->getOpcode(); local
159 switch (Opc) {
/external/llvm/include/llvm/Analysis/
H A DTargetFolder.h109 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
111 return Fold(ConstantExpr::get(Opc, LHS, RHS));
/external/llvm/include/llvm/IR/
H A DConstantFolder.h97 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
99 return ConstantExpr::get(Opc, LHS, RHS);
/external/llvm/lib/MC/
H A DMCExpr.cpp137 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS, argument
139 return new (Ctx) MCBinaryExpr(Opc, LHS, RHS);
142 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr, argument
144 return new (Ctx) MCUnaryExpr(Opc, Expr);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, argument
410 bool isSub = Opc == sub;
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
493 bool isSub = Opc == sub;
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp590 unsigned Opc = I->getOpcode(); local
591 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
652 unsigned Opc = MII->getOpcode(); local
653 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
654 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
/external/llvm/lib/Target/Sparc/
H A DSparcCodeEmitter.cpp235 unsigned Opc = MI.getOpcode(); local
236 switch (Opc) {

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