Searched defs:PC (Results 1 - 3 of 3) sorted by relevance
/art/runtime/arch/arm/ |
H A D | registers_arm.h | 48 PC = 15, enumerator in enum:art::arm::Register
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/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 93 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. 99 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. 500 EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); 553 if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) { 554 // PC relative LDR(literal) 666 CHECK_NE(rd, PC); 667 CHECK_NE(rm, PC); 766 CHECK_NE(rt, PC); 781 CHECK_NE(rt, PC); 798 CHECK_NE(rt, PC); 891 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local 918 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local [all...] |
H A D | assembler_thumb2.cc | 95 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. 101 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. 591 EmitDataProcessing(AL, TST, 1, PC, R0, ShifterOperand(0)); 746 case TST: thumb_opcode = 0b0000; set_cc = true; rd = PC; break; 747 case TEQ: thumb_opcode = 0b0100; set_cc = true; rd = PC; break; 748 case CMP: thumb_opcode = 0b1101; set_cc = true; rd = PC; break; 749 case CMN: thumb_opcode = 0b1000; set_cc = true; rd = PC; break; 751 case MOV: thumb_opcode = 0b0010; rn = PC; break; 753 case MVN: thumb_opcode = 0b0011; rn = PC; break; 1216 offset -= 4; // Account for PC offse 1776 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local 1803 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local [all...] |
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