| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 41 struct RegOp { struct in struct:llvm::X86Operand
60 struct RegOp Reg;
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| /external/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 298 unsigned RegOp = IsStore ? 0 : 5; local
300 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
310 unsigned Reg = Inst.getOperand(RegOp).getReg();
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| H A D | X86InstrInfo.cpp | 69 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // Do not insert the forward map (RegOp -> MemOp) into the table.
82 // Used for RegOp->MemOp conversion.
93 uint16_t RegOp; member in struct:X86OpTblEntry
275 unsigned RegOp = OpTbl2Addr[i].RegOp; local
279 RegOp, MemOp,
384 unsigned RegOp = OpTbl0[i].RegOp; local
388 RegOp, MemO
619 unsigned RegOp = OpTbl1[i].RegOp; local
1274 unsigned RegOp = OpTbl2[i].RegOp; local
1436 unsigned RegOp = OpTbl3[i].RegOp; local
1448 AddTableEntry(RegOp2MemOpTableType &R2MTable, MemOp2RegOpTableType &M2RTable, unsigned RegOp, unsigned MemOp, unsigned Flags) argument
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 328 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; local
329 if (RegOp >= MI->getNumOperands())
331 const MachineOperand &MO = MI->getOperand(RegOp);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 503 unsigned RegOp = OpNum; local
509 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
512 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
515 RegOp = OpNum + 1;
517 if (RegOp >= MI->getNumOperands())
519 const MachineOperand &MO = MI->getOperand(RegOp);
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 157 struct RegOp { struct in class:__anon26131::SparcOperand
174 struct RegOp Reg;
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 81 struct RegOp { struct in class:__anon26144::SystemZOperand
101 RegOp Reg;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 172 struct RegOp { struct in class:__anon25952::AArch64Operand
237 struct RegOp Reg;
3785 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); local
3787 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) {
3790 RegOp.getReg())
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1082 const MCOperand &RegOp = Inst.getOperand(0); local
1083 assert(RegOp.isReg() && "expected register operand kind");
1093 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1101 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1111 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1114 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1136 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1140 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1141 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1163 tmpInst.addOperand(MCOperand::CreateReg(RegOp
1224 const MCOperand &RegOp = Inst.getOperand(0); local
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 443 struct RegOp { struct in class:__anon25988::ARMOperand
521 struct RegOp Reg;
4390 unsigned RegOp = 4; local
4394 RegOp = 5;
4395 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
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