/external/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 52 const unsigned *Regs) { 54 RegNo = Regs[RegNo]; 190 const unsigned *Regs) { 194 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 200 const unsigned *Regs) { 204 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 210 const unsigned *Regs) { 215 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 217 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); 222 const unsigned *Regs) { 51 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs) argument [all...] |
/external/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 173 const unsigned (&Regs)[N]) { 175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); 172 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned (&Regs)[N]) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 180 void setUsed(BitVector &Regs) { argument 181 RegsAvailable.reset(Regs); 183 void setUnused(BitVector &Regs) { argument 184 RegsAvailable |= Regs;
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H A D | CallingConvLower.h | 300 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const { argument 302 if (!isAllocated(Regs[i])) 327 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) { argument 328 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 333 unsigned Reg = Regs[FirstUnalloc]; 341 unsigned AllocateRegBlock(const uint16_t *Regs, unsigned NumRegs, unsigned RegsRequired) { argument 346 if (isAllocated(Regs[StartIdx + BlockIdx])) { 354 MarkAllocated(Regs[StartIdx + BlockIdx]); 356 return Regs[StartIdx]; 364 unsigned AllocateReg(const MCPhysReg *Regs, cons argument [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 114 // \brief Collect all registers clobbered by @MI and insert them to @Regs. 117 std::set<unsigned> &Regs) { 122 Regs.insert(*AI); 151 std::set<unsigned> &Regs) { 158 collectClobberedRegisters(MI, TRI, Regs); 115 collectClobberedRegisters(const MachineInstr &MI, const TargetRegisterInfo *TRI, std::set<unsigned> &Regs) argument 149 collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, std::set<unsigned> &Regs) argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 109 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument 111 if (!isAllocated(Regs[i])) 136 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument 137 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 142 unsigned Reg = Regs[FirstUnalloc]; 148 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument 150 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, 76 Regs.push_back(Reg); 548 std::vector<unsigned> Regs; 549 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 550 assert(Regs.size() > 0 && "Empty register group!"); 551 if (Regs.size() == 0) 561 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 562 unsigned Reg = Regs[i]; 581 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 582 unsigned Reg = Regs[ 69 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument [all...] |
H A D | ExecutionDepsFix.cpp | 644 SmallVector<LiveReg, 4> Regs; local 655 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); 659 Regs.insert(i, LR); 663 Regs.push_back(LR); 669 while (!Regs.empty()) { 671 dv = Regs.pop_back_val().Value; 678 DomainValue *Latest = Regs.pop_back_val().Value;
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H A D | RegisterPressure.cpp | 423 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { argument 424 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 425 if (LiveRegs.insert(Regs[i])) 426 increaseRegPressure(Regs[i]);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 226 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local 227 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 228 if (I == Regs.end())
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H A D | RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 59 const std::vector<CodeGenRegister*> &Regs, 171 const CodeGenRegister::Set &Regs = RC.getMembers(); local 172 if (Regs.empty()) 177 OS << " {" << (*Regs.begin())->getWeight(RegBank) 315 const std::vector<CodeGenRegister*> &Regs, 323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 324 Record *Reg = Regs[i]->TheDef; 342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 390 for (unsigned i = 0, e = Regs 314 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 440 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 708 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1215 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1307 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local [all...] |
H A D | CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs): argument 160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 941 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local 942 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); 943 Registers.reserve(Regs.size()); 945 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 946 getReg(Regs[i]); 1232 CodeGenRegister::Set Regs; member in struct:__anon26577::UberRegSet 1263 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local 1964 computeCoveredRegisters(ArrayRef<Record*> Regs) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 601 /// Regs - This list holds the registers assigned to the values. 605 SmallVector<unsigned, 4> Regs; member in struct:__anon25816::RegsForValue 611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 622 Regs.push_back(Reg + i); 632 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 691 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 700 if (!TargetRegisterInfo::isVirtualRegister(Regs[Par [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 831 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { argument 837 return createTuple(Regs, RegClassIDs, SubRegs); 840 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { argument 846 return createTuple(Regs, RegClassIDs, SubRegs); 849 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, argument 854 if (Regs.size() == 1) 855 return Regs[0]; 857 assert(Regs.size() >= 2 && Regs.size() <= 4); 859 SDLoc DL(Regs[ [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 811 SmallVector<std::pair<unsigned,bool>, 4> Regs; local 843 Regs.push_back(std::make_pair(Reg, isKill)); 846 if (Regs.empty()) 848 if (Regs.size() > 1 || StrOpc== 0) { 852 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 853 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 854 } else if (Regs.size() == 1) { 857 .addReg(Regs[0].first, getKillRegState(Regs[ 888 SmallVector<unsigned, 4> Regs; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 108 ArrayRef<std::pair<unsigned, bool> > Regs, 410 /// registers in Regs as the register operands that would be loaded / stored. 418 ArrayRef<std::pair<unsigned, bool> > Regs, 421 unsigned NumRegs = Regs.size(); 452 NewBase = Regs[NumRegs-1].first; 510 if (Base == Regs[I].first) { 542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 543 | getKillRegState(Regs[i].second)); 638 SmallVector<std::pair<unsigned, bool>, 8> Regs; local 646 Regs 413 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 435 SmallVector<SDValue, 4> Regs; local 436 Regs.push_back(Val); 440 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 446 Regs.push_back(DAG.getUNDEF(VT)); 448 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 317 RegisterGroup Group, const unsigned *Regs, 322 const unsigned *Regs, RegisterKind RegKind); 325 const unsigned *Regs, RegisterKind RegKind, 456 // Parse a register of group Group. If Regs is nonnull, use it to map 461 const unsigned *Regs, bool IsAddress) { 466 if (Regs && Regs[Reg.Num] == 0) 470 if (Regs) 471 Reg.Num = Regs[Re 460 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument 477 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument 495 parseAddress(unsigned &Base, const MCExpr *&Disp, unsigned &Index, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) argument 545 parseAddress(OperandVector &Operands, const unsigned *Regs, RegisterKind RegKind, MemoryKind MemKind) argument [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 895 SmallPtrSet<const SCEV *, 16> &Regs, 908 SmallPtrSet<const SCEV *, 16> &Regs, 912 SmallPtrSet<const SCEV *, 16> &Regs, 922 SmallPtrSet<const SCEV *, 16> &Regs, 944 if (!Regs.count(AR->getOperand(1))) { 945 RateRegister(AR->getOperand(1), Regs, L, SE, DT); 970 SmallPtrSet<const SCEV *, 16> &Regs, 978 if (Regs.insert(Reg)) { 979 RateRegister(Reg, Regs, L, SE, DT); 987 SmallPtrSet<const SCEV *, 16> &Regs, 921 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument 969 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 985 RateFormula(const TargetTransformInfo &TTI, const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, const LSRUse &LU, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 1253 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon26301::LSRUse 3918 SmallPtrSet<const SCEV *, 16> Regs; local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2594 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, argument 2596 assert (Regs.size() > 0 && "RegList contains no registers?"); 2599 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2602 contains(Regs.front().second)) 2606 array_pod_sort(Regs.begin(), Regs.end()); 2610 I = Regs.begin(), E = Regs.end(); I != E; ++I)
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