/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | gen6_gs_state.c | 34 upload_gs_state(struct brw_context *brw) argument 36 struct intel_context *intel = &brw->intel; 47 if (brw->gs.prog_active) { 50 OUT_BATCH(brw->gs.prog_offset); 54 (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT)); 55 OUT_BATCH(((brw->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) | 61 (brw->gs.prog_data->svbi_postincrement_value << 86 .brw = BRW_NEW_CONTEXT,
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H A D | gen6_sampler_state.c | 34 upload_sampler_state_pointers(struct brw_context *brw) argument 36 struct intel_context *intel = &brw->intel; 44 OUT_BATCH(brw->sampler.offset); /* VS */ 46 OUT_BATCH(brw->sampler.offset); 53 .brw = (BRW_NEW_BATCH |
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H A D | gen7_disable.c | 30 disable_stages(struct brw_context *brw) argument 32 struct intel_context *intel = &brw->intel; 34 assert(!brw->gs.prog_active); 130 .brw = BRW_NEW_BATCH,
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H A D | brw_gs_state.c | 39 brw_upload_gs_unit(struct brw_context *brw) argument 41 struct intel_context *intel = &brw->intel; 44 gs = brw_state_batch(brw, AUB_TRACE_GS_STATE, 45 sizeof(*gs), 32, &brw->gs.state_offset); 50 if (brw->gs.prog_active) { 51 gs->thread0.grf_reg_count = (ALIGN(brw->gs.prog_data->total_grf, 16) / 55 brw_program_reloc(brw, 56 brw->gs.state_offset + 58 brw->gs.prog_offset + 68 gs->thread3.urb_entry_read_length = brw [all...] |
H A D | brw_clip_state.c | 37 brw_upload_clip_unit(struct brw_context *brw) argument 39 struct intel_context *intel = &brw->intel; 43 clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE, 44 sizeof(*clip), 32, &brw->clip.state_offset); 48 clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) / 51 brw_program_reloc(brw, 52 brw->clip.state_offset + 54 brw->clip.prog_offset + 60 clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length; 62 brw [all...] |
H A D | brw_vs_state.c | 40 brw_upload_vs_unit(struct brw_context *brw) argument 42 struct intel_context *intel = &brw->intel; 46 vs = brw_state_batch(brw, AUB_TRACE_VS_STATE, 47 sizeof(*vs), 32, &brw->vs.state_offset); 51 vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1; 53 brw_program_reloc(brw, 54 brw->vs.state_offset + 56 brw->vs.prog_offset + 76 if (brw->vs.prog_data->total_scratch != 0) { 78 brw [all...] |
H A D | gen6_depthstencil.c | 33 gen6_upload_depth_stencil_state(struct brw_context *brw) argument 35 struct gl_context *ctx = &brw->intel.ctx; 42 ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, 44 &brw->cc.depth_stencil_state_offset); 91 brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE; 97 .brw = BRW_NEW_BATCH,
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H A D | gen7_vs_state.c | 33 upload_vs_state(struct brw_context *brw) argument 35 struct intel_context *intel = &brw->intel; 37 const int max_threads_shift = brw->intel.is_haswell ? 45 OUT_BATCH(brw->vs.bind_bo_offset); 51 OUT_BATCH(brw->sampler.offset); 54 if (brw->vs.push_const_size == 0) { 68 OUT_BATCH(brw->vs.push_const_size); 73 OUT_BATCH(brw->vs.push_const_offset); 88 OUT_BATCH(brw->vs.prog_offset); 90 ((ALIGN(brw [all...] |
H A D | gen6_clip_state.c | 35 upload_clip_state(struct brw_context *brw) argument 37 struct intel_context *intel = &brw->intel; 44 if (brw->wm.prog_data->barycentric_interp_modes & 89 .brw = (BRW_NEW_CONTEXT),
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H A D | gen6_scissor_state.c | 35 gen6_upload_scissor_state(struct brw_context *brw) argument 37 struct intel_context *intel = &brw->intel; 43 scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE, 91 .brw = BRW_NEW_BATCH,
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H A D | gen7_cc_state.c | 32 upload_cc_state_pointers(struct brw_context *brw) argument 34 struct intel_context *intel = &brw->intel; 38 OUT_BATCH(brw->cc.state_offset | 1); 45 .brw = BRW_NEW_BATCH, 52 upload_blend_state_pointer(struct brw_context *brw) argument 54 struct intel_context *intel = &brw->intel; 58 OUT_BATCH(brw->cc.blend_state_offset | 1); 65 .brw = BRW_NEW_BATCH, 72 upload_depth_stencil_state_pointer(struct brw_context *brw) argument 74 struct intel_context *intel = &brw [all...] |
H A D | brw_clip_line.c | 48 struct intel_context *intel = &c->func.brw->intel; 129 struct brw_context *brw = p->brw; local 153 if (brw->has_negative_rhw_bug) { 190 if (brw->has_negative_rhw_bug) { 215 if (brw->has_negative_rhw_bug) { 230 if (brw->has_negative_rhw_bug) {
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H A D | brw_primitive_restart.c | 81 struct brw_context *brw = brw_context(ctx); local 83 if (brw->sol.counting_primitives_generated || 84 brw->sol.counting_primitives_written) { 135 struct brw_context *brw = brw_context(ctx); local 153 if (brw->prim_restart.in_progress) { 167 brw->prim_restart.in_progress = true; 172 brw->prim_restart.enable_cut_index = true; 174 brw->prim_restart.enable_cut_index = false; 182 brw->prim_restart.in_progress = false; 189 haswell_upload_cut_index(struct brw_context *brw) argument [all...] |
H A D | brw_sf.c | 50 static void compile_sf_prog( struct brw_context *brw, argument 53 struct intel_context *intel = &brw->intel; 65 brw_init_compile(brw, &c.func, mem_ctx); 68 c.vue_map = brw->vs.prog_data->vue_map; 125 brw_upload_cache(&brw->cache, BRW_SF_PROG, 129 &brw->sf.prog_offset, &brw->sf.prog_data); 136 brw_upload_sf_prog(struct brw_context *brw) argument 138 struct gl_context *ctx = &brw->intel.ctx; 148 key.attrs = brw [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | gen6_gs_state.c | 34 upload_gs_state(struct brw_context *brw) argument 36 struct intel_context *intel = &brw->intel; 47 if (brw->gs.prog_active) { 50 OUT_BATCH(brw->gs.prog_offset); 54 (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT)); 55 OUT_BATCH(((brw->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) | 61 (brw->gs.prog_data->svbi_postincrement_value << 86 .brw = BRW_NEW_CONTEXT,
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H A D | gen6_sampler_state.c | 34 upload_sampler_state_pointers(struct brw_context *brw) argument 36 struct intel_context *intel = &brw->intel; 44 OUT_BATCH(brw->sampler.offset); /* VS */ 46 OUT_BATCH(brw->sampler.offset); 53 .brw = (BRW_NEW_BATCH |
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H A D | gen7_disable.c | 30 disable_stages(struct brw_context *brw) argument 32 struct intel_context *intel = &brw->intel; 34 assert(!brw->gs.prog_active); 130 .brw = BRW_NEW_BATCH,
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H A D | brw_gs_state.c | 39 brw_upload_gs_unit(struct brw_context *brw) argument 41 struct intel_context *intel = &brw->intel; 44 gs = brw_state_batch(brw, AUB_TRACE_GS_STATE, 45 sizeof(*gs), 32, &brw->gs.state_offset); 50 if (brw->gs.prog_active) { 51 gs->thread0.grf_reg_count = (ALIGN(brw->gs.prog_data->total_grf, 16) / 55 brw_program_reloc(brw, 56 brw->gs.state_offset + 58 brw->gs.prog_offset + 68 gs->thread3.urb_entry_read_length = brw [all...] |
H A D | brw_clip_state.c | 37 brw_upload_clip_unit(struct brw_context *brw) argument 39 struct intel_context *intel = &brw->intel; 43 clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE, 44 sizeof(*clip), 32, &brw->clip.state_offset); 48 clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) / 51 brw_program_reloc(brw, 52 brw->clip.state_offset + 54 brw->clip.prog_offset + 60 clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length; 62 brw [all...] |
H A D | brw_vs_state.c | 40 brw_upload_vs_unit(struct brw_context *brw) argument 42 struct intel_context *intel = &brw->intel; 46 vs = brw_state_batch(brw, AUB_TRACE_VS_STATE, 47 sizeof(*vs), 32, &brw->vs.state_offset); 51 vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1; 53 brw_program_reloc(brw, 54 brw->vs.state_offset + 56 brw->vs.prog_offset + 76 if (brw->vs.prog_data->total_scratch != 0) { 78 brw [all...] |
H A D | gen6_depthstencil.c | 33 gen6_upload_depth_stencil_state(struct brw_context *brw) argument 35 struct gl_context *ctx = &brw->intel.ctx; 42 ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, 44 &brw->cc.depth_stencil_state_offset); 91 brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE; 97 .brw = BRW_NEW_BATCH,
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H A D | gen7_vs_state.c | 33 upload_vs_state(struct brw_context *brw) argument 35 struct intel_context *intel = &brw->intel; 37 const int max_threads_shift = brw->intel.is_haswell ? 45 OUT_BATCH(brw->vs.bind_bo_offset); 51 OUT_BATCH(brw->sampler.offset); 54 if (brw->vs.push_const_size == 0) { 68 OUT_BATCH(brw->vs.push_const_size); 73 OUT_BATCH(brw->vs.push_const_offset); 88 OUT_BATCH(brw->vs.prog_offset); 90 ((ALIGN(brw [all...] |
H A D | gen6_clip_state.c | 35 upload_clip_state(struct brw_context *brw) argument 37 struct intel_context *intel = &brw->intel; 44 if (brw->wm.prog_data->barycentric_interp_modes & 89 .brw = (BRW_NEW_CONTEXT),
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H A D | gen6_scissor_state.c | 35 gen6_upload_scissor_state(struct brw_context *brw) argument 37 struct intel_context *intel = &brw->intel; 43 scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE, 91 .brw = BRW_NEW_BATCH,
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H A D | gen7_cc_state.c | 32 upload_cc_state_pointers(struct brw_context *brw) argument 34 struct intel_context *intel = &brw->intel; 38 OUT_BATCH(brw->cc.state_offset | 1); 45 .brw = BRW_NEW_BATCH, 52 upload_blend_state_pointer(struct brw_context *brw) argument 54 struct intel_context *intel = &brw->intel; 58 OUT_BATCH(brw->cc.blend_state_offset | 1); 65 .brw = BRW_NEW_BATCH, 72 upload_depth_stencil_state_pointer(struct brw_context *brw) argument 74 struct intel_context *intel = &brw [all...] |