/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64_test.cc | 265 ssize_t displacement = static_cast<ssize_t>(frame_size) - (spill_regs.size() * 8 + 8); local 266 str << "subq $" << displacement << ", %rsp\n"; local 295 ssize_t displacement = static_cast<ssize_t>(frame_size) - spill_regs.size() * 8 - 8; local 296 str << "addq $" << displacement << ", %rsp\n"; local
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/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 455 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 458 * Load value from base + displacement. Optionally perform null check 469 bool short_form = IS_SIMM16(displacement); 486 short_form = IS_SIMM16_2WORD(displacement); 487 DCHECK_EQ((displacement & 0x3), 0); 497 DCHECK_EQ((displacement & 0x3), 0); 501 DCHECK_EQ((displacement & 0x1), 0); 505 DCHECK_EQ((displacement & 0x1), 0); 519 load = res = NewLIR3(opcode, r_dest.GetReg(), displacement, r_base.GetReg()); 521 load = res = NewLIR3(opcode, r_dest.GetLowReg(), displacement 552 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 574 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 655 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
H A D | target_mips.cc | 495 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { argument 501 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement); 509 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { argument 515 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement);
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/art/compiler/dex/quick/x86/ |
H A D | call_x86.cc | 27 * The sparse table in the literal pool is an array of <key,displacement> 112 // Load the displacement from the switch table 116 // Add displacement to start of method 292 int displacement = SRegOffset(base_of_code_->s_reg_low); local 294 setup_method_address_[1] = StoreBaseDisp(rs_rX86_SP, displacement, method_start,
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H A D | fp_x86.cc | 160 int displacement = is_double ? dest_v_reg_offset + LOWORD_OFFSET : dest_v_reg_offset; local 161 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_SP.GetReg(), displacement); 162 AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double); 418 int displacement = dest_v_reg_offset + LOWORD_OFFSET; local 420 LIR *fst = NewLIR2NoDest(opcode, rs_rX86_SP.GetReg(), displacement); 421 AnnotateDalvikRegAccess(fst, displacement >> 2, false /* is_load */, is_double /* is64bit */); 628 int displacement = SRegOffset(rl_dest.s_reg_low); local 630 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement, 0x7fffffff); 631 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); 632 AnnotateDalvikRegAccess(lir, displacement >> 692 int displacement = SRegOffset(rl_dest.s_reg_low); local [all...] |
H A D | utility_x86.cc | 394 int displacement = SRegOffset(rl_dest.s_reg_low); local 412 LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value); 414 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 415 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); 423 int displacement = SRegOffset(rl_value.s_reg_low); local 438 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement); 440 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 635 int displacement, RegStorage r_dest, OpSize size) { 653 DCHECK_EQ((displacement & 0x3), 0); 670 DCHECK_EQ((displacement 634 LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_dest, OpSize size) argument 766 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 781 StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size) argument 870 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
H A D | assemble_x86.cc | 613 int32_t raw_base, int32_t displacement) { 663 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { 664 // BP requires an explicit displacement, even when it's 0. 668 size += IS_SIMM8(displacement) ? 1 : 4; 703 // Thread displacement size is always 32bit. 715 // Thread displacement size is always 32bit. 731 // Thread displacement size is always 32bit. 797 // Thread displacement size is always 32bit. 816 // Thread displacement size is always 32bit. 825 // Force the displacement siz 612 ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, int32_t raw_base, int32_t displacement) argument 1324 EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t displacement, int32_t raw_cl) argument [all...] |
H A D | int_x86.cc | 1275 void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { argument 1285 LoadBaseDisp(rs_rX86_SP, displacement, dest, k32, kNotVolatile); 1289 rs_rX86_SP.GetReg(), displacement, val); 1290 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); 1408 int displacement = SRegOffset(rl_src1.s_reg_low); local 1416 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); 1417 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); 1430 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1431 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1511 int displacement local 1533 int displacement = SRegOffset(rl_src1.s_reg_low); local 1544 int displacement = SRegOffset(rl_src2.s_reg_low); local 1567 int displacement = SRegOffset(rl_src1.s_reg_low); local 1612 int displacement = SRegOffset(rl_src.s_reg_low); local 1647 int displacement = SRegOffset(rl_dest.s_reg_low); local 2484 int displacement = SRegOffset(rl_dest.s_reg_low); local 2515 int displacement = SRegOffset(rl_dest.s_reg_low); local 2957 int displacement = SRegOffset(rl_src.s_reg_low); local [all...] |
H A D | target_x86.cc | 917 int displacement = SRegOffset(rl_dest.s_reg_low); local 920 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 921 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 923 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 924 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 1359 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); local 1361 Load32Disp(rs_rX86_SP, displacement, rs_rDI); 2268 int displacement = SRegOffset(rl_result.s_reg_low); local 2269 LIR *l = NewLIR3(extr_opcode, rs_rX86_SP.GetReg(), displacement, rs_src1.GetReg()); 2270 AnnotateDalvikRegAccess(l, displacement >> [all...] |
/art/compiler/jni/quick/ |
H A D | calling_convention.h | 57 // Place iterator at start of arguments. The displacement is applied to 60 void ResetIterator(FrameOffset displacement) { argument 61 displacement_ = displacement;
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/art/runtime/interpreter/ |
H A D | interpreter_goto_table_impl.cc | 2407 int32_t displacement = static_cast<int32_t>(found_dex_pc) - static_cast<int32_t>(dex_pc); local 2408 ADVANCE(displacement);
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/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 825 int displacement, RegStorage r_src_dest, 827 DCHECK_EQ(displacement & 3, 0); 829 int encoded_disp = (displacement & kOffsetMask) >> 2; // Within range of the instruction. 831 if ((displacement & ~kOffsetMask) != 0) { 833 // Add displacement & ~kOffsetMask to base, it's a single instruction for up to +-256KiB. 834 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement & ~kOffsetMask); 843 if ((displacement & ~kOffsetMask) != 0 && !r_work.Valid()) { 850 * Load value from base + displacement. Optionally perform null check 854 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 859 bool thumb2Form = (displacement < 409 824 LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, int displacement, RegStorage r_src_dest, RegStorage r_work) argument 965 LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, VolatileKind is_volatile) argument 995 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 1087 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument [all...] |
/art/disassembler/ |
H A D | disassembler_x86.cc | 1221 int32_t displacement; local 1223 displacement = *reinterpret_cast<const int8_t*>(instr); 1227 displacement = *reinterpret_cast<const int32_t*>(instr); 1230 args << StringPrintf("%+d (", displacement) 1231 << FormatInstructionPointer(instr + displacement)
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/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 1193 * Load value from base + displacement. Optionally perform null check 1197 LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, argument 1249 bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; 1250 int scaled_disp = displacement >> scale; 1254 } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { 1256 load = NewLIR3(alt_opcode, r_dest.GetReg(), r_base.GetReg(), displacement); 1259 // TODO: cleaner support for index/displacement registers? Not a reference, but must match width. 1261 LoadConstantWide(r_scratch, displacement); 1269 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); 1274 LIR* Arm64Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorag argument 1289 LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, VolatileKind is_volatile) argument 1294 StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) argument 1365 StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, VolatileKind is_volatile) argument 1387 StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) argument [all...] |
/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 995 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { argument 996 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile); 999 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { argument 1000 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile); 1002 // Load a reference at base + displacement and decompress into register. 1003 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, argument 1005 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile); 1027 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { argument 1028 return StoreBaseDisp(r_base, displacement, r_src, kWord, kNotVolatile); 1031 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorag argument 1041 Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) argument [all...] |