| /external/qemu/include/exec/ |
| H A D | softmmu_header.h | 89 int mmu_idx; local
93 mmu_idx = CPU_MMU_INDEX;
94 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
96 res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
98 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
110 int mmu_idx; local
114 mmu_idx = CPU_MMU_INDEX;
115 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
118 MMUSUFFIX)(env, addr, mmu_idx);
120 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_inde
137 int mmu_idx; local
[all...] |
| H A D | softmmu_template.h | 147 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, argument
151 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
163 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
166 tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
167 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
176 ioaddr = env->iotlb[mmu_idx][index];
194 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
200 res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
201 res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
212 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retadd
229 helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr) argument
305 MMUSUFFIX(CPUArchState *env, target_ulong addr, int mmu_idx) argument
316 helper_le_lds_name(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr) argument
323 helper_be_lds_name(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr) argument
359 helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, int mmu_idx, uintptr_t retaddr) argument
435 helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, int mmu_idx, uintptr_t retaddr) argument
508 MMUSUFFIX(CPUArchState *env, target_ulong addr, DATA_TYPE val, int mmu_idx) argument
[all...] |
| /external/qemu/target-i386/ |
| H A D | mem_helper.c | 132 void tlb_fill(CPUX86State* env, target_ulong addr, int is_write, int mmu_idx, argument
137 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
|
| H A D | helper.c | 933 int is_write, int mmu_idx)
965 int is_write1, int mmu_idx)
974 is_user = mmu_idx == MMU_USER_IDX;
1230 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
932 cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx) argument
964 cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, int is_write1, int mmu_idx) argument
|
| /external/qemu/ |
| H A D | cputlb.c | 59 int mmu_idx; local
61 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
62 env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
88 int mmu_idx; local
109 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
110 tlb_flush_entry(&env->tlb_table[mmu_idx][
164 int mmu_idx; local
199 tlb_set_page(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) argument
305 int mmu_idx, page_index, pd; local
[all...] |
| H A D | exec.c | 561 int mmu_idx; local
562 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
565 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
615 int mmu_idx; local
616 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
618 tlb_update_dirty(&env->tlb_table[mmu_idx][
633 tlb_set_page_exec(CPUArchState *env, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, int is_softmmu) argument
[all...] |
| /external/qemu/target-mips/ |
| H A D | helper.c | 346 int mmu_idx, int is_softmmu)
424 mmu_idx, TARGET_PAGE_SIZE);
439 int mmu_idx)
452 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
453 __func__, env->active_tc.PC, address, rw, mmu_idx);
471 mmu_idx, TARGET_PAGE_SIZE);
475 ret = cpu_mips_tlb_refill(env,address,rw,mmu_idx,1);
345 cpu_mips_tlb_refill(CPUMIPSState *env, target_ulong address, int rw , int mmu_idx, int is_softmmu) argument
438 cpu_mips_handle_mmu_fault(CPUMIPSState *env, target_ulong address, int rw, int mmu_idx) argument
|
| H A D | op_helper.c | 2094 void tlb_fill (CPUMIPSState* env, target_ulong addr, int is_write, int mmu_idx, argument
2100 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
|
| /external/qemu/target-arm/ |
| H A D | op_helper.c | 78 void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, argument
83 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
|
| H A D | helper.c | 628 int mmu_idx)
1362 int access_type, int mmu_idx)
1369 is_user = mmu_idx == MMU_USER_IDX;
1376 tlb_set_page (env, address, phys_addr, prot | PAGE_EXEC, mmu_idx,
627 cpu_arm_handle_mmu_fault(CPUARMState *env, target_ulong address, int rw, int mmu_idx) argument
1361 cpu_arm_handle_mmu_fault(CPUARMState *env, target_ulong address, int access_type, int mmu_idx) argument
|