/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 357 int scale, OpSize size) { 372 if (!scale) { 375 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale); 410 int scale, OpSize size) { 424 if (!scale) { 427 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale); 356 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument 409 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
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H A D | int_mips.cc | 486 RegLocation rl_index, RegLocation rl_dest, int scale) { 517 if (scale) { 519 OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); 543 LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); 555 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 598 if (scale) { 600 OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); 620 StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); 485 GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_dest, int scale) argument 554 GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) argument
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/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 59 ScaleFactor scale() const { function in class:art::x86::Operand 98 void SetSIB(ScaleFactor scale, Register index, Register base) { argument 100 CHECK_EQ(scale & ~3, 0); 101 encoding_[1] = (scale << 6) | (index << 3) | base; 171 Address(Register index, ScaleFactor scale, int32_t disp) { argument 174 SetSIB(scale, index, EBP); 178 Address(Register base, Register index, ScaleFactor scale, int32_t disp) { argument 182 SetSIB(scale, index, base); 185 SetSIB(scale, index, base); 189 SetSIB(scale, inde [all...] |
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 71 ScaleFactor scale() const { function in class:art::x86_64::Operand 118 void SetSIB(ScaleFactor scale, CpuRegister index, CpuRegister base) { argument 120 CHECK_EQ(scale & ~3, 0); 127 encoding_[1] = (scale << 6) | (static_cast<uint8_t>(index.LowBits()) << 3) | 205 Address(CpuRegister index, ScaleFactor scale, int32_t disp) { argument 208 SetSIB(scale, index, CpuRegister(RBP)); 212 Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) { argument 216 SetSIB(scale, index, base); 219 SetSIB(scale, index, base); 223 SetSIB(scale, inde [all...] |
/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 693 int scale, OpSize size) { 697 bool thumb_form = (all_low_regs && (scale == 0)); 721 if (scale) { 723 EncodeShift(kArmLsl, scale)); 753 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); 759 int scale, OpSize size) { 763 bool thumb_form = (all_low_regs && (scale == 0)); 788 if (scale) { 790 EncodeShift(kArmLsl, scale)); 818 store = NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); 692 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument 758 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument [all...] |
H A D | int_arm.cc | 1294 RegLocation rl_index, RegLocation rl_dest, int scale) { 1313 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1336 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1370 LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); 1382 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1396 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1438 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1459 StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); 1293 GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_dest, int scale) argument 1381 GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) argument
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/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 456 0 /* scale */, 0 /* disp */); 460 0 /* scale */, 0 /* disp */); 512 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); 516 0 /* scale */, value /* disp */); 634 LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, argument 716 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 724 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 726 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 731 load = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 733 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 761 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument 781 StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size) argument 865 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument [all...] |
H A D | assemble_x86.cc | 693 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 699 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 711 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 728 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 741 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 756 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 767 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl 775 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 813 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 824 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 1008 EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int32_t disp) argument 1101 EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument 1130 EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t raw_index, int scale, int32_t disp) argument 1143 EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t raw_reg) argument 1159 EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, int32_t disp, int32_t imm) argument 1526 EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, int32_t raw_index, int scale, int32_t table_or_disp) argument [all...] |
H A D | int_x86.cc | 905 void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { argument 906 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); 2062 RegLocation rl_index, RegLocation rl_dest, int scale) { 2082 data_offset += constant_index_value << scale; 2098 LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); 2111 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 2130 data_offset += constant_index_value << scale; 2154 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); 2156 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); 2061 GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_dest, int scale) argument 2110 GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) argument
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/art/disassembler/ |
H A D | disassembler_x86.cc | 1106 uint8_t scale = (sib >> 6) & 3; local 1118 if (scale != 0) { 1119 address << StringPrintf(" * %d", 1 << scale);
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/art/compiler/dex/quick/arm64/ |
H A D | utility_arm64.cc | 1025 int scale, OpSize size) { 1051 DCHECK(scale == 0 || scale == expected_scale); 1053 (scale != 0) ? 1 : 0); 1094 // This is a tertiary op (e.g. ldrb, ldrsb), it does not not support scale. 1096 DCHECK_EQ(scale, 0); 1099 DCHECK(scale == 0 || scale == expected_scale); 1101 (scale != 0) ? 1 : 0); 1108 int scale) { 1024 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument 1107 LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) argument 1112 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument 1187 StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) argument 1202 int scale = 0; local 1299 int scale = 0; local [all...] |
H A D | int_arm64.cc | 1102 RegLocation rl_index, RegLocation rl_dest, int scale) { 1121 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1145 EncodeShift(kA64Lsl, scale)); 1184 LoadRefIndexed(reg_ptr, As64BitReg(rl_index.reg), rl_result.reg, scale); 1186 LoadBaseIndexed(reg_ptr, As64BitReg(rl_index.reg), rl_result.reg, scale, size); 1199 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1213 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1256 EncodeShift(kA64Lsl, scale)); 1281 StoreRefIndexed(reg_ptr, As64BitReg(rl_index.reg), rl_src.reg, scale); 1283 StoreBaseIndexed(reg_ptr, As64BitReg(rl_index.reg), rl_src.reg, scale, siz 1101 GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_dest, int scale) argument 1198 GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) argument [all...] |
/art/runtime/ |
H A D | thread.h | 508 size_t scale; local 511 scale = 1; 514 scale = pointer_size / sizeof(void*); 518 scale = 1; 521 return ThreadOffset<pointer_size>(base + ((tls_ptr_offset * scale) / shrink));
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/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 1009 int scale) { 1010 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference); 1037 int scale) { 1038 return StoreBaseIndexed(r_base, r_index, r_src, scale, kReference); 1152 int scale, OpSize size) = 0; 1158 int scale, OpSize size) = 0; 1378 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1380 RegLocation rl_index, RegLocation rl_src, int scale, 1008 LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) argument 1036 StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) argument
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