Searched refs:reg_size (Results 26 - 37 of 37) sorted by relevance

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/external/jemalloc/src/
H A Darena.c1588 bin->stats.allocated += i * arena_bin_info[binind].reg_size;
1606 memset((void *)((uintptr_t)ptr + bin_info->reg_size), 0xa5,
1637 size_t size = bin_info->reg_size;
1984 size = bin_info->reg_size;
2251 assert(arena_bin_info[small_size2bin(oldsize)].reg_size
2490 size_t align_min = ZU(1) << (jemalloc_ffs(bin_info->reg_size) - 1);
2502 bin_info->reg_interval = bin_info->reg_size +
2594 bin_info->reg_size = size; \
H A Dctl.c1499 CTL_RO_NL_GEN(arenas_bin_i_size, arena_bin_info[mib[2]].reg_size, size_t)
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vs_emit.c1168 GLuint reg_size )
1174 GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * reg_size;
1187 brw_MUL(p, acc, vp_address, brw_imm_uw(reg_size));
1190 brw_MUL(p, acc, suboffset(vp_address, 4), brw_imm_uw(reg_size));
1208 int reg_size = 32; local
1225 brw_MUL(p, acc, vp_address, brw_imm_uw(reg_size));
1229 brw_MUL(p, acc, suboffset(vp_address, 4), brw_imm_uw(reg_size));
1231 brw_imm_uw(byte_offset + reg_size / 2));
/external/jemalloc/test/unit/
H A Dstats.c267 p = mallocx(arena_bin_info[0].reg_size, 0);
H A Dmallctl.c328 TEST_ARENAS_BIN_CONSTANT(size_t, size, arena_bin_info[0].reg_size);
/external/vixl/src/a64/
H A Ddebugger-a64.cc602 const uint64_t reg_size = target_reg.SizeInBits(); local
604 const uint64_t count = reg_size / format_size;
606 const uint64_t reg_value = reg<uint64_t>(reg_size,
613 uint64_t data = reg_value >> (reg_size - (i * format_size));
/external/chromium_org/v8/src/arm64/
H A Dsimulator-arm64.cc2131 T reg_size = sizeof(T) * 8; local
2137 mask = diff < reg_size - 1 ? (static_cast<T>(1) << (diff + 1)) - 1
2141 mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R));
2142 diff += reg_size;
2170 T result = (static_cast<unsignedT>(src) >> R) | (src << (reg_size - R));
2172 T topbits_preshift = (static_cast<T>(1) << (reg_size - diff - 1)) - 1;
2389 unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits local
2391 double fn_val = fpreg(reg_size, instr->Rn());
2395 case FCMP_d: FPCompare(fn_val, fpreg(reg_size, instr->Rm())); break;
2412 unsigned reg_size local
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H A Dassembler-arm64.cc2265 unsigned reg_size = rd.SizeInBits(); local
2278 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
2300 unsigned reg_size = rd.SizeInBits(); local
2302 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) |
2303 ImmSetBits(imm_s, reg_size) | ImmRotate(imm_r, reg_size) | dest_reg |
2390 unsigned reg_size = rd.SizeInBits(); local
2396 unsigned non_shift_bits = (reg_size - left_shift) & (reg_size - 1);
/external/chromium_org/v8/src/arm/
H A Dsimulator-arm.cc1529 int reg_size,
1541 *end_address = rn_val + (num_regs * reg_size) - reg_size;
1542 rn_val = rn_val + (num_regs * reg_size);
1546 *start_address = rn_val - (num_regs * reg_size);
1547 *end_address = rn_val - reg_size;
1552 *start_address = rn_val + reg_size;
1553 *end_address = rn_val + (num_regs * reg_size);
1527 ProcessPU(Instruction* instr, int num_regs, int reg_size, intptr_t* start_address, intptr_t* end_address) argument
/external/jemalloc/include/jemalloc/internal/
H A Darena.h238 * reg_interval has at least the same minimum alignment as reg_size; this
244 size_t reg_size; member in struct:arena_bin_info_s
249 /* Interval between regions (reg_size + (redzone_size << 1)). */
/external/chromium_org/v8/test/cctest/
H A Dtest-assembler-arm64.cc8573 // * Push <reg_count> registers with size <reg_size>.
8582 int reg_size,
8596 // Work out which registers to use, based on reg_size.
8599 RegList list = PopulateRegisterArray(NULL, x, r, reg_size, reg_count,
8643 __ PushSizeRegList(list, reg_size);
8665 __ PopSizeRegList(list, reg_size);
8683 literal_base &= (0xffffffffffffffffUL >> (64-reg_size));
8754 // * Push <reg_count> FP registers with size <reg_size>.
8763 int reg_size,
8776 // Work out which registers to use, based on reg_size
8580 PushPopJsspSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument
8761 PushPopFPJsspSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument
8933 PushPopJsspMixedMethodsHelper(int claim, int reg_size) argument
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/external/vixl/test/
H A Dtest-assembler-a64.cc7752 // * Push <reg_count> registers with size <reg_size>.
7761 int reg_size,
7774 // Work out which registers to use, based on reg_size.
7777 RegList list = PopulateRegisterArray(NULL, x, r, reg_size, reg_count,
7819 __ PushSizeRegList(list, reg_size);
7841 __ PopSizeRegList(list, reg_size);
7859 literal_base &= (0xffffffffffffffff >> (64-reg_size));
7928 // * Push <reg_count> FP registers with size <reg_size>.
7937 int reg_size,
7950 // Work out which registers to use, based on reg_size
7759 PushPopXRegSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument
7935 PushPopFPXRegSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument
8108 PushPopXRegMixedMethodsHelper(int claim, int reg_size) argument
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