Searched refs:zero (Results 76 - 100 of 972) sorted by relevance

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/external/libcxx/test/containers/sequences/array/array.zero/
H A DAndroid.mk17 test_makefile := external/libcxx/test/containers/sequences/array/array.zero/Android.mk
19 test_name := containers/sequences/array/array.zero/tested_elsewhere
/external/libcxx/test/containers/sequences/dynarray/dynarray.zero/
H A DAndroid.mk17 test_makefile := external/libcxx/test/containers/sequences/dynarray/dynarray.zero/Android.mk
19 test_name := containers/sequences/dynarray/dynarray.zero/default
/external/libcxx/test/utilities/time/time.point/time.point.cons/
H A Ddefault.pass.cpp27 assert(t.time_since_epoch() == Duration::zero());
32 static_assert(t.time_since_epoch() == Duration::zero(), "");
/external/llvm/test/MC/AArch64/
H A Darm64-mapping-within-section.s15 .zero 3
H A Dmapping-within-section.s15 .zero 3
/external/oprofile/events/mips/74K/
H A Devents14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
29 event:0xb counters:0,2 um:zero minimu
[all...]
/external/llvm/test/MC/Mips/
H A Delf-gprel-32-64.s46 addiu $2, $zero, -1
50 daddiu $4, $zero, 8
58 addiu $2, $zero, 1
64 addiu $2, $zero, 3
67 addiu $2, $zero, 2
70 addiu $2, $zero, 7
H A Ddo_switch3.s28 addiu $1, $zero, 2
36 addiu $2, $zero, 4
42 daddiu $3, $zero, 8
52 addiu $2, $zero, 1
56 addiu $2, $zero, 2
60 addiu $2, $zero, 0
64 addiu $2, $zero, 3
H A Dmips-control-instructions.s20 # CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
21 # CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
23 # CHECK32: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
24 # CHECK32: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
26 # CHECK32: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
27 # CHECK32: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
29 # CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
30 # CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
32 # CHECK32: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
33 # CHECK32: tltu $zero,
[all...]
H A Ddo_switch1.s27 addiu $1, $zero, 2
34 addiu $2, $zero, 4
45 addiu $2, $zero, 1
49 addiu $2, $zero, 2
53 addiu $2, $zero, 0
57 addiu $2, $zero, 3
H A Ddo_switch2.s28 addiu $1, $zero, 2
35 addiu $2, $zero, 4
47 addiu $2, $zero, 1
51 addiu $2, $zero, 2
55 addiu $2, $zero, 0
59 addiu $2, $zero, 3
/external/jemalloc/include/jemalloc/internal/
H A Dvalgrind.h33 #define JEMALLOC_VALGRIND_MALLOC(cond, ptr, usize, zero) do { \
35 VALGRIND_MALLOCLIKE_BLOCK(ptr, usize, p2rz(ptr), zero); \
39 zero) do { \
46 if (zero && old_usize < usize) { \
66 if (zero && tail_size > 0) { \
84 #define JEMALLOC_VALGRIND_MALLOC(cond, ptr, usize, zero) do {} while (0)
87 zero) do {} while (0)
H A Dhuge.h12 void *huge_malloc(arena_t *arena, size_t size, bool zero);
13 void *huge_palloc(arena_t *arena, size_t size, size_t alignment, bool zero);
17 size_t extra, size_t alignment, bool zero, bool try_tcache_dalloc);
/external/oprofile/events/x86-64/hammer/
H A Devents23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
24 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
28 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
29 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
34 event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
35 event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimu
[all...]
/external/oprofile/events/x86-64/family11h/
H A Devents25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
26 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
30 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
31 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
46 event:0x47 counters:0,1,2,3 um:zero minimu
[all...]
/external/libcxx/test/numerics/complex.number/complex.ops/
H A Dcomplex_divide_complex.pass.cpp48 case zero:
51 case zero:
55 assert(classify(r) == zero);
58 assert(classify(r) == zero);
71 case zero:
78 assert(classify(r) == zero);
91 case zero:
111 case zero:
131 case zero:
H A Dcomplex_times_complex.pass.cpp50 case zero:
53 case zero:
54 assert(classify(r) == zero);
57 assert(classify(r) == zero);
73 case zero:
74 assert(classify(r) == zero);
93 case zero:
113 case zero:
133 case zero:
/external/compiler-rt/test/asan/TestCases/
H A Dthrow_invoke_test.cc8 static volatile int zero = 0; variable
17 if (zero == 0)
19 else if (zero == 1)
/external/fdlibm/
H A De_atanh.c41 static double zero = 0.0; variable
59 return x/zero;
60 if(ix<0x3e300000&&(huge+x)>zero) return x; /* x<2**-28 */
H A De_log10.c59 static double zero = 0.0; variable
78 return -two54/zero; /* ieee_log(+-0)=-inf */
79 if (hx<0) return (x-x)/zero; /* ieee_log(-#) = NaN */
/external/compiler-rt/lib/builtins/
H A Dfp_mul_impl.inc26 // Detect if a or b is zero, denormal, infinity, or NaN.
38 // infinity * non-zero = +/- infinity
40 // infinity * zero = NaN
45 //? non-zero * infinity = +/- infinity
47 // zero * infinity = NaN
51 // zero * anything = +/- zero
53 // anything * zero = +/- zero
72 // zero
[all...]
/external/valgrind/main/exp-bbv/tests/arm-linux/
H A Dmillion.S17 bne big_loop @ repeat till zero
23 mov r0,#0 @ result is zero
/external/compiler-rt/test/builtins/Unit/
H A Dmuldc3_test.c23 enum {zero, non_zero, inf, NaN, non_zero_nan}; enumerator in enum:__anon19653
29 return zero;
64 case zero:
67 case zero:
68 if (classify(r) != zero)
72 if (classify(r) != zero)
92 case zero:
93 if (classify(r) != zero)
119 case zero:
144 case zero
[all...]
H A Dmultc3_test.c26 enum {zero, non_zero, inf, NaN, non_zero_nan}; enumerator in enum:__anon19655
32 return zero;
67 case zero:
70 case zero:
71 if (classify(r) != zero)
75 if (classify(r) != zero)
95 case zero:
96 if (classify(r) != zero)
122 case zero:
147 case zero
[all...]
H A Dmulxc3_test.c26 enum {zero, non_zero, inf, NaN, non_zero_nan}; enumerator in enum:__anon19656
32 return zero;
67 case zero:
70 case zero:
71 if (classify(r) != zero)
75 if (classify(r) != zero)
95 case zero:
96 if (classify(r) != zero)
122 case zero:
147 case zero
[all...]

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